JPH06268829A - Compressed picture memory controller - Google Patents

Abstract

PURPOSE:To attain coding and decoding simultaneously at a high speed by adopting a bank structure for a picture memory structure corresponding to a coded data structure and controlling the coding and decoding exclusively with respect to the same bank in a picture memory. CONSTITUTION:When original picture data (16Mbyte capacity) of a size A are stored in a 1st bank 5, the original picture data are coded into data in 48 bits width by a coder 2 in the unit of 4X4 blocks. A control section 7 allows a selector 4a to be thrown to the position of a coded output and gives a write signal to DRAMs 5a-5c having a data width of 8 bits each to allow the DRAMs to store the coded data in 48 bits as data in total 24 bits through two writing operations. Then the control section 7 allows a selector 4b to be thrown to the position of a coded output and gives a write signal to DRAMs 6a-6c having a data width of 8 bits each to allow the DRAMs to store the coded data in 48 bits as data in total 24 bits through two writing operations. Simultaneously the coded data stored in the bank 5 are read and decoded. The processing above is applied similarly to a 2nd bank 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus for compressing / decompressing image data, and more particularly to an image compressing / decompressing apparatus in which the data length of coded data is fixed.

[0002]

2. Description of the Related Art Conventionally, a method for editing encoded image data has been proposed, one of which is disclosed in Japanese Patent Laid-Open No. 3-11.
There is one shown in No. 0914. FIG. 2 is a functional block diagram of the method disclosed in Japanese Patent Application Laid-Open No. 3-110914. The image memory compresses image data for one screen in block units in a fixed length and is controlled by a control signal of one system. 1
It is possible to edit the image at the time of decoding by storing the image data in a bank and reading and decoding the coded data in block units.

[0003]

Since the conventional image compression method is configured as described above, in the case where the encoding process and the decoding process of the original image data are simultaneously performed at high speed,
Access arbitration processing for storing the encoded image data in the image memory and reading the encoded data from the image memory is required, which makes it difficult to realize high-speed processing continuously in real time. There is a problem that it becomes complicated.

The present invention has been made in order to solve the above problems, and it is possible to successively encode and decode image data of a plurality of screens without requiring access arbitration processing of an image memory. With the goal. Another object is to perform high-speed storage and reading in the image memory.

[0005]

In order to achieve the above-mentioned object, the image memory according to the present invention has a structure corresponding to a coded data structure of fixed length, and the image memory has one color or one screen. It is composed of a plurality of banks, and the image data storage control unit and the image data read control unit can arbitrarily select one or more banks, and when a plurality of banks are simultaneously selected, they can be treated as continuous banks. To do.
In addition, the configuration is such that the data width when multiple banks are selected simultaneously is multiple. The data line width at this time is configured to be less than or equal to the bit width of the encoded data.

[0006]

The present invention has the above-described structure, and the image memory capable of efficiently storing the fixed length encoded data of the original image and the image memory capable of efficiently reading the fixed length encoded data are independent as banks. Therefore, high-speed processing can be realized at the same time by performing encoding and decoding in different banks. In addition, the encoded data can be stored in and read from the image memory at high speed.

[0007]

EXAMPLES Example 1. FIG. 1 shows a block diagram of a compressed image memory control circuit according to the present invention. In this figure, 1 is an image control block, 2 is an encoder for encoding original image data, 3 is a decoder for decoding encoded data, 4a,
Reference numeral 4b is a selector for selecting whether to store the encoded data from the encoder 2 in the memory or to send the encoded data from the memory to the decoder 3, and 5 is a 2M × 8 16M DRAM 5
A first bank for encoded data storage memory composed of three stones a to 5c, 6 is a 2M × 8 16M DRAM 6a to 6c
A second bank of encoded data storage memory composed of three stones, 7 is an encoder 2, a decoder 3, selectors 4a and 4
b, the first bank 5 and the second bank 6 are control units.

Here, an example is shown in which the original image handles image data corresponding to a capacity of 16 Mbytes for one color of A4 size. The original image data is divided into 4 × 4 16-byte block units, and one block of image data includes a reference level for designating a representative gradation level representative of the gradation level of each pixel in the block and a block. Of the difference value indicating the distribution range of the representative gradation within the block and three-component data of the resolution component indicating which value of the representative gradation of each pixel in the block is fixed length coded, and the size of the three-component data 6 bytes (48 bits), image memory is A4 per bank
It is composed of two banks 5 and 6 each having a capacity for storing one color size, and the input / output data width to the image memory per bank is 24 bits, and one image memory bank is 2M × 8.
The operation will be described based on an example in which the encoding process and the decoding process for one color of the original image data are simultaneously performed in the case of being configured with 3 stones of 16 MDRAM.

First, when storing A4 size original image data in the first bank 5, the original image data is encoded by the encoder 2 into 48-bit wide data in units of 4 × 4 blocks. The control unit 7 selects the encoded output side of this encoded data by the selector 4a, and gives a write signal to the DRAMs 5a, 5b, 5c each having a data width of 8 bits, and operates twice as a total of 24 bits of data. Stores 48 bits of data.

Next, when reading and decoding the A4 size encoded data stored in the first bank 5 and storing the next A4 size original image data in the second bank 6 at the same time, an encoder is used. The 48-bit encoded data encoded by the encoder 2 is encoded by the controller 7 by the selector 4b.
Select the output side of each of the DRs and each has a data width of 8 bits
Write signals to the AMs 6a, 6b, and 6c to give a total of 2
As 4-bit data, 48-bit data is stored by two operations.

Simultaneously with the operation of storing the encoded data in the second bank 6, the encoded data stored in the first bank 5 is read and decoded. In this operation, the control unit 7 selects the read side to the decoder 3 by the selector 4a, and DR
For each block, the encoded data of 48 bits stored in the AMs 5a, 5b, and 5c is read out as 24-bit data by two read operations. Second bank 6
Reading and decoding of encoded data from the first bank 5
The next image data is encoded and stored in the same manner. As described above, the control unit 7 controls the same bank so that the encoder 2 and the decoder 3 do not simultaneously access the same bank.

When the A3 size image data is encoded and stored in the image memory, the control unit 7 selects both the selector 4a and the selector 4b on the output side of the encoder 2 and the first bank. DR of both 5 and second bank 6
A write signal is given to AM to perform write processing. When the encoded data of A3 size stored in the first bank 5 and the second bank 6 is read and decoded, the control unit 7 selects either the selector 4a or the selector 4b on the read side to the decoder 3. Then, the read operation is performed from the DRAMs of both the first bank 5 and the second bank 6. When handling these A3 size image data, the control unit 7 exclusively writes to and from the encoder 2 and to the decoder 3.

In the case of handling an A3 size image, the control unit 7 first selects the first bank 5 for storing and reading the encoded data to and from the second bank, and then the second bank 6 after the series of processing is completed. 2 by selecting
One bank may be treated as one continuous area, or the first bank 5 and the second bank 6 may be simultaneously selected by the control unit 7 and used as a data line having a width twice that of the 24-bit data line. It may be treated as one area having a data width of 48 bits. For example, when storing encoded data, for the encoded data of 48 bits per block, the control unit 7 places the upper 24 bits in the first bank 5 and the lower 2 bits.
4 bits are stored in the second bank 6 by one write operation.

Example 2. In the above-described first embodiment, the example in which the image memory is configured with two banks has been shown, but it may be divided into more banks depending on the size of the encoded data per block. Even when two banks are selected at the same time and the data line width for storing and reading the encoded data is doubled and used, the effect can be obtained even if the banks are divided into two or more banks. In practice, it is efficient to configure with two banks.

Example 3. Although the encoded data of one block of image data is 6 bytes in the above-described first embodiment, the block size and the encoded data size may be any number as long as the encoded data size is a fixed length.

Example 4. In the above-described first embodiment, when an A4 size image is accessed to each bank, 4
2 bits of 8-bit coded data over 24-bit data line
Although the example in which the access is performed in a divided manner is shown, the configuration may be such that the 48-bit width can be accessed once, or the access can be performed three times or more.

Embodiment 5. In the above-described first embodiment, the image memory for one color is shown as an example.
It may be processed as a screen portion, or image memories of a plurality of colors may be simultaneously controlled in parallel.

[0018]

As described above, in the image compression / expansion processing device which encodes the original image data in a fixed length, temporarily stores it in the image memory, and edits it while reading and decoding it. The image memory configuration and the bank configuration are adopted, and the encoding and decoding are exclusively controlled for the same bank in the image memory, so that complicated memory control is not required and high-speed simultaneous encoding and decoding is possible. Can be done. In addition, the image memory configuration and bank configuration corresponding to the encoded data structure are taken, and by controlling multiple banks in parallel, the data width of the image memory can be widened, and the number of access to the image memory can be reduced to achieve high-speed processing. It can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram of a compressed image memory control circuit showing an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional compressed image memory control circuit.

[Explanation of symbols]

 1 Image Control Block 2 Encoder 3 Decoder 4a to 4b Selector 5 Encoded Data Storage Memory First Bank 5a to 5c Encoded Data Storage DRAM 6 Encoded Data Storage Memory Second Bank 6a to 6c Code For storing digitized data 7 controller

Front Page Continuation (72) Inventor Hiroaki Furuta 3-11-17 Chuo, Itami-shi Mitsubishi Electric Semiconductor Software Co., Ltd. (72) Inventor Eisaku Tomita 3-1-117 Chuo, Itami-shi Mitsubishi Electric Semiconductor Software Co., Ltd. In-house (72) Inventor Masaru Onishi 2-14-40 Ofuna, Kamakura-shi Mitsubishi Electric Corporation Life Systems Research Institute

Claims (2)

[Claims] 1. A reference level for designating a representative gradation level that represents the gradation level of each pixel in the block by dividing the original image data into blocks of a small area, and a representative gradation in the block. Of the difference value indicating the distribution range of the pixel and the three-component data of the resolution component indicating which value of each of the pixels in the block is the representative gradation,
In an image compression / expansion processing device that stores component data (hereinafter referred to as encoded data) in an image memory, and reads and decodes the image data, an area in which the image data of one color or one screen can be stored is N (N Is an integer greater than or equal to 2), and each area is configured as N independent banks, and when the N banks are selected, the N banks are defined as consecutive N banks. Controllable means for controlling each of the N banks independently when each bank is selected, and means for selecting at least one or more banks when the encoded data is stored in the image memory, Means for selecting at least one bank when reading encoded data from the image memory; storing the encoded data in the image memory; Readout of the encoded data, compressed image memory control apparatus characterized by having a means for selecting exclusively to the same bank. 2. The original image data is divided into blocks of small areas, a reference level for designating a representative gradation level representative of the gradation level of each pixel in the block, and a representative gradation in the block. Of the difference value indicating the distribution range of the pixel and the three-component data of the resolution component indicating which value of each of the pixels in the block is the representative gradation,
In an image compression / expansion processing device that stores component data (hereinafter referred to as encoded data) in an image memory, and reads and decodes the encoded data, or stores the encoded data in the image memory or reads the encoded data from the image memory. Is the total number of bits of encoded data per block, N
(N is an integer greater than or equal to 2) A means for performing with a data width of 1 /
A means for dividing the image memory into an area capable of storing image data for one color or one screen into N areas, each area being configured as independent N banks, and the bank includes N banks. When N is selected, N banks can be controlled as continuous banks, and when each bank is selected, N banks can be controlled independently, and when the encoded data is stored in the image memory. Is at least 1
Means for selecting one or more banks, means for selecting at least one bank when the encoded data is read from the image memory, storage of the encoded data in the image memory, and the image A compressed image memory control device, comprising means for exclusively reading out the encoded data from the memory for the same bank.