JP2727512B2 - IC pattern design equipment - Google Patents

Description

Detailed Description of the Invention [Table of Contents] Overview Industrial application field Conventional technology Problems to be solved by the invention Means for solving the problem Actions Embodiment (1) One embodiment of the present invention (First and second embodiments) (Fig. 2) Another embodiment of the present invention (Fig. 3) Effects of the Invention [Overview] Regarding an IC pattern design apparatus, an RC pattern of wiring is automatically extracted to obtain an efficient and highly reliable IC pattern. An IC pattern design system that aims to provide an IC pattern design system that can perform design, and that restores the circuit from the IC design pattern and that requires the determination of the RC distribution constant of the wiring when restoring the circuit. A dividing means for dividing the wiring pattern into partial patterns which are not to be subjected to resistance calculation; and a distribution determining method for a predetermined square which is to be subjected to resistance calculation among the partial patterns divided by the dividing means. Resistance determining means for determining a resistance element as the resistance element, and capacitance determining means for determining a capacitance as a distribution constant for each of a predetermined square which is to be subjected to resistance calculation and a partial pattern which is not to be subjected to resistance calculation, divided by the dividing means. Are provided.

[Industrial applications]

The present invention relates to an IC pattern design apparatus, and more particularly to an IC pattern design apparatus that automatically restores an RC distribution constant of a wiring when restoring a circuit from an IC design pattern.

In IC development, layout design is the most important design process in LSI design, and is the work of designing LSI mask patterns. In this case, in order to verify the validity of the design, the circuit and circuit constants are automatically restored from the design pattern, and the restored data is operated by a circuit simulator to check the IC operation. In recent years, with the increasing integration of ICs, narrow and long wiring patterns have been used.In order to perform accurate circuit simulation, the RC distribution constant of the wiring cannot be ignored and the circuit restoration device There is a need to restore the RC distribution constant of the wiring.

[Conventional technology]

In the conventional IC pattern design equipment, the circuit and circuit constants are automatically restored from the design pattern.However, in the restoration circuit, the calculation of the RC distribution constant and the insertion work into the restoration circuit are performed manually every time the circuit is restored. ing. Specifically, an RC network that approximately represents the RC distribution constant is calculated and manually inserted into the restoration circuit.

[Problems to be solved by the invention]

However, in such a conventional IC pattern design apparatus, the work of calculating the RC distribution constant and inserting it into the restoration circuit has to be performed every time the circuit is restored, so the amount of work is large, and the There is a possibility that mistakes may be mixed, and there is a problem that quick and efficient design cannot be performed.

In particular, as the degree of integration of the IC increases, in the circuit simulation of the conventional restoration circuit that ignores the RC distribution constant of the wiring, there are many parts that produce a non-negligible error between the result and the actual operation of the IC, Coping with manual work becomes increasingly difficult.

Therefore, an object of the present invention is to provide an IC pattern design apparatus capable of automatically extracting an RC distribution constant of a wiring and performing efficient and highly reliable IC pattern design.

[Means for solving the problem]

In order to achieve the above object, an IC pattern designing apparatus according to the present invention restores a circuit from an IC pattern and, at the time of restoring the circuit, needs to determine an RC distribution constant of the wiring. A dividing unit that divides the pattern into a predetermined rectangle to be subjected to resistance calculation and a partial pattern that is not to be subjected to resistance calculation; and, among the partial patterns divided by the dividing unit, a predetermined rectangle to be subjected to resistance calculation. Resistance determining means for determining a resistance element as a constant, and capacitance determination for determining a capacitance as a distribution constant for each of a predetermined square and a partial pattern not to be subjected to resistance calculation divided by the dividing means. Means are provided.

[Action]

According to the present invention, the wiring design pattern is divided into a predetermined rectangle to be subjected to the resistance calculation and a partial pattern not to be subjected to the resistance calculation. A resistance element as a constant is determined, and a capacitance as a distribution constant is determined for each of a predetermined square to be subjected to resistance calculation and a partial pattern not to be subjected to resistance calculation.

Therefore, at the time of circuit restoration, the RC distribution constant is automatically extracted and becomes circuit data, thereby improving the IC pattern design efficiency and reliability.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIGS. 1 and 2 show an embodiment of the present invention, which is an apparatus for performing everything from circuit restoration to simulation and verification. FIG. 3 is a block diagram showing the configuration of the IC pattern design device. In this figure, the IC pattern design device is roughly composed of a graphic input device 1 and a verification device 2.

First, the graphic input device 1 includes an auxiliary storage device 3, an auxiliary storage input / output device 4, a CPU 5, a storage device 6, a video RAM 7, a video control device 8, a display 9, a mouse input device 10, a mouse 11, and a keyboard input device. 12, a keyboard 13, a communication input / output device 14, and a communication input / output device 15.

The auxiliary storage device 3 stores the graphics input device control program execution code P1 and the layout pattern data D1, and the CPU 5 sends the IC layout pattern to the program execution code P7 via the auxiliary storage input / output device 4 at the instruction of the designer. Is read into the storage device 6, and various controls of the graphic input device 1 are performed based on the read execution code P1. The IC layout pattern designer can interactively input a layout pattern through the mouse input device 10 using the mouse 11 while watching the pattern displayed on the display 9. Various instructions required for design can be interactively input by the keyboard 13 via the keyboard input device 12. The input layout pattern D1 is held on the auxiliary storage device 3, and the pattern data D1 created on the auxiliary storage device 3 is displayed on the display 9 and the mouse
The correction can be made interactively using the keyboard 11 or the keyboard 13. The video RAM 7 and the video control device 8 are for displaying images on the display 9. Further, the pattern data D1 created on the auxiliary storage device 3 is sent to the verification device 2 via the communication input / output device 14.

The verification device 2 includes a communication input / output device 15, a CPU 16, a main storage device 17, an auxiliary storage input / output device 18, a terminal input / output device 19,
It comprises an auxiliary storage device 20, a keyboard 21 and a display 22. The pattern data D1 sent from the verification device 2 is received by the communication input / output device 15 and stored in the auxiliary storage device 20, and the CPU 16 executes the circuit restoration program execution code P2 (operation control of the present invention) on the auxiliary storage device 20. And reads the data to the main storage device 17 and performs various processes of circuit restoration based on the control code P2 in the main storage device 17. Do. That is, the circuit data D2 restored by processing the layout pattern data D1 of the auxiliary storage device 20
Is created on the auxiliary storage device 20.

Further, regarding the simulation, the CPU 16 reads the simulation program execution code P3 on the auxiliary storage device 20 into the main storage device 17, and reads the simulation program execution code P3 from the main storage device.
The simulation operation is executed based on the control code P2 on the computer 17, the analyzed circuit data D2 is analyzed, and the analysis result D3 is created on the auxiliary storage device 20. Auxiliary storage device 20
The above analysis result D3 is displayed on the display 22 so that the IC layout pattern designer can check whether the analysis result D3 satisfies the design requirements, and if not, the graphic input device 1, the layout pattern on the auxiliary storage device 3 is corrected, and the corrected pattern data D1 created on the auxiliary storage device 3 is transmitted to the verification device 2 via the communication input processing device 14 again. it can. On the other hand, when the condition is satisfied, an IC can be manufactured using the layout data on the auxiliary storage device 3.

 Next, the operation will be described.

The IC layout pattern designer creates a layout pattern using the mouse 11 while watching the pattern displayed on the display 9 of the graphic input device 1, and then sends the pattern data D1 to the verification device 2 to perform circuit restoration.
The RC network is created by restoring the RC distribution constant. Thereafter, the restored circuit is simulated, and it is verified whether or not the result satisfies the design requirement. If the result is not satisfied, the layout pattern is corrected again, and the process is continued until the result is satisfied. Then, an IC is manufactured based on the satisfied layout data.

Here, the present embodiment is characterized in that the circuit restoration processing described above, in particular, circuit data including an RC network which approximately represents the RC distribution constant of the wiring pattern is automatically restored. A description will be given in accordance with the steps shown in FIG.

If there is a wiring pattern 30 as shown in FIG. 2A, first, a rectangle to be subjected to horizontal resistance calculation is obtained from the wiring pattern 20. That is, FIG. 2 (a)
As shown in FIG. 7, a vertical cut line (represented by 34) passing through each vertex and the vertex of the through holes 31, 32, and 33 is provided in the wiring pattern 30, and is divided into trapezoids. There are 13 cut lines. The effective range of the cut line is limited to the inside of the wiring pattern 30, and does not affect other parts of the pattern beyond the pattern boundary. Then
Rectangles i, ii, ii satisfying the following conditions among the generated trapezoids
Let i be the target rectangle for horizontal resistance calculation.

B) The long side is horizontal (horizontal), and includes only actual pattern lines (meaning lines outside the wiring pattern 30).

B) The short side is vertical (vertical) and consists only of cut lines.

C) Do not overlap with through holes 31-33.

Further, the length of the long side is L, and the length of the short side is W.

Next, the process proceeds to the step of FIG.
Obtain the rectangle to be subjected to the vertical resistance calculation from.
That is, a horizontal cut line (represented by 35 as a representative) passing through each vertex of the wiring pattern 30 and the vertex of the through holes 31, 32, and 33 is provided, and is divided into trapezoids.
There are nine cut lines. The effective range of the cut line is limited to the inside of the wiring pattern 30, and does not affect other parts of the pattern beyond the pattern boundary. Next, rectangles iv and v satisfying the following conditions among the generated trapezoids are set as target rectangles for vertical resistance calculation.

B) The long side is vertical (vertical) and is composed of only actual pattern lines (meaning lines outside the wiring pattern 30).

B) The short side is horizontal (vertical) and consists only of cut lines.

C) Do not overlap with through holes 31-33.

Further, the length of the long side is L, and the length of the short side is W.

Next, the process proceeds to the step of FIG.
Obtains a parallelogram to be subjected to oblique resistance calculation from. That is, the target rectangles iv and v for the vertical resistance calculation are graphically subtracted from the wiring pattern 30. Cut lines (represented by 36) passing through the vertices of the subtracted patterns 30a to 30c and the vertices of the through holes 31 to 33 are provided, and are divided into trapezoids. There are 12 cut lines. Note that the effective range of the cut line is limited to the inside of the pattern, and does not affect other parts of the pattern beyond the pattern boundary. A parallelogram vi that satisfies the following condition among the generated trapezoids is set as a target parallelogram for oblique resistance calculation.

B) It is not rectangular.

B) The oblique side is composed of only actual pattern lines.

C) The vertical side is composed of only cut lines.

D) Do not overlap with through holes 31-33.

Further, the length of the oblique side is L, and the length of the vertical side is W.

Next, the process proceeds to the step of FIG. 2 (d), and a partial pattern which is not a resistance calculation target is obtained. That is, the target rectangles i to iii for the horizontal resistance calculation and the parallelogram ii for the diagonal resistance calculation are further subtracted from the pattern subtracted in the above process, to obtain a partial pattern that is not the resistance calculation target. This partial pattern is represented by 41-47. The steps in FIGS. 2A to 2D correspond to blocks that realize the function of the dividing means.

Next, the process proceeds to the step of FIG. 2A, and a connection list of each pattern is created. That is, a connection list is created by assuming that the acquired partial patterns are connected to each other and that the obtained patterns and the through holes 31 to 33 are connected by overlap. Fig. 2 (f)
become that way.

When the partial pattern not to be subjected to the resistance calculation comes into contact with the partial pattern to be subjected to the resistance calculation, the W value of the partial pattern to be subjected to the resistance calculation is subtracted from the total perimeter t of the partial pattern not to be subjected to the resistance calculation. The peripheral length t of the partial pattern for which the resistance was not calculated is set as t. here,
The partial patterns to be subjected to the resistance calculation include rectangles iv for vertical resistance calculation and rectangles i to ii for horizontal resistance calculation.
i and the oblique resistance calculation target quadrilateral vi.

Next, for each of the acquired partial patterns, parameters such as capacitance C, resistance R, area S, and perimeter t are calculated, and a parameter list shown in Table 1 is created. The steps in FIGS. 2 (e) and 2 (f) correspond to blocks realizing the functions of the resistance determining means and the capacity determining means.

 Here, the calculation of the capacitance C is based on the following equation.

C = c1 * S + c2 * t where S: area of each partial pattern t: 2 * L for a partial pattern for which resistance is to be calculated, and for a partial pattern for which resistance is not calculated, the above-described method is used. Calculated c1 * S: Coupling capacitance between the bottom surface of the wiring pattern 30 and the substrate. c1 is a coefficient c2 * t: represents a coupling capacitance between the side surface of the wiring pattern 30 and the substrate. c2 is a coefficient The calculation of the resistance R is performed according to the following conditions.

B) Set to 0 for partial patterns that are not subject to resistance calculation.

B) The horizontal resistance calculation target rectangles i to iii and the vertical resistance target rectangles iv and v are calculated by the following equations.

R = ρ (L / W) where ρ: sheet resistance value Oblique resistance calculation target parallelogram vi is calculated by the following equation.

Where ρ is the sheet resistance The connection list and the parameter list obtained in the above-described steps become an RC network that approximately represents the RC distribution constant of the wiring pattern 30. Therefore, it was done manually
In the present embodiment, the restoration of the RC distribution constant can be automatically extracted and the circuit data including the RC network can be automatically restored, and an efficient IC pattern design can be performed.

In addition, since the RC distribution constant can be automatically extracted, the contribution to the improvement of the reliability of the IC design pattern verification work, the reduction of the work amount, and the work time is great. Unless distribution constants are considered, there are many wiring parts where circuit simulation cannot be performed with sufficient accuracy.
The above effects are remarkable.

Next, FIG. 3 shows another embodiment to which the IC pattern designing apparatus according to the present invention is applied, in particular, an example in which the wiring pattern is an FET.

In FIG. 3 (a), 50 is a wiring pattern made of, for example, Al, 51 and 52 are through holes, 53 is a diffusion region, for example, a source region, 54 is a channel and a portion facing the gate electrode, and 55 is a portion. The through hole overlaps with the diffusion region 53. When there is such an IC design pattern, the wiring pattern 50 is divided into partial patterns by the process described in detail in the above embodiment, and the capacitance C and the resistance R
Is calculated as shown in FIG. 3 (b). When the circuit is restored from this, it becomes as shown in FIG. 3 (c).
Reference numeral 56 denotes an FET including the diffusion region 53 and the channel 54.

In this manner, even with the wiring pattern of the FET of the present embodiment, the same effect can be obtained by automatically extracting the RC distribution constant as in the above embodiment.

〔The invention's effect〕

According to the present invention, when restoring a circuit of an IC pattern,
RC distribution constants can be automatically extracted, and the efficiency of IC pattern design and the reliability of IC pattern design can be improved.

[Brief description of the drawings]

1 and 2 are diagrams showing an embodiment of an IC pattern designing apparatus according to the present invention, FIG. 1 is an overall configuration diagram thereof, FIG. 2 is a diagram showing a process of automatically extracting an RC distribution constant thereof, FIG. 3 is a diagram showing a circuit restoring process of another embodiment of the IC pattern designing apparatus according to the present invention. 1 ... Graphic input device, 2 ... Verification device, 3, 20 ... Auxiliary storage device, 4, 18 ... I / O device for auxiliary storage, 5, 16 ...
... CPU, 6, 17 ... Main memory, 7 ... Video RAM, 8 ...
... Video control device, 9,22 ... Display, 10 ... Mouse input device, 11 ... Mouse, 12 ... Keyboard input device, 13,21 ... Keyboard, 14,15 ... Communication I / O device , 30,50 ... Wiring pattern, 31-33,51,52,55
…… Through hole, 34, 35 …… Cut line, 41-47…
... partial pattern, 53 ... diffusion area, 53, 54 ... channel.

Claims (1)

(57) [Claims] (1) To restore a circuit from an IC design pattern and to determine the RC distribution constant of the wiring when restoring the circuit
In the IC pattern designing apparatus, the dividing means divides the wiring design pattern into a predetermined rectangle to be subjected to resistance calculation and a partial pattern not to be subjected to resistance calculation; The resistance determining means for determining the resistance element as a distributed constant for the predetermined square to be processed, and the predetermined square and the partial pattern which are not to be subjected to resistance calculation divided by the dividing means And a capacitance determining means for determining a capacitance as a distribution constant.