JPH0589198A - Logical simulator - Google Patents

Abstract

PURPOSE:To provide a logical simulation result which is directly connected with an actual circuit and has high accuracy by obtaining a wiring delay value for each different wiring so as to reflect it on simulation. CONSTITUTION:By adding both a wiring delay calculating part 10 which reads a delay information file 14 and then calculates the delay value which will become actual wiring delay and an automatic node generating part 11 which automatically generates node information tables 6, 7 which have delay values for each different wiring and are used in simulation to conventional logical simulation, the logical simulation with higher accuracy is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulator used as means for checking logic operation and timing verification in a logic circuit.

[0002]

2. Description of the Related Art In designing a logic circuit, a logic simulator is often used as a means for checking the logic operation and verifying the timing. FIG. 3 is a flowchart showing the configuration and processing of a conventional logic simulator. In FIG. 3, 8 is a logic circuit input section for reading and inputting a logic circuit whose operation is to be checked, 12 is an element delay calculation section for calculating a delay value of an element forming the logic circuit, and 13 is for the logic circuit. Is a logic simulation execution unit that executes a simulation. Reference numeral 9 denotes a discriminating unit for discriminating whether or not the delay information file 14 is externally provided. Only when the file 14 is present, the element delay calculating unit 12 performs the delay calculation of the delay value of the element. The delay information file 14 stores information that causes delay in signal transmission such as wiring capacitance value and wiring resistance value after the layout of the logic circuit.

Next, the operation will be described. First, the logic circuit input unit 8 reads a logic circuit for which a logic simulation is to be executed. Next, the determination unit 9 determines whether or not there is the delay information file 14, and if there is, the element delay calculation unit 12 calculates the delay for the logic simulation target element and gives an individual delay value. Finally, the logic simulation execution unit 13 executes a logic simulation for the logic circuit based on the delay value, and obtains the simulation result.

[0004]

Since the conventional logic simulator is constructed as described above, detailed delay values due to different wirings cannot be handled, and these delay values are stored in the elements connected to the wirings. It is absorbed and treated as the delay value of the element, which causes a problem that the logic simulation of the actual circuit cannot be performed accurately.

The present invention has been made in order to solve the above-mentioned problems, and can handle the element delay value given to each element and also handle the wiring delay value due to different wirings. It is an object of the present invention to provide a logic simulator having a highly accurate simulation function.

[0006]

A logic simulator according to the present invention is based on a delay information file 14 which stores information such as wiring capacitance value and wiring resistance value after a layout of a logic circuit which causes delay in signal transmission. A wiring delay calculation unit 10 that calculates a delay value that is an actual wiring delay, and an automatic node information table 6 and 7 that automatically stores node information having delay values for different wirings based on the calculation result The node generation unit 11, the element delay calculation unit 12 that calculates the delay value of the element in the logic circuit based on the delay information file 14, the node information tables 6 and 7 and the logic circuit based on the element delay value And a logic simulation execution unit 13 that executes a logic simulation.

[0007]

The wiring delay calculation unit 10 calculates the delay value which is the actual wiring delay based on the delay information file 14. Based on the calculation result, the automatic node generation unit 11 automatically creates the node information tables 6 and 7 storing the node information having different delay values for each wiring. The element delay calculation unit 12 calculates the delay value of the element based on the delay information file 14. The logic simulation execution unit 13 executes a logic simulation for the logic circuit based on the node information tables 6 and 7 and the element delay value. The contents of the node information tables 6 and 7 are reflected as detailed delay values when executing the logic simulation.

[0008]

1 is a flow chart showing the configuration and processing of a logic simulator according to an embodiment of the present invention.
In FIG. 1, 8 is a logic circuit input section for reading and inputting a logic circuit whose operation is to be checked, 9 is a discriminating section for discriminating whether or not there is a delay information file 14 outside, and 10 is an actual circuit based on the delay information file 14. A wiring delay calculation unit for calculating a delay value which becomes a wiring delay, and 11 is an automatic node generation for automatically creating node information tables 6 and 7 storing node information having delay values for different wirings based on the calculation result. , 12 is an element delay calculating section for calculating the delay value of an element in the logic circuit based on the delay information file 14, 1
Reference numeral 3 is a logic simulation execution unit that executes a logic simulation on the logic circuit based on the node information tables 6 and 7 and the element delay value.

FIG. 2 is a circuit diagram of a logic circuit in which logic simulation is executed by the logic simulator of this embodiment. This logic circuit is composed of a NAND element and an AND element. In FIG. 2, 1 is an external input pin, 2
Is an external output pin, 3 is a NAND element, and 4 and 5 are A
It represents an ND element. The NAND element 3 and the AND elements 4 and 5 are constituent elements in this logic circuit, and 6 and 7 are NAND elements 3 created by the automatic node generation unit 11 in FIG. 1 in order to realize the present invention.
Node information table from to element 4 and NAND
It is a node information table from the element 3 to the AND element 5. These node information tables 6 and 7 have wiring delay values.

Next, the operation of the above embodiment will be described with reference to FIGS. In FIG. 1, the logic circuit input unit 8 is as described in the related art. Next, if there is the delay information file 14, the wiring delay calculation unit 10 calculates a delay value that is the actual wiring delay based on the delay information file 14, and the automatic node generation unit 11 calculates the delay value for each different wiring. Node information tables 6 and 7 having Then, the element delay calculation unit 12 calculates the delay value of the element as described in the related art, and finally the logic simulation execution unit 13 determines the wiring delay value and the element delay value indicated by the node information tables 6 and 7. Then, a logic simulation is performed on the logic circuit to obtain a simulation result.

In the embodiment shown in FIG. 2, the delay values are different between the nodes 3-4 and 3-5 for which the wiring delay calculation is performed, because the wirings are different from each other. Therefore, the automatic node generation unit 11 of FIG. 1 creates the node information table 6 for 3-4 and the node information table 7 for 3-5. The calculated delay values for the respective wirings are stored in these node information tables 6 and 7. A logic simulation is executed based on this information. At this time, first, an input pattern signal is input from the external input pin 1 and passes through the NAND element 3 with a delay value. The signal reaching the AND element 4 is delayed by the delay value described in the node information table 6, and the signal reaching the AND element 5 is delayed by the delay value described in the node information table 7. The signal is then AND element 4 and AND
It passes through the element 5 with a certain delay value and the external output pin 2
Appears as a simulation result.

As described above, according to the above-described embodiment, the delay can be handled, and the delay value can be determined by reading the wiring capacitance value, the wiring resistance value, etc. from the outside. A logic simulator with a function that automatically recognizes the difference in the delay value due to the wiring internally from the capacitance value and resistance value between different elements and can perform a highly accurate logic simulation for each different wiring delay. Can be realized.

In the above embodiment, the delay from the NAND element 3 to the AND element 4 and the delay from the NAND element 3 to the AND element 5
The node information tables 6 and 7 are created as delays of the NAND element 3 to the AND element 4 and the NAND element 3
AND element 4 and AND on the path from
It is also possible to divide at the branch point to the element 5 and first obtain the delay values up to the branch point, and create a node information table for them, and in this case also, the same effect as the above-mentioned embodiment can be obtained.

[0014]

As described above, according to the present invention, the delay value which is the actual wiring delay is calculated based on the delay information file, and the node information table having the delay value for each different wiring based on the calculation result. Is created automatically and the logic simulation is executed based on the node information table and the element delay value. Therefore, the element delay value given for each element and the wiring delay value by different wiring can be handled. That is, it is possible to simulate a difference in delay value due to different wirings, and as a result, it is possible to obtain a highly accurate logic simulation that is more suited to an actual circuit than in the past. In particular, it becomes possible to perform a logic simulation in consideration of the RC circuit model, and a simulation result more suited to an actual circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a flowchart showing the configuration and processing of a simulator according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a logic circuit that is logically simulated by the logic simulator of this embodiment.

FIG. 3 is a flowchart showing the configuration and processing of a conventional logic simulator.

[Explanation of symbols]

 6, 7 Node information table 10 Wiring delay calculation unit 11 Automatic node generation unit 12 Element delay calculation unit 13 Logic simulation execution unit 14 Delay information file

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[Procedure amendment]

[Submission date] June 22, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0004

[Correction method] Change

[Correction content]

[0004]

Since INVENTION Problems to be Solved conventional logic simulator is constructed as described above, delay values are not handled in each wiring becomes different <br/> in the same signal, these delay values However, it is absorbed by the element connected to the wiring and is treated as a delay value of the element, which causes a problem that the logic simulation of the actual circuit cannot be performed accurately.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0005

[Correction method] Change

[Correction content]

The present invention has been made in order to solve the above problems, and handles the element delay value given to each element, and at the same time, arranges wirings for different wirings in the same signal. An object of the present invention is to provide a logic simulator that can handle delay values and has a highly accurate simulation function that is more suitable for an actual circuit.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction content]

As described above, according to the above-described embodiment, the delay can be handled, and the delay value can be determined by reading the wiring capacitance value, the wiring resistance value, etc. from the outside. Internally, the difference in the delay value due to the wiring is automatically recognized from the capacitance value and resistance value between different elements, and the wiring delay value is different for each wiring even within the same signal.
It is possible to realize a logic simulator equipped with a function capable of performing a highly accurate logic simulation capable of handling .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

[0014]

As described above, according to the present invention, the delay value which is the actual wiring delay is calculated based on the delay information file, and the node information table having the delay value for each different wiring based on the calculation result. Is created automatically and the logic simulation is executed based on the node information table and the element delay value, so the element delay value given for each element and the wiring delay due to different wiring in the same signal The value can be handled, that is , the difference in delay value due to different wirings in the same signal can be simulated, which enables a highly accurate logic simulation more suitable for an actual circuit than the conventional one. The effect is obtained. In particular, it becomes possible to perform a logic simulation in consideration of the RC circuit model, and a simulation result more suited to an actual circuit can be obtained.

Claims (1)

[Claims] 1. A logic simulator that performs a simulation operation for checking the logic operation and verifying the timing in a logic circuit, which causes a delay in signal transmission such as a wiring capacitance value and a wiring resistance value after the layout of the logic circuit. A wiring delay calculation unit that calculates a delay value that is an actual wiring delay based on a delay information file that stores information, and a node information table that stores node information having delay values for different wirings based on the calculation result An automatic node generator that automatically creates a delay element, an element delay calculator that calculates a delay value of an element in the logic circuit based on the delay information file, and the node information table and the element delay value based on the element delay value. It has a logic simulation execution unit that executes a logic simulation for a logic circuit. A logic simulator to collect.