JPH08263530A - Method for generating model for logic simulation - Google Patents

Abstract

PURPOSE: To extract logic information and delay information from a logic circuit which is already verified and generate the model which has optimized logic representation and is equivalent in logic simulation to the original logic circuit and fast in simulation speed. CONSTITUTION: For the generation of the logic simulation model, the logic circuit 101 which is already verified, a means for logic composition 104 which inputs a circuit designing rule data base 102 and generates representation having logic, extracted from the logic circuit, optimized from the logic circuit 101 and data base 102, and a delay information generating means which generates a delay data base 107 by extracting timing information on the logic circuit 101 are provided; and those results are integrated to provide the model which is equivalent in logic simulation to the input logic circuit and fast.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for creating a logic simulation model, and more particularly to a method for creating a logic simulation model in consideration of timing information.

[0002]

2. Description of the Related Art Conventionally, for board-level logic simulation, the connection information of a verified logic design circuit is modeled to create a logic model, and the logic model is used as a library to perform the logic simulation as it is. Are doing.

As a logic simulation model at the board level, a register transfer level (hereinafter referred to as R
A method of expressing with a TL level model is well known. This RTL-level simulation model can perform high-speed simulation because it represents a logic circuit with a high degree of abstraction. However, the model provided at the RTL level is a parameter of the model regarding timing and detailed operation of the circuit. There was a problem in terms of expression, and it could not be used in functional simulation with severe timing constraints. Also, the method of expressing with a hardware model using an actual semiconductor chip is well known, but this hardware model is limited to modeling because the hardware of the semiconductor chip cannot be obtained when it does not hinder the development process. There was a problem that caused. Therefore, a method is known in which the operation of a logic circuit can be expressed accurately in a logical and timing manner, and is expressed by a software model described by an object code for performing a logic simulation at high speed.

FIG. 9 shows an example of this conventional software simulation model creation flow.

Referring to FIG. 9, first, the creator of the software model constructs a model of the operation of this logic circuit from the specifications of the logic circuit and the data 902 of the logic circuit or macroblock and stores it in the database (step 90).
3). When all the operations are defined, the delay and timing information 904 is added to complete the software simulation model (step 905).

A concrete example of the above-mentioned preparation method is shown in FIGS. FIG. 10 shows the connection information of the logic circuit to be modeled. The model designer uses the logic circuit 1000 shown in FIG.
01, 1002) is expressed by a logic function prepared in the logic simulator (see FIG. 11) and stored in the database. In this example, INV, AND, OR and FF
Is a logical function expression of each gate. Next, the delay value of the gate on the path is added for each propagation path of the signal and the propagated signal value to create timing information. Arrows represent delays of gates and signal lines (see FIG. 12). The logic simulation model shown in FIG. 13 is completed by reconnecting the logic functions shown in FIG. 11 and adding information on the delay value between terminals based on the timing information calculated as described above.

[0007]

However, in the conventional method of manually creating a model, the number of gates to several tens of gates is the limit in order to create a logically and timing-accurate model. Therefore, the actual models are limited to simple logic gates such as AND and OR, and small-scale circuits such as FF and latches.

Further, in order to create a simulation model of a large-scale circuit, this model creating method includes a method of connecting these simple logic gates, FFs, latches, etc. according to the circuit configuration, and an external method. And a method of creating a delay between terminals by adding a gate delay value and a wiring delay value according to a signal propagation path.

That is, when the RTL level model is used in the logic circuit simulation creation method, there is a problem that the model describing the detailed operation is inaccurate in view of the operation and timing at the gate level. It was Furthermore, the conventional software simulation model is created by using the gate level structure as the circuit becomes complicated because the traditional software development method is used. Therefore, the software model includes logical redundancy. There is also a possibility that processing speed will decrease during simulation.

Therefore, an object of the present invention is to cope with speeding up of the logic simulation, and a logic simulation model which is accurate in terms of timing is automatically created using a logic synthesis tool, and a circuit is realized from a verified logic circuit. The present invention is to provide a method for creating a logic simulation model in which the present logic is extracted, optimized and replaced with a logic expression, and at the same time, timing information of a logic circuit is extracted, converted into a database, and timing data is added after a logic operation.

[0011]

A method for creating a model for logic simulation according to the present invention extracts a logic block based on verified logic circuit information, optimizes the number of logic blocks, and makes the logic circuit equivalent to the logic circuit. Logic synthesizing means for creating a logic expression, and timing information is extracted from the logic circuit information, and the propagation time from the input terminal to the output terminal of the logic circuit is delayed based on the timing information according to the path of the circuit configuration of the logic circuit. And delay information creating means for creating information, wherein the output of the delay information creating means is the timing information of the logical expression.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for creating a logic simulation model according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a procedure for creating a logic simulation model according to the present invention.

First, the creation of logical information will be described. A circuit design rule database file 102 used for design verification of the logic circuit 101 is input (step 105).
The file 102 describes circuit design rules, prohibitions, restrictions, etc., and has a structure as shown in FIG. 14, for example. Of these, the element logic information (1401) is used.

In the method for creating the model for logic simulation of this embodiment, when the logic circuit 101 includes sequential elements such as flip-flops, the sequential elements and the combinational circuit 103 between them are divided. Next, the logic of each gate used in the logic circuit 101 is extracted from the file 102 (step 105), and the logic expression of the divided partial circuits is constructed by using the logic synthesizing means 104.

The logic synthesizing means 104 expands the intermediate variable of the multistage logic into positive logic and negative logic by using, for example, the Shannon expansion formula (step 110), and thereby the logic of the divided combinational circuit part is obtained. The number of stages is changed from two to two (step 111), and the logical expression is optimized (step 112). This optimization step (112) is performed by, for example, M
INI-II (T. Sasao, “Imput var
iasignment and output
t phase optimization of PL
A's ", IEEE TC Vol. C-33, No.
10, pp. 879-894, Oct. 1984) may be used. In this optimizing step (112), common factors of logic are grouped, and the logic expression is changed so that the number of logic operations is minimized. By optimizing the combinational logic expression, the amount of calculation can be reduced and the simulation can be sped up. A logic simulation model including logic information of the optimized logic expression is created.

Since the above-mentioned model does not have the delay information of the logic circuit only by the logic information, its accuracy is inaccurate as the logic simulation model. Therefore, the embodiment of the present invention further includes a step of creating delay information from the logic circuit 101 in order to create an accurate logic simulation model.

First, in this embodiment, the logic circuit 101 is provided with the delay information creating means 106 for obtaining the output delay between all external terminals. This delay value calculation uses a static analysis (Srinivas Deva) to obtain the delay value between terminals from the delay value of each gate and signal line without using a test pattern.
das, Kurt Keutzer, SharpMad
lik, “Delay Computation in
Combinatorial Logic Circ
uits: Theory and Algorithm
s ", ICCAD'91, pp.176, 1991) method or a method disclosed in Japanese Patent Application Laid-Open No. 3-33980, in which a delay value is calculated by performing a simulation by using chip layout information together with logical connection information. All the delay values obtained by the delay information creating means 106 are output as a database to the delay database 107. Further, a hash table 108 may be created to search the delay database 107 at high speed.

A logical simulation model is created by adding a mechanism for searching the delay database 107 at high speed using the hash table 108 to the obtained delay data 107 and obtaining an output delay value.

FIGS. 2 to 7 show examples of modeling by the procedure of the embodiment of the present invention shown in FIG. The circuit diagram shown in FIG. 2 is a logic circuit for modeling. This circuit has the same structure as the circuit shown in FIG. The combinational partial circuit (201, 202) sandwiched between the sequential elements and external terminals of the circuit shown in FIG. 2 and the sequential element 203 are divided into respective partial circuits (301, 302) and sequential element 303 as shown in FIG. . Here, the circuit 201 is the circuit 301
Further, the circuit 202 is divided into the circuit 302, and the sequential element 203 is divided into the sequential element 303. Formula 304, Formula 3
Reference numerals 07 are logical expressions of the circuits 301 and 302, respectively. By applying the MINI-II algorithm to Expression 304, Expression 305 is obtained. Expression 306 is obtained by extracting common factors from expression 305. Similarly, Equations 307 to 308 and 309 are obtained. Formula 304,
By the conversion of 305 and 306, the circuit 301 becomes the circuit 401.
Is converted to, and by the conversion of equations 307, 308, and 309,
Circuit 302 is converted to circuit 402.

By the above operation, the logic of the combinational partial circuit is optimized. Then, the logical expression is created by expressing the operation of the combinational partial circuit by using the logical expression such as the expression of the circuit 401 and the expression of the circuit 402 such as the expression 405 (see FIG. 4B).

Next, the delay value between the external terminals is calculated. Referring to FIG. 5, since delay is set only between the clock terminal and the output terminal of the FF 501 in this circuit, the delay is set between the terminal D and the terminal X and between the terminal E and the terminal X in the entire circuit. It Finally, the circuits 401, 402, 40
3 is connected as in the original circuit, and delay values are set between the terminals D and X and between the terminals E and X to obtain the model shown in FIG.

Further, in FIG. 6, the logical functions of the equations 601 and 602 are expressed by a logical expression which is a combination of AND, OR and INVERTER. In the software model, this logical function is represented by BDD (Binary Deci).
(Sion Diagram) and MDD (Multipl)
By using eDecisionDiagram), the logical expression can be made compact, which allows high-speed calculation. For example, a paper entitled "BDD processing technique on a computer" (Shinichi Minato: Information Processing, Vol. 34, No 5, pp. 593-599,
The treatment method according to May 1993) may be applied.

FIG. 7A shows the logic of equation 601. Further, FIG. 7B shows the logic of Expression 602.
BDD expresses variables as nodes and values as branches. Starting from the top contact point, if the value of the variable marked on the round node is 0, the left branch is traced, and if it is 1, the right branch is traced. The logical value marked on the square node that finally arrives becomes the value of the function for the given variable. In the logical operation using BDD, the operation result may be obtained without evaluating all variables, and the operation time can be shortened.

The operation of the logic simulation to which the logic simulation model created by the present invention is applied will be described with reference to FIG.

First, the start of the simulation starts from the signal change of the input pin. In response to this, the event is registered in the event queue (801). Events are sequentially fetched from the event queue (803), and the gates to which the events have propagated are calculated (804). Operation (8
According to 04), it is determined whether or not an event has occurred due to a change in the output value of the gate (805), and if it has occurred, the process returns to event registration (802). If the event does not occur, it is checked whether or not the event remains in the event queue. If the event remains, the process returns to the event extraction (803). If the event does not remain, the output delay value reference ( 807) is performed. The delay database is searched using the hash table (808) created at this time. Finally, the output value and the delay value are passed to the simulator (810), and the simulation using this software model ends.

[0027]

As described above, according to the present invention, since the logic simulation model is created from the verified logic circuit by the logic synthesis and the delay calculation method, the existing logic connection information can be used as it is, and the time is easily and time-consuming. We can provide the best model.

That is, although the logic of the circuit can be optimized by the conventional logic synthesis tool, the delay between the external terminals is calculated according to the route along which the signal propagates. This has the effect of improving the drawback that the correct delay value cannot be obtained due to the change from the present invention.

In the method developed this time, the delay between external terminals is analyzed by the circuit before optimization, the data is stored in a database, and the delay information is added to the logically optimized model at the time of simulation. It is possible to create a logical simulation model that is correct even in delay.

[Brief description of drawings]

FIG. 1 is a flowchart of a method for creating a logic simulation model according to an embodiment of the present invention.

FIG. 2 is a circuit diagram applied to an embodiment of the present invention.

FIG. 3 is a circuit diagram in which circuit division and logic extraction applied to the embodiment are performed.

FIG. 4 is a circuit diagram in which logic optimization is applied to the embodiment.

FIG. 5 is a diagram showing a delay calculation applied to the embodiment.

FIG. 6 is a diagram of a logic simulation model of a circuit applied to the embodiment.

7 is a diagram of a BDD representation of logic to which the embodiment shown in FIG. 4 is applied.

FIG. 8 is a flowchart when the logic simulation model created according to the present invention is operated.

FIG. 9 is a conventional logic simulation model creation flow.

FIG. 10 is a circuit diagram of a conventional technique.

FIG. 11 is a diagram of a logical representation of the prior art.

FIG. 12 is a diagram of a delay calculation according to the related art.

FIG. 13 is a diagram of a conventional logic simulation model.

FIG. 14 is an example of contents of a circuit design rule database.

[Explanation of symbols]

101 Logic Circuit 102 Circuit Design Rule Database 103 Logic Gate 104 Logic Synthesizing Unit 105 Gate Logic Extracting Step 106 Delay Information Creating Unit 107,809 Delay Database 108,808 Hash Table 109 Logic Simulation Model 110 Circuit Development Step 111 Logic Stage Number Changing Step 112 Combinatorial logic optimization step 113 Basic gate and basic block delay time extraction step 114 Input / output terminal delay calculation step 201, 202, 301, 302, 401, 402
Circuit configuration diagram 304 to 309, 404 to 406, 601 to 602
Logical expression 801 to 807,810 Simulation step

Claims (1)

[Claims] 1. A logic synthesizing means for extracting a logic block based on verified logic circuit information and optimizing the number of the logic blocks to create a logic expression equivalent to the logic circuit.
Delay information creating means for extracting timing information from the logic circuit information and creating delay information for the propagation time from the input terminal to the output terminal of the logic circuit according to the path of the circuit configuration of the logic circuit based on the timing information. Prepare,
A method for creating a model for logic simulation, wherein the output of the delay information creation means is used as timing information of the logic expression.