JPH02183554A - Ic pattern design apparatus - Google Patents

Abstract

PURPOSE:To enable effective IC pattern design of high reliability by determining capacitances as distributed constants regarding a specified square as the object for divided resistance calculation and partial patterns which do not become the object for resistance calculation. CONSTITUTION:For a wiring pattern 30, cut lines 34 in the vertical direction are arranged so as to pass each vertex and the vertexes of through holes 31-33, and trapezoid division is performed. The design pattern 30 for wiring is divided into the following; a specified square as the object for resistance calculation, and partial patterns 41-47 which do not become the object for resistance calculation. Resistance elements as distributed constants are determined about the specified square for resistance calculation. Capacitances as the distributed constants are determined about the specified square as the object for resistance calculation and each of the partial patterns which do not become the object for resistance calculation. Thereby, at the time of circuit reconstruction, RC distributed constants are automatically extracted and turn to circuit data, so that the design efficiency and reliability of IC pattern are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Applications Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Examples (1) One Embodiment of the Present Invention (2) Other Implementations of the Present Invention Example Effects of the invention (Figure 1.2) (Figure 3) [Summary] Regarding the IC pattern design device, it automatically extracts the RC distribution constant of wiring to achieve efficient and highly reliable IC pattern design. IC that can be used
The purpose is to provide a pattern design device that restores a circuit from an IC design pattern and that requires the determination of the RC distribution constant of wiring when restoring the circuit.
In the C pattern design device, dividing means divides the wiring design pattern into predetermined rectangles to be subjected to resistance calculation and partial patterns not to be subjected to resistance calculation; For a predetermined rectangle to be subjected to, a resistance determining means for determining a resistance element as a distributed constant, a predetermined rectangle to be subjected to resistance calculation divided by a dividing means, and a partial pattern not to be subjected to resistance calculation. , and capacity determining means for determining the capacity as a distributed constant.

[Industrial application field]

The present invention relates to an IC pattern design device, and more particularly, to an IC pattern design device that automatically restores RC distribution constants of wiring when restoring a circuit from an IC design pattern.

In IC development, layout design is the most important design process in LSI design, and is the work of designing the LSI mask pattern. In this case, in order to verify the validity of the design, the circuit and circuit constants are automatically restored from the design pattern, and a circuit simulator is operated using the restored data to check the IC operation. In recent years, as ICs have become more highly integrated, narrower and longer wiring patterns have come to be used.In order to perform accurate circuit simulation, the RC distribution constant of the wiring cannot be ignored, and circuit restoration equipment is required. There is a need to restore the RC distribution constant of wiring.

[Conventional technology]

Conventional IC pattern design equipment automatically restores the circuit and circuit constants from the design pattern, but in the restoration circuit, the calculation of the RC distribution constant and the insertion into the restoration circuit must be done manually each time the circuit is restored. ing. In detail, the RC that approximately expresses the RC distribution constant is
The circuit network is calculated and manually inserted into the restoration circuit.

[Problem to be solved by the invention]

However, with such conventional IC pattern design equipment, the work required to manually calculate the RC distribution constant and insert it into the restoration circuit each time a circuit is restored requires a large amount of work and requires manual intervention. There was a problem that a quick and efficient design could not be done because there was a possibility of mistakes being made.

In particular, as the degree of integration of ICs increases, circuit simulations of conventional restoration circuits that ignore the RC distribution constants of interconnections tend to produce non-negligible errors between the results and the actual operation of the IC. It becomes increasingly difficult to deal with the problem manually.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an IC pattern design device that can automatically extract RC distribution constants of wiring and design an IC pattern with high efficiency and reliability.

[Means to solve the problem]

In order to achieve the above object, the IC pattern design device according to the present invention restores a circuit from an IC design pattern, and
In an IC pattern design device that requires the determination of RC distribution constants for wiring when restoring a circuit, the wiring design pattern is divided into predetermined rectangles that are subject to resistance calculation and partial patterns that are not subject to resistance calculation. a dividing means; a resistance determining means for determining a resistance element as a distributed constant for a predetermined rectangle to be subjected to resistance calculation among the partial patterns divided by the dividing means; and a resistance calculation target divided by the dividing means; Capacity determining means for determining the capacitance as a distributed constant for each of the predetermined rectangles and partial patterns that are not subject to resistance calculation;
has been established.

[Effect]

In the present invention, a wiring design pattern is divided into a predetermined rectangle that is the target of resistance calculation and a partial pattern that is not the target of resistance calculation, and then the distribution of the predetermined rectangle that is the target of resistance calculation among the partial patterns is A resistance element as a constant is determined, and a capacitance as a distributed constant is determined for each of a predetermined rectangle that is a target of resistance calculation and a partial pattern that is not a target of resistance calculation.

Therefore, during circuit restoration, the RC distribution constants are automatically extracted as circuit data, improving the design efficiency and reliability of IC patterns.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1.2 is a diagram showing an embodiment of the present invention, which is an apparatus that performs everything from circuit restoration to simulator and verification. Third
The figure is a block diagram showing the configuration of an IC pattern design device. In this figure, the IC pattern design device is broadly divided into a graphic input device 1 and a verification device 2.

First, the graphic input device 1 includes an auxiliary storage device 3, an auxiliary storage input/output device 4, a CPU 5, a storage device 6, a video RAM 7,
It is composed of a video control device 8, a display 9, a mouse input device 10, a mouse 11, a keyboard input device 12, a keyboard 13, a communication input/output device 14, and a communication input/output device 15.

The auxiliary storage device 3 stores the graphic input device control program execution code PI and the layout pattern data D1, and the CPU 5 stores the program execution code P7 via the auxiliary storage input/output device 4 according to the instructions of the IC layout pattern designer. It is read into the storage device 6, and various controls of the graphic input device 1 are performed based on the read execution code P1.

In addition, IC layout pattern designers use Display 9.
The layout pattern can be input interactively using the mouse 11 through the mouse input device 1O while looking at the pattern displayed on the screen, and various instructions necessary for pattern design can be input using the keyboard 13. This allows for interactive input via the keyboard input device 12. The input layout pattern DI is held on the auxiliary storage device 3, and the pattern data D1 created on the auxiliary storage device 3 is displayed on the display 9, and can be modified interactively using the mouse 11 and keyboard 13. is now possible. Note that the video RAM 7 and the video control device 8 are for displaying images on the display 9.

Furthermore, the pattern data D1 created on the auxiliary storage device 3 is sent to the verification device 2 via the communication input/output device 14.

The verification device 2 includes a communication input/output device 15, a CPU 16, a main storage device 17, an auxiliary storage input/output device 18, a terminal input/output device 19, an auxiliary storage device 20, a keyboard 21, and a display 22. The pattern data D1 sent from the verification device 2 is received by the communication input/output device 15 and stored in the auxiliary storage device 20. (Includes operation control, and corresponds to the function of realizing dividing means, resistance determining means, and capacity determining means)
is read into the main storage device 17, and the main storage device 17
Various circuit restoration processes are performed based on the above control code P2.

That is, the layout pattern data D1 of the auxiliary storage device 20 is processed and restored circuit data D2 is created on the auxiliary storage device 20.

Furthermore, regarding the simulation, the CPU 16 reads the simulation program execution code P3 on the auxiliary storage device 20 into the main storage device 17, executes the simulation operation based on the control code P2 on the main storage device 17, and restores the simulation program. The resulting circuit data D2 is analyzed and an analysis result D3 is created on the auxiliary storage device 20. The analysis result D3 on the auxiliary storage device 20 is displayed on the display 22 so that the IC layout pattern designer can check whether the analysis result D3 satisfies the design requirements. modifies the layout pattern on the auxiliary storage device 3 using the graphic input device 1, and sends the modified pattern data DI created on the auxiliary storage device 3 again to the verification device 2 via the communication input/output device 14. Can be sent. On the other hand, if the conditions are satisfied, the configuration is such that an IC can be manufactured using the layout data on the auxiliary storage device 3.

Next, the effect will be explained.

The IC layout pattern designer uses the mouse 11 while looking at the pattern displayed on the display 9 of the graphic input device 1.
A layout pattern is created using , and then the pattern data D1 is sent to the verification device 2 to restore the circuit, and at the same time, the RC distribution constants are also restored to create an RC network. After that, the restored circuit is simulated, and it is verified whether the results satisfy the design requirements. If not, the layout pattern is revised again, and the process continues until the design requirements are met. Then, an IC is manufactured based on the satisfied layout data.

Here, this embodiment is characterized by the above-mentioned circuit restoration process, particularly in automatically restoring circuit data including an RC network that approximately represents the RC distribution constant of the wiring pattern, and this is shown in FIG. This will be explained according to the steps shown in .

If there is a wiring pattern 30 as shown in FIG. 2(a), first a rectangle to be subjected to horizontal resistance calculation is obtained from the wiring pattern 30. That is, Fig. 2 (a
), the wiring pattern 30 is divided into trapezoids by providing a vertical cut line (representatively indicated by 34) passing through each apex and the apex of the through holes 31, 32, and 33. Note that there are 13 cut lines. The effective range of the cut line is limited to the inside of the wiring pattern 30, and does not cross the pattern boundary and affect other parts of the pattern.

Next, among the resulting trapezoids, a rectangle that satisfies the following conditions!
s! lx! ! Let f be the target rectangle for horizontal resistance calculation.

b) The long side is oriented sideways (horizontal) and consists only of actual pattern lines (meaning lines outside the wiring pattern 30).

Mouth) The short side is vertical (vertical) and consists only of cut lines.

c) Do not overlap with through holes 31 to 33.

Furthermore, let the length of the long side be W, and let W be the length of the short side.

Next, the process moves to the step shown in FIG. 2(b), and the wiring pattern 30 is formed.
Obtain the rectangle to be used for vertical resistance calculation.

That is, the wiring pattern 30 is divided into trapezoids by providing a horizontal cut line (representatively indicated by 35) passing through each apex of the wiring pattern 30 and the apexes of the through holes 31, 32, and 33. There are nine cut lines. The effective range of the kuft line is limited to the inside of the wiring pattern 30, and does not cross the pattern boundary and affect other parts of the pattern. Next, among the resulting trapezoids, rectangles iv and v that satisfy the following conditions are set as target rectangles for vertical resistance calculation.

b) The long side is vertical (vertical) and consists only of actual pattern lines (meaning lines outside the wiring pattern 30).

Mouth) The short side is horizontal (vertical) and consists only of cut lines.

c) Do not overlap with through holes 31 to 33.

Furthermore, let the length of the long side be W, and let W be the length of the short side.

Next, the process moves to the step shown in FIG. 2(c), and the wiring pattern 30 is formed.
Obtain the parallelogram that is the target of diagonal resistance calculation from . That is, the target rectangles iv and v for vertical resistance calculation are graphically subtracted from the wiring pattern 30. The force/t line passing through the subtracted vertices of patterns 30a to 30C and the vertices of through holes 31 to 33 (representatively 3
6) is provided and divided into trapezoids. The cut line is 1
There are two. Note that the effective range of the cut line is limited to the inside of the pattern, and does not cross the pattern boundary and affect other parts of the pattern. Among the resulting trapezoids, a parallelogram v1 that satisfies the following conditions is set as a target parallelogram for diagonal resistance calculation.

b) It is not rectangular.

Mouth) The diagonal side consists only of actual pattern lines.

C) Vertical sides consist only of cut lines.

2) Do not overlap with through holes 31 to 33.

Furthermore, let the length of the diagonal side be W, and let the length of the vertical side be W.

Next, the process moves to the step shown in FIG. 2(d), and partial patterns that are not subject to resistance calculation are obtained. That is, the target rectangle i = iii for horizontal resistance calculation and the target parallelogram ii for diagonal resistance calculation are further subtracted from the pattern subtracted in the above step to obtain partial patterns that were not subjected to resistance calculation. This partial pattern is represented by 41-47. The steps shown in FIGS. 2(a) to 2(d) above correspond to blocks that realize the function of the dividing means.

Next, the process moves to the step shown in FIG. 2(e), and a connection list for each pattern is created. That is, the connection list is created by assuming that the partial patterns acquired so far are connected to each other by contact, and the acquired patterns and the through holes 31 to 33 are connected by overlap.

When expressed in symbols, it is as shown in FIG. 2(f).

In addition, when a partial pattern that is not the target of resistance calculation comes into contact with a partial pattern that is the target of resistance calculation, subtract the W value of the partial pattern that is the target of resistance calculation from the total circumference t of the partial pattern that is not the target of resistance calculation. Let t be the peripheral surface length of the partial pattern that was not included in the resistance calculation. Here, the partial patterns to be subjected to resistance calculation are vertical resistance calculation object rectangle 1vsv horizontal direction resistance calculation object rectangle i 4
iii and the quadrilateral vi for which the diagonal resistance is calculated.

Next, for each of the obtained partial patterns, the capacity C
Parameters such as 1 resistance R1 area S and peripheral surface length t are calculated, and a parameter list shown in Table 1 is created. 2nd above
The steps in Figures <e> and (f) correspond to blocks that implement the functions of the resistance determining means and the capacitance determining means.

Here, the capacitance C is calculated according to the following formula (2).

C=C1*S+c 2*t・-・・・■However, S: Area of each partial pattern t: For partial patterns that are subject to resistance calculation, 2*L For partial patterns that are not subject to resistance calculation, the above cl*S: Represents the coupling capacitance between the bottom surface of the wiring pattern 30 and the substrate. cl represents a coefficient c2*t: coupling capacitance between the side surface of the wiring pattern 30 and the substrate. C2 is a coefficient, and the resistance R is calculated according to the following conditions.

b) Regarding partial patterns that are not subject to resistance calculation,
Set to 0.

(Example) The horizontal resistance calculation target rectangle i''iii and the vertical resistance calculation rectangle iVsV are calculated using the following formula (2).

R=ρ(L/W)...■ However, ρ: Sheet resistance value Oblique direction resistance Regarding the parallelogram vi to be calculated, the calculation is performed using the following formula (■).

R = ρ ■ ding (L / W) ...... ■ However, ρ: Sheet resistance value (actual, below is blank) Table 1 The connection list and parameter list obtained by the above process are based on the wiring pattern 30 This becomes an RC network that approximately represents the RC distribution constant of . Therefore, in this embodiment, the restoration of the RC distribution constant, which was conventionally performed manually, is automatically extracted.
Circuit data including a C circuit network can be automatically restored, allowing efficient IC pattern design.

In addition, since the RC distribution constant can be automatically extracted, it greatly contributes to improving the reliability of IC design pattern verification work and reducing the amount of work and work time.Especially in recent high-density ICs, wiring RC The above effect is remarkable because there are many wiring parts for which circuit simulation cannot be performed with sufficient accuracy unless distributed constants are taken into account.

Next, FIG. 3 shows another embodiment to which the IC pattern design apparatus according to the present invention is applied, particularly in the case where the wiring pattern is an FET.

In FIG. 3(a), 50 is a wiring pattern made of, for example, A2, 51 and 52 are through holes, 53 is a diffusion region, for example, a source region, 54 is a channel and is a portion facing the gate electrode, and 55 is a This is a through hole that overlaps with the diffusion region 53. When such an IC design pattern exists, the wiring pattern 50 is divided into partial patterns by the process described in detail in the previous embodiment, and the capacitance C1 resistance R of each portion is calculated, as shown in FIG. 3(b). become.

When the circuit is restored from this, it becomes as shown in FIG.
It represents ET.

In this way, even with the wiring pattern of the FET of this embodiment, it is possible to automatically extract the RC distribution constant and obtain the same effect as in the previous embodiment.

〔Effect of the invention〕

According to the present invention, it is possible to automatically extract the RC distribution constant when restoring the circuit of an IC pattern, and it is possible to improve the efficiency of IC pattern design and the reliability of IC pattern design.

[Brief explanation of the drawing]

FIG. 1.2 is a diagram showing an embodiment of the IC pattern design device according to the present invention, FIG. 1 is a diagram of its overall configuration, FIG. FIG. 3 is a diagram showing the circuit restoration process of another embodiment of the IC pattern design apparatus according to the present invention. 1... Graphic input device, 2... Verification device, 3.20... Auxiliary storage device, 4.18... Auxiliary storage input/output device, 5.16
...cpu. 6.17...Main storage device, 7...Video RAM. 8...Video control device, 9.22...Display, 10...Mouse input device, ll...Mouse, 12... Human power device for keyboard, 13.21・
...Keyboard, 14.15...Communication input/output device, 30.50
...Wiring pattern, 31-33.51.52.
55...Through hole, 34.35...
- Cut line, 41-47... Partial pattern, 53... Diffusion area 53. 54... Channel. Figure 2 Figures 41-47: Partial pattern diagram

Claims (1)

[Claims] In an IC pattern design device that restores a circuit from an IC design pattern and, at the time of circuit restoration, requires determination of an RC distribution constant of wiring, the wiring design pattern is used as a resistance calculation target. dividing means for dividing the partial pattern into a predetermined rectangle and a partial pattern that is not subject to resistance calculation; and a capacitance determining means that determines a capacitance as a distributed constant for each of the predetermined rectangles that are divided by the dividing means and are subject to resistance calculation and the partial patterns that are not subject to resistance calculation. An IC pattern design device characterized by: