JP2757544B2 - Electronic circuit design equipment - Google Patents

Description

The present invention is used in an electronic circuit design apparatus that automatically performs circuit design. In particular, the present invention is applied to pattern data of an integrated circuit, a substrate circuit, etc., at the time of design. The present invention relates to an electronic circuit design apparatus having an improved polygonalizing method when display data or exposure data designed as wiring data with a width connecting wirings.

〔Overview〕

The present invention relates to an electronic circuit design apparatus for setting width wiring data with respect to pattern data, wherein the width and vertex coordinate values of the width wiring data are enlarged or reduced in accordance with the minimum resolution and magnification, and then the width is added. It is intended to improve the width accuracy by making it polygonal.

[Conventional technology]

As shown in FIG. 5 (a), the wiring data with width (hereinafter, simply referred to as path data or data) has a data width (W) 53, a vertex number (n) 54, and coordinate values for the vertex number. (P1 to Pn) 55, which are 50 in FIG. 5 (b).
Thus, the polygon data having a constant width such as 52 is displayed on a drawing or a screen in the state of the polygon data 52 or is used as exposure data.

Further, the coordinates of the pattern data have integer values in units of the minimum resolution for processing by the digital computer, and this is the same in drawings and screen displays.

FIG. 6 is a block diagram showing a main part of a conventional electronic circuit designing apparatus.

In this conventional example, the processor (CPU) 101 and the memory (MEM) 1
02, keyboard (KB) 104, display (CRT) 105,
Memory with input / output interface (I / O) 103
Using a database stored in 102, predetermined data is input from a keyboard 104, processed by a processor 101, and a design screen and data of an electronic circuit are output via an input / output interface 103.

FIG. 7 is a block diagram showing a conventional wiring processing unit with a width. Parameter input means 1 for inputting parameters, parameter calculation means 2 for calculating input parameters, wiring data input means 3 for inputting path data, and wiring data polygon means for polygonizing path data 5 and polygon data enlarging means 6 for enlarging and enlarging the polygon data. And each means 1
6 is included in the processor 101 of FIG.

Next, the operation of this conventional example will be described with reference to the flowchart shown in FIG.

After inputting the minimum resolution and the enlargement / reduction ratio at the time of displaying the drawing (step S11), and obtaining the magnification for multiplying the design data coordinate value (step S12), the following processing is performed on the path data. Was. First, the width of the path data and the vertex coordinate values are input (step S13), then the path data is polygonized (step S14), and the polygon data is multiplied by the magnification (step S1).
5) Use polygon data that matches the minimum output resolution.
The above-described processing is repeated until the data ends, and the processing ends (step S16).

[Problems to be solved by the invention]

In the above-described path data slicing method in the conventional electronic circuit design apparatus, assuming that the minimum resolution is 0.5 μm and the path width is 1.5 μm, input data such as the data 62 in FIG. When the width is assigned, the data becomes like data 63. However, since the vertices are not placed on the grid 61 having the minimum resolution, the data is shifted from the original data 63 like the data 64 when the data is put on the grid by rounding off. Then, the magnification 2
Even if the data is multiplied, even though the original data is on the grid as shown at 73 in FIG. 9 (b), the data still remains off as at data 74.

Even when the minimum resolution is 0.5 μm and the path width is 2 μm, the data 83 is obtained by mathematically squaring the portion at an oblique angle of 45 ° as shown in FIG. Similarly, when the data is put on the grid by rounding, the data becomes data 84, and even if the data is multiplied by twice the magnification, as shown in the data 94 in FIG. It is only enlarged.

If the path data is polygonized in this way, the rounding at the time of widthing will cause an error of about (maximum of input resolution) × magnification at the time of output, and it will be further miniaturized in the future
There is a disadvantage in that the effect of rounding on LSI data increases.

The object of the present invention is to eliminate the disadvantages mentioned above,
An object of the present invention is to provide an electronic circuit design device provided with a means for performing wiring with high precision.

[Means for solving the problem]

The present invention provides an electronic circuit design apparatus including a width-based wiring setting unit that sets width-based wiring data including a vertex coordinate group and a width of a reference line for pattern data of an electronic circuit, wherein the width-based wiring setting unit includes: After enlarging or reducing the width-attached wiring data in accordance with the minimum resolution and the magnification, a means for converting the converted data into polygonal data comprising a group of vertex coordinates is provided.

Further, in the present invention, the wiring data conversion element may be wiring data enlarging means for enlarging and calculating a value of the wiring data with width in accordance with a magnification.

Further, in the present invention, the wiring data converting means may be wiring data reducing means for reducing and calculating the value of the wiring data with width in accordance with a magnification.

[Action]

The present invention multiplies input data by a magnification determined from a minimum resolution and a scaling ratio of output data before performing width setting of path data, and forms a polygon by adding a width.

Therefore, when the polygon is formed into polygons, the mathematically polygonized data is placed on the lattice points, but the enlarged polygonized data does not deviate from the lattice points, and the error due to rounding is further enlarged. As a result, the accuracy with width can be further improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a wiring processing unit with a width according to an embodiment of the present invention.

In this embodiment, a parameter input means 1 for inputting an input data resolution, an output data resolution and an enlargement ratio, and a parameter calculation means 2 for calculating a magnification from these parameters.
And an interconnect circuit inputting means 3 for inputting path data, the wiring data enlargement for enlarging and calculating the width and vertex coordinate value of the path data according to the magnification, which is a feature of the present invention. And a wiring data polygonizing means 5 for polygonizing the enlarged path data and outputting vertices. The means 1 to 5 are included in the processor 101 of FIG. 6 showing the electronic circuit designing apparatus of the present invention.

Next, the operation of this embodiment will be described with reference to the flowchart shown in FIG.

First, the resolution of the input data, the resolution of the output data, and the enlargement / reduction ratio are input by the parameter input means 1 (step S1). Next, the parameter calculator 2 determines the conversion magnification of the input / output data coordinate value from the parameters input in step S1 (step S2). Next, path data is input by the wiring data input means 3 (step S3). Next, the width and coordinates input in step S3 are enlarged and converted by the wiring data enlarging means 4 by the magnification obtained in step S2 (step S4). Thereafter, the path data enlarged and converted in step S4 is polygonized by the wiring data polygonizing means 5 (step S5). Then, these processes are performed until the data ends, and the process ends (step S6).

Next, a specific example according to the present embodiment will be described with reference to FIGS. 3 (a) and (b) and FIGS. 4 (a) and (b). Here, the description will be made on the assumption that the minimum resolution is 0.5 μm for both input and output, and the magnification is 2. Therefore, the magnification calculated by the parameter calculation means 2 is 2.

In the wiring example (1) of FIGS. 3A and 3B, the path width is 1.5 μm, and FIGS. 9A and 9B of the conventional example are used.
Is the same as As shown in FIG. 3A, the path width and vertex coordinates of the data 12 are input by the wiring data input means 3. Next, as shown in FIG. 3 (b), the wiring data enlarging means 4 converts the coordinates by a scaling factor to become enlarged data 22 having a width of 3 μm. Then, when it is polygonalized and placed on a grid, it becomes polygonalized data 24. In this case, the data matches the mathematically assigned data 23, and the data is not rounded as shown in FIG. 9 (b).

The wiring example (2) shown in FIGS. 4 (a) and (b) has a path width of 2.0 μm, which is the same as the conventional example shown in FIGS. 10 (a) and (b). Also in this case, similarly, the coordinate data is converted from the path width and the vertex coordinates of the input data 32 shown in FIG. 4A to become the enlarged data 42 having a width of 4 μm shown in FIG. Is polygonized and placed on a grid, resulting in output data 44 that has been polygonized. In this case, the data portion of 45 ° is rounded as in FIG. 10 (b), but the upper and lower sides of the 45 ° portion of the data 44 are mathematically widthened in FIG. 4 (b). It is below data 43,
10 The output data 94 of FIG.
, The result is a more accurate wrapping result.

Although the above embodiment has been described with respect to the case of the enlargement magnification, the same can be applied to the case of the reduction magnification.

〔The invention's effect〕

As described above, according to the present invention, the width and the vertex coordinate values of the path data are enlarged or reduced in accordance with the minimum resolution and the magnification, and then the width is added to form a polygon, so that the width can be more accurately provided. There is an effect that can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a wiring processing unit with a width according to an embodiment of the present invention. FIG. 2 is a flowchart showing the operation. FIGS. 3A and 3B are explanatory diagrams showing a wiring example (1). FIGS. 4A and 4B are explanatory diagrams showing a wiring example (2). FIGS. 5A and 5B are explanatory diagrams showing the structure and graphics of path data used in the present invention. FIG. 6 is a block diagram showing a main part of an embodiment of the present invention and a conventional electronic circuit designing apparatus. FIG. 7 is a block diagram showing a conventional wiring processing unit having a width according to the present invention. FIG. 8 is a flowchart showing the operation. 9 (a) and 9 (b) are explanatory diagrams showing a wiring example (1). FIGS. 10A and 10B are explanatory diagrams showing a wiring example (2). DESCRIPTION OF SYMBOLS 1 ... Parameter input means, 2 ... Parameter calculation means, 3 ... Wiring data input means, 4 ... Wiring data enlargement means, 5 ... Wiring data polygonalization means, 6 ... Polygonal data enlargement means, 11 , 21, 31, 41, 61, 71, 81, 91 ... grid points, 12, 32, 62, 82 (input) data, 13, 23, 3
3, 43, 63, 73, 83, 93 ... (mathematical polygonalized) data, 22, 42, 72, 92 ... (enlarged) data, 24, 44,
74, 94 ... (output) data, 50, 53 ... data width (W), 51, 55 ... vertex coordinates (P1 to Pn), 54 ... number of vertices (n), 52 ... polygon data , 64, 84 ... data (of intermediate polygons), 101 ... processor (CPU), 102 ... memory (MEM), 103 ... input / output interface (I / O), 1
04: Keyboard (KB), 105: Display (CR
T), S1 to S6, S11 to S16 ... steps.

Claims (1)

(57) [Claims] 1. An electronic circuit design apparatus comprising: a width-based wiring setting unit configured to set width-based wiring data including a vertex coordinate group and a width of a reference line with respect to pattern data of an electronic circuit; An electronic circuit design device, comprising: means for enlarging or reducing the width-attached wiring data according to a minimum resolution and a magnification, and then converting the converted data into polygonal data comprising a group of vertex coordinates. .