JP2720838B2 - Data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device in an information processing system, and more particularly to a data transfer device provided with a data buffer for prefetching data read from a main storage device by an input / output device.

[0002]

2. Description of the Related Art Conventionally, this type of data transfer apparatus has been
When an I / O device reads data from main storage,
The data transfer performance between the main storage device and the input / output device has been improved by pre-reading the data in the main storage device.

In a current data transfer device, a system bus connecting a central processing unit and a main storage device is connected to a plurality of channel control devices (a channel control device having one or more input / output devices under its control). I / O doing
In many cases, a bus connection device for connecting the mutual buses is provided between the (Input / Output) bus. This means that in a large-scale system in which a plurality of central processing units, main storage units, and channel control units are present (a system related to the data transfer device; hereinafter, the term "system" is used in the same sense). This is because if the control device has a configuration in which the central processing unit and the main storage device are connected one-to-one, the system performance is reduced.

The present invention is directed to a data transfer apparatus in which the above "data prefetching" is performed and in which the above bus connection device is provided.

Conventionally, in this type of data transfer device, the number of data to be prefetched is a system-specific constant regardless of which data input / output device reads the data in the main storage device. .

That is, in the conventional data transfer device, a memory data read request from a channel control device having an input / output device (hereinafter referred to as a read main input / output device) that is a subject that reads data from a main storage device is provided. Accordingly, the predetermined number of data is pre-read in the data buffer in the bus connection device.

[0007]

In the above-described conventional data transfer apparatus, the number of data to be pre-read becomes a constant unique to the system regardless of which data input / output apparatus is the read-based input / output apparatus. Therefore, in response to a memory data read request from the channel control device, the bus connection device has no choice but to pre-read the fixed number of data from the main storage device. That is, the performance of the read-oriented input / output device (the number of memory read data; the number of data that can be read continuously when the input / output device reads data from the main storage device) is considered in the prefetching of data by the bus connection device. There was no.

Here, usually, the certain number (the number of pre-read data unique to the system) is set in accordance with the largest number of memory read data of a plurality of input / output devices existing in the system related to the data transfer device. Is done.

Therefore, when the channel controller (a channel controller having a read-based input / output device under its control) reads from the main memory a smaller number of data than the number of data previously read into the data buffer (read-based input / output). When the number of memory read data of the device is smaller than the predetermined number), an invalid transfer cycle (a transfer cycle including useless data transfer) occurs between the main storage device and the data buffer in the bus connection device. There was a problem of doing.

In view of the above, it is an object of the present invention to individually determine the number of data to be prefetched for each channel control device and to transmit data from a main storage device to a data buffer (I / O) in a bus connection device.
By controlling the data transfer to the O buffer unit, invalid transfer cycles between the main storage device and the data buffer in the bus connection device can be reduced, and the system performance can be improved. A transfer device is provided.

As a technique relating to the control of pre-reading in the data transfer apparatus, a technique disclosed in Japanese Patent Application Laid-Open No. 5-151138 (data transfer apparatus) is disclosed. However, this prior art is related to prefetch control in a data transfer device having no bus connection device, and has a different configuration from the present invention. Further, the present invention is also different from the technology according to the publication in that the prefetch control based on a specific numerical value “the number of memory read data” is performed. Vague information called "data transfer performance" is used as information that serves as a reference for control.)

[0012]

According to the present invention, there is provided a data transfer apparatus comprising: a plurality of input / output devices; a plurality of channel control devices having the input / output devices subordinate; a central processing unit; a main storage device; Connects an I / O bus connecting a channel control device to a system bus connecting the central processing unit and the main storage device, and controls data transfer between the main storage device and the channel control device An I / O buffer table in the bus connection device for storing the number of memory read data of each of the plurality of channel control devices;
At the time of setting the I / O buffer table, a memory read data number read instruction is issued, and based on the response, the number of memory read data is stored in the I / O buffer table. The central processing unit for issuing a memory data read instruction at the time of reading, and notifying a response indicating the number of memory read data of its own device to the memory read data number read instruction issued from the central processing unit, A channel control circuit in the channel control device for issuing a memory data read request to the bus connection device in response to a memory data read command for an input / output device under the control of the device, and issuance of the memory data read request The number of memory read data of the channel control device having the original channel control circuit is It is obtained from the I / O buffer table, an I / O buffer unit having the size of the number of memory read data is allocated, the data of the main storage device is pre-read in the I / O buffer unit, and the data in the I / O buffer unit is read. The I / O in the bus connection device for outputting data on the I / O bus
An O-buffer control unit; and a data control circuit in the channel control device for inputting data output on the I / O bus by the I / O buffer control unit and transmitting the data to the read-based input / output device.

[0013]

In the data transfer device of the present invention, the I / O buffer table in the bus connection device stores the number of memory read data of each of the plurality of channel controllers, and the central processing unit executes the following processes A and A. Then, the channel control circuit in the channel control device performs the following processes B and B, the I / O buffer control unit in the bus connection device performs the following processes C to C, and performs data control in the channel control device. The circuit inputs the data output on the I / O bus by the I / O buffer control unit and sends the data to the read main input / output device. A At the time of setting the I / O buffer table, a memory read data number read instruction is issued, and based on the response,
The number of memory read data is stored in the / O buffer table. A: A memory data read instruction is issued when data in the main storage device is read by the input / output device. B. In response to a memory read data number read instruction issued from the central processing unit, a response indicating the number of memory read data of the own device is notified. B. A memory data read request is issued to the bus connection device in response to a memory data read command issued from the central processing unit for an input / output device under its control. C Obtain from the I / O buffer table the number of memory read data of the channel control device having the channel control circuit that issued the memory data read request. C Allocate an I / O buffer unit having the size of the number of memory read data. C The data in the main memory is pre-read in the I / O buffer. C Output the data in the I / O buffer unit to the I / O bus.

[0014]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the data transfer device of the present invention.

The data transfer device of this embodiment includes a central processing unit 10, a main storage device 20, a bus connection device 30, a plurality of (here, three) channel control devices 41 to 43,
One or more (here, three) input / output devices 51 to 59 are respectively connected under the control of the channel controllers 41 to 43.
, A system bus 100, and an I / O bus 200. It goes without saying that the numbers of the plurality of channel control devices and the plurality of input / output devices are not limited to the numbers (3 and 9) shown in FIG. In addition, the number of the central processing unit 10 and the number of the main storage devices 20 may be plural.

The central processing unit 10 is a device for performing arithmetic processing, and includes an input / output process (a memory data read process targeted by the present invention) relating to a certain input / output device (any one of the input / output devices 51 to 59). When performing the operation, the channel controller corresponding to the input / output device (the channel control device 41 having the input / output devices 51 to 53 under the control and the input / output devices 54 to 56 under the control of the input / output device via the bus connection device 30). Input / output instruction (a memory data read instruction targeted by the present invention is one of them) to the channel control device 42 having the same or the channel control device 43 having the input / output devices 57 to 59 under its control. Issue.

The main storage device 20 is connected to the central processing unit 10 and the bus connection device 30 via the system bus 100 via a bus, and sends data to the bus connection device 30 according to a request from the bus connection device 30. .

The bus connection device 30 is a system bus 100 connecting the central processing unit 10 and the main storage device 20.
And I / O connecting the channel controllers 41 to 43
The device connects to the bus 200.

The bus connection device 30 is connected to the main storage device 20
Buffer I / O control unit 31 for controlling the pre-reading of the data read from the I / O device to the read main input / output device, and an I / O buffer serving as a data buffer for storing the pre-read data.
Based on an instruction (memory read data number read command) from the buffer unit 32 and the central processing unit 10, the number of memory read data of each of the channel control devices 41 to 43 (memory read data of the input / output device under the channel control device) I / O buffer table 33 for storing the maximum number of numbers)
It is comprised including.

The I / O buffer control unit 31 is provided with a certain channel control device (one of the channel control devices 41 to 43).
When a memory data read request is issued, the number of memory read data of the channel controller is acquired by referring to the I / O buffer table 33, and data corresponding to the number of memory read data is pre-read from the main storage device 20. Then, the data is stored in the I / O buffer unit 32.

The I / O buffer table 33 stores the number of memory read data of the channel control device 41.
A table 331, an I / O table 332 storing the number of memory read data of the channel control device 42, and an I / O table storing the number of memory read data of the channel control device 43.
And an O table 333. In addition, I / O
The number of tables is the same as the number of channel control devices connected to the I / O bus 200, and it is needless to say that the number of tables is not limited to three in FIG.

Channel controllers 41, 42 and 43
Are input / output devices 51 to 53, 54 connected under their own device in accordance with input / output commands from the central processing unit 10.
This is a device for controlling the input and output of data relating to .about.56 and 57.about.59.

When data transfer based on a memory data read command (one of input / output commands) from the central processing unit 10 is performed, the channel controllers 41 to 43 reduce the number of data indicated by the memory data read command. When the transfer performance (the number of memory read data) of the read main input / output device is exceeded, the transfer cycle is divided into several parts, and a request for the right to use the I / O bus 200 is made for each transfer cycle. When one transfer cycle ends, the right to use the I / O bus 200 is relinquished (a plurality of transfer cycles are not generated continuously by one bus use request).

Each channel control device (here, the channel control device 41 will be described as a representative) is configured to include a channel control circuit 411 and a data control circuit 412 (the other channel control devices 42 and 43 also has a similar circuit).

The channel control circuit 411 responds to a memory read data number read instruction from the central processing unit 10.
It has a function of responding as the maximum number of memory read data of the input / output devices 51 to 53 connected under its own device (the own channel control device 41) as the number of memory read data of its own device. I have.

The data control circuit 412 is connected to the I / O bus 20
0 (data from the main storage device 20 in the case where any of the input / output devices 51 to 53 connected under its own device is a read-only input / output device), and inputs the data. To the read-based input / output device.

FIG. 2 is a diagram showing a configuration of a memory read data number read instruction issued from the central processing unit 10 to the channel controllers 41 to 43 and a configuration of a response thereto.

The memory read data number read instruction is EP
U CH # (identification information of the central processing unit (here, the central processing unit 10) that issued the memory read data number read instruction. This information is used to make it possible to cope with a system having a plurality of central processing units. Yes) and CMD
(Command to instruct reading of the number of memory read data)
And PCU CH # (identification information of the channel control device to which the memory read data number read instruction is issued).

The response to the memory read data number read instruction includes control data indicating the number of memory read data of the channel control device (any one of the channel control devices 41 to 43) to which the memory read data number read instruction is issued. I have. Here, the control data is represented by the least significant byte of the response (the other three bytes are RFU (R
Elevate For Use), and the lower two bits in the one byte represent the number of memory read data.

The central processing unit 10 issues a memory read data number read instruction shown in FIG. 2 to each of the channel controllers 41 to 43, and the control data in the response shown in FIG.
When the control data is “01h”, 4 bytes are determined as the number of memory read data of the channel control device that is the source of the response (the destination of the read command of the number of memory read data). When the control data is "10h", 256 bytes are determined as the number of memory read data (see FIG. 2), and the I / O in the bus connection device 30 is determined.
The number of memory read data is stored in a corresponding I / O table (one of I / O tables 331 to 333) in the O buffer table 33.

In this embodiment, the number of memory read data is assumed to be one of 4, 64 and 256 bytes. It goes without saying that the types are not limited to these (however,
The three types of numerical values in the present embodiment are appropriate from an actual operation).

FIG. 3 is a flowchart showing the processing of the data transfer device of the present embodiment.

FIG. 3A is a flowchart showing the processing of the data transfer apparatus of this embodiment when a memory read data number read instruction is issued (when the I / O buffer table 32 is set). This processing includes a memory read data number read instruction issuing step 301 and a response notifying step 302.
And a memory read data number storage step 303.

FIG. 3B shows a state when a memory data read instruction is issued (when any of the input / output devices 51 to 59 is in the main storage device 2).
9 is a flowchart showing processing of the data transfer device of the present embodiment when data is read from 0). This processing includes a memory data read command issue step 304, a memory data read request issue step 305, an I / O table reference step 306, and a data transfer control step 307.
And an I / O bus data transmission step 308 and an end report notification step 309.

Next, the operation of the data transfer apparatus according to the present embodiment thus configured will be described.

First, the operation at the time of issuing the memory read data number read instruction (when setting the I / O buffer table 32 at the time of system startup, etc.) will be described (see FIG. 3A).

The central processing unit 10 includes a system bus 10
0, to each of the channel control devices 41 to 43 via the bus connection device 30 and the I / O bus 200 (here, the case of “to the channel control device 41” will be described as a representative). A memory read data number read instruction as shown in FIG. 2 is issued (step 301).

The channel control circuit 411 in the channel control device 41 responds to this memory read data number read instruction by reading the number of memory read data of its own device (the channel control device 41 including itself). A response (see FIG. 2) indicating the maximum number of memory read data of the input / output devices 51 to 53 (see FIG. 2) is sent to the central processing unit 10 via the I / O bus 200, the bus connection device 30, and the system bus 100. (Step 302).

The central processing unit 10 stores the number of memory read data in the response to the I / O table 331 (I / O table corresponding to the channel control unit 41) in the I / O buffer table 33 in the bus connection unit 30. (Step 303).

Such processing is performed for all the channel controllers connected to the I / O bus 200. That is, the number of memory read data of the channel control device 42 is determined by the I / O table 332 (the channel control device 42).
Is stored in an I / O table corresponding to the I / O table 33).
3 (I / O table corresponding to channel control device 43)
Is stored in

Second, the operation when a memory data read instruction is issued (when the data in the main storage device 20 is read by the input / output device (any of the input / output devices 51 to 59)) will be described (FIG. 3B). )reference). Here, the operation when the input / output device 51 is a read-based input / output device will be described.

The central processing unit 10 includes a system bus 10
0, the channel controller 41 (the channel controller having the input / output device 51 which is a read / input device) under the control of the read / output device via the bus connection device 30 and the I / O bus 200. The specified memory data read command is issued (step 304).

When the channel control circuit 411 in the channel control device 41 decodes the memory data read command and recognizes that the memory data read command is to use the input / output device 51 as a read main input / output device, I /
A memory data read request to the bus connection device 30 via the O bus 200 (from the main storage device 20 to the input / output device 51
(A memory data read request for transferring data) is issued (step 305).

Upon receiving the memory data read request from the channel control device 41, the I / O buffer control unit 31 in the bus connection device 30 determines that the memory data read request is from the channel control device 41. I / O table 3 corresponding to the channel controller 41 based on the
31 (step 306).

Further, based on the number of memory read data stored in the I / O table 331 referred to in step 306, the I / O buffer control unit 31 stores the data in the main storage device 20 which is the target of the memory data read instruction. (Step 307) is performed as follows.

The I / O buffer unit 32, which is a data buffer for storing data corresponding to the number of memory read data, is allocated in the bus connection device 30.

Via the system bus 100, the data corresponding to the number of the memory read data is pre-read into the I / O buffer unit 32 allocated from the main storage device 20.

At the same time, the I / O bus 200
The data in the buffer unit 32 is output.

The data control circuit 412 in the channel control device 41 inputs the data output on the I / O bus 200 and sends the data to the input / output device 51 which is a read-based input / output device (step). 308).

The channel control circuit 411 in the channel control device 41 completes the data transfer indicated by the memory data read instruction as described above (when the amount of data to be transferred is large and a plurality of transfer cycles occur). When the data transfer is realized, after all the transfer cycles are completed), a completion report indicating the completion is sent to the central processing unit 10 via the I / O bus 200, the bus connection device 30, and the system bus 100. Notification is made to the user (step 309).

Upon receiving the end report, the central processing unit 10 shifts the control to the execution of processing subsequent to the memory data read processing.

[0053]

As described above, the data transfer device of the present invention supports a memory read data number read instruction for setting the number of memory read data of each channel control device in the I / O buffer table, and By referring to the I / O buffer table at the time of issuing the data read instruction, the bus connection device can determine the appropriate number of data to be prefetched in consideration of which input / output device is the read main input / output device. Become like Therefore, according to the present invention, an invalid transfer cycle between the main storage device and the data buffer (I / O buffer unit) in the bus connection device can be reduced, and the system performance can be improved. Occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data transfer device of the present invention.

FIG. 2 is a diagram showing a configuration of a memory read data number read instruction handled by the data transfer device shown in FIG. 1 and a response thereto.

FIG. 3 is a flowchart showing a process of the data transfer device shown in FIG. 1;

[Explanation of symbols]

Reference Signs List 10 central processing unit 20 main storage device 30 bus connection device 31 I / O buffer control unit 32 I / O buffer unit 33 I / O buffer table 41, 42, 43 channel control device 51, 52, 53, 54, 55, 56 , 57,58,5
9 I / O device 100 System bus 200 I / O bus 331, 332, 333 I / O table 411 Channel control circuit 412 Data control circuit

Claims (3)

(57) [Claims] 1. An I / O bus connecting a plurality of input / output devices, a plurality of channel control devices having the input / output devices under control, a central processing unit, a main storage device, and the channel control devices. A data transfer device comprising a bus connection device that connects a system bus connecting the central processing unit and the main storage device and controls data transfer between the main storage device and the channel control device; An I / O buffer table in the bus connection device for storing the number of memory read data of each of the plurality of channel control devices; and issuing a memory read data number read command when the I / O buffer table is set and responding Based on said I
A central processing unit that stores the number of memory read data in an I / O buffer table and issues a memory data read command when the data in the main storage device is read by the input / output device; and a memory that is issued from the central processing device. In response to a read data number read command, a response indicating the number of memory read data of the own device is notified, and the bus connection device is issued in response to a memory data read command for an input / output device under the control of the own device issued from the central processing unit. A channel control circuit in the channel control device that issues a memory data read request to the I / O buffer table, and a channel control circuit in the channel control device having the channel control circuit that issues the memory data read request. From the I / O buffer unit having the size of the number of memory read data. Te, pre-read data stored in the main storage to the I / O buffer section, the data in the I / O buffer section I /
An I / O buffer control unit in the bus connection device for outputting on the O bus, and data output on the I / O bus by the I / O buffer control unit and input to the read-only input / output device A data control circuit in the channel control device. 2. The memory read data number read instruction includes “identification information of a central processing unit that has issued the memory read data number read instruction”, “command for instructing read of the memory read data number”, and “memory read data number read command”. 2. The data transfer device according to claim 1, comprising "identification information of a channel control device to which the number read command is issued." 3. The memory controller according to claim 1, wherein the number of memory read data of each channel controller is any one of 4, 64, and 256 bytes.
A data transfer device according to claim 1.