JPH096704A - Data transfer device - Google Patents

Abstract

PURPOSE: To reduce the cycle of invalid transfer between a main storage device and a data buffer inside a bus connector. CONSTITUTION: An I/O buffer table 33 stores the number of memory read data of respective channel controllers 41-43. Based on the response of a memory read data number reading instruction, a central processing unit(CPU) 10 stores the number of memory read data in the I/O buffer table 33. Corresponding to a memory data read instruction on input/output devices 51-53 issued from the CPU 10, a channel control circuit 411 issues a memory data read request to a bus connector 30. An I/O buffer control part 31 acquires the number of memory read data of channel controllers 41-43 at the issue source of memory data read request and performs the allocation of an I/O buffer part 32 and control of look-ahead of data of a main storage device 20 based on that numerical value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer device in an information processing system, and more particularly to a data transfer device provided with a data buffer for prefetching data read by an input / output device from a main storage device.

[0002]

2. Description of the Related Art Conventionally, this type of data transfer device has been
When the I / O device reads data from the main memory,
By prefetching the data in the main storage device, the data transfer performance between the main storage device and the input / output device has been improved.

Further, in the present data transfer apparatus, a system bus connecting the central processing unit and the main memory unit and a plurality of channel control units (channel control units having one or more input / output units under the control) are connected. I / O
In many cases, a bus connection device for connecting the buses to each other is provided between the (Input / Output) bus. This is a channel in a large-scale system (a system related to the data transfer device; hereinafter, the term "system" is used in a similar sense) having a plurality of central processing units, main storage devices, and channel control devices. This is because the system performance deteriorates if the control device has a one-to-one connection with the central processing unit and the main storage device.

The present invention is directed to a data transfer device in which "prefetching of data" as described above is performed and which is provided with the bus connection device as described above.

Conventionally, in this type of data transfer device, the number of data to be prefetched is a constant number peculiar to the system regardless of which data input / output device reads the data in the main storage device. .

That is, in the conventional data transfer device, a memory data read request is issued from a channel controller having an input / output device (hereinafter referred to as a read main input / output device) which is a main body for reading data in the main storage device. Accordingly, the data buffer in the bus connection device is prefetched for the predetermined number of data.

[0007]

In the above-mentioned conventional data transfer device, the number of data to be prefetched becomes a constant number unique to the system regardless of which data input / output device is the read main input / output device. Therefore, in response to a memory data read request from the channel control device, the bus connection device has no choice but to pre-read the fixed amount of data from the main storage device. That is, the performance of the read main input / output device (the number of memory read data; the number of data that can be continuously read when the input / output device reads data from the main storage device) is considered in the prefetch of data by the bus connection device. There was no.

Here, the fixed number (the number of pre-read data unique to the system) is usually set in accordance with the maximum number of memory read data of a plurality of input / output devices existing in the system related to the data transfer device. To be done.

Therefore, when the channel control device (the channel control device having a read main input / output device under it) reads from the main storage device a smaller number of data than the number of prefetched data in the data buffer (read main input / output) When the number of memory read data of the device is smaller than the certain number), an invalid transfer cycle (transfer cycle including useless data transfer) occurs between the main memory device and the data buffer in the bus connection device. There was a problem to do.

In view of the above points, an object of the present invention is to individually judge the number of data to be preread for each channel control device, and to determine the data buffer (I / I) in the bus connection device from the main storage device.
By controlling the data transfer to the O buffer unit), it is possible to reduce an invalid transfer cycle between the main storage device and the data buffer in the bus connection device, and to improve the system performance. To provide a transfer device.

As a technique for controlling prefetching in the data transfer device, a technique disclosed in Japanese Patent Application Laid-Open No. 5-151138 (data transfer device) is disclosed. However, this conventional technique is a technique relating to the prefetch control in a data transfer device having a configuration in which a bus connection device does not exist, and its configuration is different from that of the present invention. The invention of the present application is also different from the technique according to the publication in that the read-ahead control is performed based on the “number of memory read data”, which is a specific numerical value. The vague information called "data transfer performance" is used as the information that serves as a reference for control).

[0012]

A data transfer apparatus according to the present invention comprises a plurality of input / output devices, a plurality of channel control devices having the input / output devices under its control, a central processing unit, a main storage device, and An I / O bus connecting a channel controller and a system bus connecting the central processing unit and the main memory are connected to control data transfer between the main memory and the channel controller. And a bus connection device for controlling the I / O buffer table in the bus connection device for storing the number of memory read data of each of the plurality of channel control devices.
When the I / O buffer table is set, a memory read data number read command is issued, and based on the response, the memory read data number is stored in the I / O buffer table, and the I / O device stores the data in the main memory device. The central processing unit that issues a memory data read command at the time of reading, and sends a response indicating the number of memory read data of its own device to the memory read data number read command issued from the central processing unit, and the central processing unit A channel control circuit in the channel control device that issues a memory data read request to the bus connection device in response to a memory data read command related to an input / output device under its own device issued by The number of memory read data of the channel control device having the original channel control circuit is set in advance. It is acquired from the I / O buffer table, an I / O buffer unit having the size of the memory read data number is allocated, the data of the main storage device is prefetched to the I / O buffer unit, and the data in the I / O buffer unit is read. I / O in the bus connection device for outputting data on the I / O bus
An O buffer control unit and a data control circuit in the channel control device for inputting the data output on the I / O bus by the I / O buffer control unit and sending it to the read main input / output device.

[0013]

In the data transfer device of the present invention, the I / O buffer table in the bus connection device stores the number of memory read data of each of the plurality of channel control devices, and the central processing unit performs the following processes A and A. Then, the channel control circuit in the channel control device performs the following processes B and B, the I / O buffer control unit in the bus connection device performs the following processes C to C, and controls the data in the channel control device. The circuit inputs the data output on the I / O bus by the I / O buffer control unit and sends it to the read main input / output device. At the time of setting the I / O buffer table, the memory read data number read command is issued and I
Store the number of memory read data in the / O buffer table. A A memory data read command is issued when the I / O device reads data in the main memory. B In response to a memory read data number read command issued from the central processing unit, a response indicating the number of memory read data of its own device is notified. B A memory data read request is issued to the bus connecting device in response to a memory data read command issued by the central processing unit for the input / output device under its own device. C The number of memory read data of the channel control device having the channel control circuit that issued the memory data read request is acquired from the I / O buffer table. C Allocate an I / O buffer unit having the size of the memory read data number. C The data in the main storage device is prefetched to the I / O buffer unit. C Outputs the data in the I / O buffer section to the I / O bus.

[0014]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the data transfer apparatus of the present invention.

The data transfer apparatus of this embodiment comprises a central processing unit 10, a main storage unit 20, a bus connection unit 30, a plurality of (here, three) channel control units 41 to 43, and
Input / output devices 51 to 59 connected to each of the channel control devices 41 to 43 by one or more (here, 3).
And a system bus 100 and an I / O bus 200. Needless to say, the numbers of the plurality of channel control devices and the plurality of input / output devices are not limited to the numbers (3 and 9) shown in FIG. Further, the number of central processing units 10 and main storage units 20 may be plural.

The central processing unit 10 is a device for performing arithmetic processing, and it is an input / output processing relating to a certain input / output apparatus (any of the input / output apparatuses 51 to 59) (the memory data read processing which is the object of the present invention is also part 1). Channel control device corresponding to the input / output device (the channel control device 41 having the input / output devices 51 to 53 under its control and the input / output devices 54 to 56 under the control of the input / output device 51) via the bus connection device 30. An input / output command (a memory data read command targeted by the present invention is one of them) is also issued to the channel control device 42 that it has and any of the channel control devices 43 that have the input / output devices 57 to 59 under it. Issue.

The main storage device 20 is bus-connected to the central processing unit 10 and the bus connecting device 30 via the system bus 100, and sends data to the bus connecting device 30 in response to a request from the bus connecting device 30. .

The bus connection device 30 is a system bus 100 connecting the central processing unit 10 and the main storage device 20.
And the I / O connecting the channel control devices 41 to 43
It is a device for connecting to the bus 200.

The bus connection device 30 is a main storage device 20.
I / O buffer control unit 31 for controlling prefetching of data read from the read main input / output device and I / O which is a data buffer for storing the prefetched data
Based on an instruction (memory read data number read instruction) from the buffer unit 32 and the central processing unit 10, the number of memory read data of each channel control device 41 to 43 (memory read data of an input / output device under the control of the channel control device). I / O buffer table 33 for storing the maximum number)
It is comprised including.

The I / O buffer controller 31 is a channel controller (one of the channel controllers 41 to 43).
When a memory data read request is issued from the main memory device 20, the memory read data number of the channel control device is acquired by referring to the I / O buffer table 33, and the data corresponding to the memory read data number is preread from the main storage device 20. And stores it in the I / O buffer section 32.

The I / O buffer table 33 stores the number of memory read data of the channel controller 41.
A table 331, an I / O table 332 that stores the number of memory read data of the channel controller 42, and an I / O table that stores the number of memory read data of the channel controller 43.
And an O table 333. I / O
It goes without saying that the number of tables is the same as the number of channel control devices connected to the I / O bus 200, and is not limited to 3 in FIG.

Channel controllers 41, 42 and 43
Is an input / output device 51 to 53, 54 connected under its own device in accordance with an input / output command from the central processing unit 10.
This is a device for controlling the input / output of data relating to 56 to 57 and 57 to 59.

The channel control devices 41 to 43, when the data transfer based on the memory data read command (one of the input / output commands) from the central processing unit 10 is performed, determine the number of data specified by the memory data read command. When the transfer performance (the number of memory read data) of the read main input / output device is exceeded, the transfer cycle is divided into several, and the right to use the I / O bus 200 is requested for each transfer cycle. When one transfer cycle ends, the right to use the I / O bus 200 is abandoned (a plurality of transfer cycles are not continuously generated by one bus use request).

Each channel control device (here, the channel control device 41 is representatively described) is configured to include a channel control circuit 411 and a data control circuit 412 (other channel control devices 42 and 42). 43 also has a similar circuit).

The channel control circuit 411 responds to the memory read data number read command from the central processing unit 10.
It has a function of responding the maximum number of the memory read data numbers of the input / output devices 51 to 53 connected to the own device (the own channel control device 41) as the memory read data number of the own device. There is.

The data control circuit 412 is connected to the I / O bus 20.
0 (data from the main storage device 20 when any of the input / output devices 51 to 53 connected under its own device is a read-based input / output device) is input and the data is output. Is sent to the lead-based input / output device.

FIG. 2 is a diagram showing the structure of the memory read data number read command issued from the central processing unit 10 to the channel control devices 41 to 43, and the structure of its response.

The memory read data number read command is EP
U CH # (identification information of the central processing unit (here, the central processing unit 10) that has issued the memory read data number reading instruction. This information is used to support a system having a plurality of central processing units. Yes, and CMD
(Command for instructing to read the number of memory read data)
And PCU CH # (identification information of the channel control device to which the memory read data number read command is issued).

The response of the memory read data number read command includes control data indicating the number of memory read data of the channel control device (one of the channel control devices 41 to 43) to which the memory read data number read command is issued. There is. Here, the control data is represented by the least significant 1 byte of the response (the other 3 bytes are RFU (R
The number of memory read data is represented by the lower 2 bits in the 1 byte.

The central processing unit 10 issues the memory read data number read instruction shown in FIG. 2 to each of the channel control units 41 to 43, and the control data in the response shown in FIG.
When "h", 4 bytes are determined as the memory read data number of the channel control device that is the issuer of the response (issue destination of the memory read data number read instruction), and when the control data is "01h", 64 bytes are determined. The number of memory read data is determined, and when the control data is “10h”, 256 bytes is determined as the number of memory read data (see FIG. 2).
The memory read data number is stored in the corresponding I / O table (one of I / O tables 331 to 333) in the O buffer table 33.

In the present embodiment, the number of memory read data is 4 bytes, 64 bytes or 256 bytes, but the number of memory read data which can be set by the data transfer device of the present invention and It goes without saying that the types are not limited to these (however,
The three types of numerical values in this embodiment are appropriate in actual operation).

FIG. 3 is a flow chart showing the processing of the data transfer apparatus of this embodiment.

FIG. 3A is a flow chart showing the processing of the data transfer apparatus of this embodiment at the time of issuing a memory read data number read instruction (when setting the I / O buffer table 32). This process is performed by issuing a memory read data number read command issuing step 301 and a response notifying step 302.
And a memory read data number storage step 303.

FIG. 3B shows that when the memory data read command is issued (one of the input / output devices 51 to 59 is the main storage device 2).
7 is a flowchart showing the processing of the data transfer device of the present embodiment when reading data from 0). This process is performed by the memory data read command issuing step 304, the memory data read request issuing step 305, the I / O table reference step 306, and the data transfer control step 307.
And an I / O bus data sending step 308 and an end report notifying step 309.

Next, the operation of the data transfer apparatus of this embodiment having the above-mentioned structure will be described.

First, the operation at the time of issuing a memory read data number read command (when setting the I / O buffer table 32 at system startup etc.) will be described (see FIG. 3A).

The central processing unit 10 is a system bus 10
0, via the bus connection device 30 and the I / O bus 200, for each channel control device 41 to 43 (herein, the case of “for the channel control device 41” will be described as a representative). A memory read data number read command as shown in 2 is issued (step 301).

In response to the memory read data number read command, the channel control circuit 411 in the channel control device 41 determines the number of memory read data of its own device (the channel control device 41 including itself) (connected to the subordinate of the own device). Of the memory read data of the input / output devices 51 to 53 (see FIG. 2) is sent to the central processing unit 10 via the I / O bus 200, the bus connection device 30 and the system bus 100. (Step 302).

The central processing unit 10 uses the number of memory read data in the response as the I / O table 331 (I / O table corresponding to the channel control device 41) in the I / O buffer table 33 in the bus connection device 30. (Step 303).

Such processing is performed for all the channel control devices connected to the I / O bus 200. That is, the number of memory read data of the channel controller 42 is the I / O table 332 (the channel controller 42).
Stored in the I / O table), and the number of memory read data of the channel controller 43 is stored in the I / O table 33.
3 (I / O table corresponding to channel controller 43)
Stored in.

Second, the operation at the time of issuing the memory data read command (when the input / output device (any of the input / output devices 51 to 59) reads the data of the main storage device 20) will be described (FIG. 3 (b)). )reference). Here, the operation when the input / output device 51 is a read-oriented input / output device will be described.

The central processing unit 10 is the system bus 10
0, through the bus connection device 30 and the I / O bus 200, a read main input / output device is connected to a channel control device 41 (a channel control device having an input / output device 51 which is a read main input / output device under its control). The specified memory data read command is issued (step 304).

When the channel control circuit 411 in the channel control device 41 decodes the memory data read command and recognizes that the memory data read command makes the input / output device 51 the read main input / output device, I /
A memory data read request (from the main storage device 20 to the input / output device 51) to the bus connection device 30 via the O bus 200.
Issue a memory data read request) to transfer data to (step 305).

When the I / O buffer controller 31 in the bus connection device 30 receives the memory data read request from the channel controller 41, the memory data read request comes from the channel controller 41. Based on the I / O table 3 corresponding to the channel control device 41
31 is referred to (step 306).

Further, the I / O buffer control section 31 determines, based on the number of memory read data stored in the I / O table 331 referred to in step 306, in the main storage device 20 which is the target of the memory data read instruction. The data transfer control for the data (memory data) is performed as shown in the following (1) to (3) (step 307).

An I / O buffer section 32, which is a data buffer for storing data corresponding to the memory read data number, is allocated in the bus connection device 30.

Through the system bus 100, data corresponding to the number of memory read data is prefetched to the I / O buffer unit 32 allocated from the main storage device 20.

At the same time, I / O on the I / O bus 200
The data in the buffer unit 32 is output.

The data control circuit 412 in the channel control device 41 inputs the data output on the I / O bus 200 and sends the data to the input / output device 51 which is the read main input / output device (step). 308).

When the data transfer instructed by the memory data read command is completed as described above, the channel control circuit 411 in the channel control device 41 (when the data amount of the data transfer is large and a plurality of transfer cycles occur). When the data transfer is realized, after the completion of all transfer cycles), a completion report indicating that effect is sent to the central processing unit 10 via the I / O bus 200, the bus connection device 30, and the system bus 100. It is notified to the user (step 309).

Upon receiving this end report, the central processing unit 10 shifts control to the execution of processing subsequent to the memory data read processing.

[0053]

As described above, in the data transfer device of the present invention, the memory read data number read instruction for setting the memory read data number of each channel control device in the I / O buffer table is supported. By referring to the I / O buffer table at the time of issuing a data read command, the bus connection device can determine the appropriate number of data to be prefetched in consideration of which input / output device is the read main input / output device. Like Therefore, according to the present invention, it is possible to reduce invalid transfer cycles between the main memory device and the data buffer (I / O buffer unit) in the bus connection device, and it is possible to improve the system performance. Occurs.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a data transfer device of the present invention.

FIG. 2 is a diagram showing a configuration of a memory read data number read command and its response handled by the data transfer device shown in FIG.

FIG. 3 is a flowchart showing a process of the data transfer device shown in FIG.

[Explanation of symbols]

10 Central Processing Unit 20 Main Storage Device 30 Bus Connection Device 31 I / O Buffer Control Unit 32 I / O Buffer Unit 33 I / O Buffer Table 41, 42, 43 Channel Control Device 51, 52, 53, 54, 55, 56 , 57, 58, 5
9 I / O device 100 System bus 200 I / O bus 331, 332, 333 I / O table 411 Channel control circuit 412 Data control circuit

Claims (3)

[Claims] 1. An I / O bus connecting a plurality of input / output devices, a plurality of channel control devices having the input / output devices under its control, a central processing unit, a main storage device, and the channel control device. And a bus connection device that connects a system bus connecting the central processing unit and the main storage device to each other and controls a data transfer between the main storage device and the channel control device, An I / O buffer table in the bus connection device for storing the memory read data number of each of the plurality of channel control devices, and a memory read data number read command issued when the I / O buffer table is set Based on I
/ O buffer table for storing the number of memory read data and issuing a memory data read command when the input / output device reads data in the main memory, and a memory issued by the central processing unit The bus connection device is notified of a response indicating the number of memory read data of its own device in response to the read data number read command, and in response to the memory data read command regarding the input / output device under its own device issued from the central processing unit. A channel control circuit in the channel control device that issues a memory data read request to the I / O buffer table, and the number of memory read data of the channel control device that has the channel control circuit that issued the memory data read request. Acquired from the I / O buffer part of the size of the memory read data Te, pre-read data stored in the main storage to the I / O buffer section, the data in the I / O buffer section I /
An I / O buffer control unit in the bus connection device for outputting on the O bus, and data output on the I / O bus by the I / O buffer control unit are input and sent to a read main input / output device. And a data control circuit in the channel control device. 2. The memory read data number read instruction is “identification information of the central processing unit that issued the memory read data number read instruction”, “command for instructing to read the memory read data number”, and “corresponding memory read data”. 2. The data transfer device according to claim 1, comprising "identification information of a channel control device to which a number reading command is issued". 3. The number of memory read data of each channel control device is any one of 4 bytes, 64 bytes and 256 bytes.
A data transfer device according to claim 1.