JP2714184B2 - Output buffer circuit - Google Patents

Description

The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit provided in a semiconductor integrated circuit.

(Prior Art) An example of a conventional output buffer circuit using an IC is shown below. The output buffer circuit of FIG. 9 includes a P-channel MOS transistor TP01 having a source connected to the VDD power supply and an N-channel MOS transistor TN01 having a source connected to the GND (ground) potential.
The drains of the transistors were connected in common to the output line 13, the gates of both transistors were connected in common, and connected to the signal input line 20.
It consists of a CMOS inverter IV01. FIG. 10 shows input and output waveforms when the output buffer circuit shown in FIG. 9 operates. FIG. 11 shows an example in which the output buffer circuit of the CMOS inverter shown in FIG. 9 is constituted by a pattern, in which a P-channel MOS transistor TP01 and an N-channel M
The polysilicons PG01 and NG01 forming the gate of the OS transistor TN01 are collectively connected by an input line 20 made of metal wiring.

Here, in the output buffer circuit in FIG. 9, the parasitic inductances L01, L0 due to the power lines 11, 12 and the output line 13 are shown.
Due to the resonance circuit composed of 2, L03 and the load capacitance C01 of the output line 13, voltage oscillation occurs in the power supply lines 11, 12 and the output line 13 when the output buffer is driven, and as shown in FIG. An undershoot phenomenon occurs. Also the
As shown in the pattern shown in FIG. 11, when the divided polysilicon gates are collectively connected by the metal wiring 20, all the connected transistors (T01
T06 or T11 to T16) are simultaneously turned on, so that the output load is rapidly charged and discharged, so that the above-mentioned overshoot and undershoot phenomenon becomes more remarkable.
As a result, there is a problem that the power supply voltage fluctuates, which causes a malfunction or a latch-up phenomenon of another element connected to the same power supply line as the output buffer circuit.

FIG. 12 shows an example in which the output buffer circuit of the CMOS inverter shown in FIG. 9 is formed by another pattern.
In the pattern of FIG. 11, the gates are collectively connected by metal wiring, whereas in the output buffer circuit of FIG. 12, collective connection by metal wiring is not performed in order to use the delay of the gate. Since the divided gates are connected in series by the polysilicon PG02 and NG02 which are gate electrode materials, the delay of CR of the polysilicon gate causes
P-channel and N-channel MOS transistors (T
21~T26 or T31～T36) is no longer possible to turn on simultaneously, so that T21-T22 ...... T _n is a P-channel MOS transistor, also T31-T is an N-channel MOS transistor
32 to gradually turn on and so ...... T _n, charging by the inflow of current from the VDD power supply is slowly performed inflow and the load capacitance C01 to GND of the charge accumulated in the load capacitor C01 in FIG. 9 Therefore, the above-described overshoot and undershoot phenomena are suppressed. However, in the output buffer circuit as shown in FIG. 12, the delay due to the CR of the gate is determined by the gate size of the transistor. The size of the N-channel MOS transistor and the size of the N-channel MOS transistor must be adjusted. Here, in the case of the MOS transistor, in the same process, the same transistor size due to a difference in mobility, etc. Is about 2-3 times larger than that of the P-channel MOS transistor, and the setting of the transistor size for the required transistor characteristics becomes unbalanced between the P-channel and N-channel transistors. It is difficult to adjust the transistor size to obtain You. Further, with the recent miniaturization of devices due to the advancement of semiconductor technology, the layer resistance of polysilicon conventionally used as a gate electrode material is as high as 20 to 30 Ω / □, which causes wiring delay. Therefore, a refractory metal silicide is being used as a new gate material, and the layer resistance when using MoSi ₂ , WSi ₂ , or TaSi ₂ as a gate electrode is 2-3Ω / □, which is lower than that of polysilicon. The value is one digit smaller. These silicides have chemical properties very similar to polysilicon, and can be handled almost in the same way as polysilicon in the process except for some steps.

As described above, when the layer resistance of the gate electrode material is being reduced along with the miniaturization of the device, an output signal is generated at the time of output buffer switching by utilizing the delay of the gate electrode material as in the output buffer in FIG. Even if an attempt is made to suppress the overshoot and undershoot phenomena that occur, this cannot be achieved.

(Problems to be Solved by the Invention) As described above, with the increase in the speed of the semiconductor device, in the conventional output buffer circuit, as shown in FIG. During switching of the output buffer, voltage oscillation occurs on the power supply line and output line, causing overshoot and undershoot phenomena as shown in Fig. 10. As a result, the power supply voltage fluctuates. This causes malfunction of other elements and induction of latch-up phenomenon.

Further, in the circuit of FIG. 12 devised to improve the above-described problem, the transistor used for the output buffer is gradually turned on using the delay due to the CR of the gate electrode material, so that the circuit connected to the output line of the output buffer is used. Since the charging and discharging of the applied load capacity is performed slowly, the overshoot and undershoot phenomena are suppressed. However, it may be difficult to adjust the transistor size to obtain a predetermined gate delay amount. If the delay due to the CR of the gate electrode is large, the period during which the transistors TP01 and TN01 shown in FIG. 9 are simultaneously turned on becomes long, and a large through current flows between the power supplies VDD and GND. In recent years, with the miniaturization of devices due to advances in semiconductor technology, gate electrode materials have been reduced in resistance. Even if an attempt is made to suppress the shoot and undershoot phenomena, it cannot be realized.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output buffer circuit that can solve the above-mentioned conventional problems.

[Constitution of the Invention] (Means and Action for Solving the Problems) According to the present invention, a first P-channel MOS transistor having an output connected to an output line and a gate divided into a plurality of parts, and an output connected to the output line A first N-channel MOS transistor having a gate divided into a plurality of gates;
A second P-channel MOS transistor connected between the gates of the channel MOS transistors, the input side and the output side of which are commonly connected, and a low-level potential applied to the gate and a second N-channel MOS transistor applied to the gate at a high level potential channel
A third P-channel MOS transistor is connected between the MOS transistor and the gate of the first N-channel MOS transistor, the input side and the output side are commonly connected, and a low-level potential is applied to the gate and a high level is applied to the gate. A third N-channel MOS transistor to which a potential is applied, wherein gm of the second P-channel MOS transistor is greater than gm of the third P-channel MOS transistor, and gm of the third N-channel MOS transistor is higher than that of the third N-channel MOS transistor. An output buffer circuit characterized in that gm is made larger than gm of the second N-channel MOS transistor.

The present invention also provides a first P-channel MOS transistor having an output connected to an output line and a divided gate, and a first P-channel MOS transistor having an output connected to the output line and a divided gate. An input signal that is connected between an N-channel MOS transistor and the gate of the first P-channel MOS transistor, has an input side and an output side commonly connected, and controls conduction of the first P-channel and N-channel MOS transistors, A signal is connected between a second P-channel MOS transistor whose gate is supplied with a signal of opposite phase, a second N-channel MOS transistor whose gate is supplied with a high-level potential, and the gate of the first N-channel MOS transistor. , An input side and an output side are commonly connected, and a third P-channel MOS transistor whose gate is supplied with a low-level potential is connected to the first P-channel MOS transistor. A third N-channel MOS transistor whose gate is supplied with a signal having a phase opposite to that of an input signal for controlling conduction of the N-channel MOS transistor, wherein gm of the second P-channel MOS transistor is equal to the third P-channel MOS transistor. G of channel MOS transistor
m larger than the third N-channel MOS transistor.
An output buffer circuit characterized in that gm is made larger than gm of the second N-channel MOS transistor.

The present invention further provides a first P-channel MOS transistor having an output connected to an output line and a divided gate, and a first P-channel MOS transistor having an output connected to the output line and a divided gate. An N-channel MOS transistor, an input side of which is commonly connected to an input signal for controlling conduction of the first P-channel and N-channel MOS transistors, and an output side of a first stage among a plurality of gates of the first P-channel MOS transistor Connected to the remaining gates except the gate,
A second P-channel MOS transistor having a gate commonly connected to a signal having a phase opposite to that of an input signal for controlling conduction of the first P-channel and N-channel MOS transistors; and a gate of the first P-channel MOS transistor The input and output are connected between the gates of the second N-channel MOS transistor whose gate is supplied with a high-level potential and the first N-channel MOS transistor, and the gate has a low level. A third P-channel MOS transistor to which a potential is applied and an input side are commonly connected to an input signal for controlling conduction of the first P-channel and N-channel MOS transistors, and an output side is the first N-channel MOS transistor.
The plurality of gates of the S transistor are connected to the remaining gates other than the first stage gate, and the gates are commonly connected to a signal having a phase opposite to that of the input signal for controlling conduction of the first P-channel and N-channel MOS transistors. A third N-channel MOS transistor, wherein gm of the second P-channel MOS transistor is larger than gm of the third P-channel MOS transistor, and
An output buffer circuit characterized in that gm of the transistor is made larger than gm of the second N-channel MOS transistor.

That is, in the present invention, the transistor gate for the output buffer is divided, and the transistor for signal output can be turned on gradually by connecting the gate with the transistor, so that the load capacitance connected to the output line is charged and discharged. Can be performed gently. Further, by setting the size of the transistor connected between the gates in a predetermined relationship, it is possible to reduce a through current generated at the time of output buffer switching. Accordingly, the present invention suppresses the overshoot and undershoot phenomena that occur during output buffer switching in a conventional output buffer with the increase in the speed of a semiconductor device, and prevents a through current between a power supply and ground during output buffer switching. Therefore, it is possible to prevent a malfunction and a latch-up phenomenon of another element sharing the power supply. Further, in the present invention, with the miniaturization of the device due to the recent advancement of semiconductor technology, even if the resistance of the gate electrode is reduced, the resistance element provided between the divided gate electrodes described above with reference to FIG. Such a problem does not occur.

(Embodiment) FIG. 1 is a circuit diagram of a pattern image of an output buffer circuit considered during the present invention. In FIG. 1, the gate of the P-channel transistor TP01 of the output buffer is divided into PG11 to PG14, the adjacent gates are connected by resistance elements DF01 to DF03 formed by diffusion layers, and the gate of the N-channel transistor TN01 is connected to NG11 to NG13. The adjacent gates are connected by resistance elements DF11 and DF12 formed by diffusion layers. The sources S are connected in common on the power supply side, and the drains D are connected in common by output lines 42.

In this circuit, the output 41 of the pre-buffer IV10 by the CMOS inverter to which the input 40 is connected is first connected to the gate PG11 of the P-channel transistor and the gate of the N-channel transistor.
NG11, and thereafter, through the resistance of the diffusion layer connecting the respective gates, T41 → T42 → T43 →... T48 for the P-channel transistor, T51 → T52 → T53 for the N-channel transistor → Since it is gradually turned on at T56, the charging and discharging of the load capacitance C01 connected to the output line 42 is performed slowly. Therefore, the overshoot and undershoot phenomena shown in FIG. 10 are suppressed. Further, in the configuration in which the divided gates are connected by the resistance element as shown in FIG. 1, the delay amount can be easily set, and the resistance value of the diffusion layer is usually 50 to 50.
Since it is about 0 Ω / □ and is variable depending on the shape of the diffusion layer pattern, setting for obtaining a predetermined gate delay amount is easy.

FIG. 2 shows a first embodiment of the present invention. In this embodiment, the gate of the P-channel transistor of the output buffer is divided into PG11 to PG14, the gate of the N-channel transistor is divided into NG11 to NG13, and the adjacent gates are commonly connected to the input side and the output side, respectively. P-channel transistors (TP11 to TP13 on the P-channel side, TP14 and TP15 on the N-channel side) whose gates are supplied with the GND (ground) potential, and N-channel transistors (TN11 on the P-channel side) whose gates are supplied with the VDD potential. ~ TN13, N channel side is TN14, T
N15) and a P-channel transistor T
P-channel transistor T connecting gates of P01
Gm (conductance) of each of P11 to TP13 is larger than gm of each of P-channel transistors TP14 to TP15 connecting between the gates of N-channel transistor TN01,
The gm of each of the N-channel transistors TN14 to TN15 connecting the gates of the N-channel transistor TN01 is P
N connecting the gates of the channel transistors TP01
It is set larger than gm of each of the channel transistors TN11 to TN13. The drains D are commonly connected by an output line 42, and the output 41 of the prebuffer IV10 by the CMOS inverter at the input point 40 is connected to the gate PG11 of the P-channel transistor TP01 and the gate NG11 of the N-channel transistor TN01 of the output buffer. It is connected to the.

In the circuit of FIG. 2, when the input point 40 of the input IN is lowered from the VDD potential to the GND potential, the P of the CMOS inverter IV10 is reduced.
The channel transistor is turned on, and the potential of the node 41 becomes
Start rising from GND potential. Next, in the output buffer, the potential of the gates PG11 and NG11 starts to rise. In the P-channel transistor, when the P-channel transistors TP11 to TP13 connecting between the divided gates are turned on, the P-channel transistors T41 to T48 are quickly turned off, so that a through current can be prevented. Thereafter, in the N-channel transistor TN01 of the output buffer, the N-channel transistor connecting the divided gates is connected.
By turning on TN14 to TN15, the transistor T51 is turned on.
~ T56 turns on gradually. At this time, the on-resistance of the N-channel transistors TN14 to TN15 rises due to the back gate bias effect as the gate potential of the N-channel transistors T53 to T56 rises, and the rise of the gate potential becomes gentle. Also transistors TP14, TP
Reference numeral 15 serves to finally bring the gate potential to a complete "1" level. Next, the signal input node 40 is connected to GND
When the potential is raised from the potential to the VDD potential, the CMOS inverter IV10
N-channel transistor is turned on, and the potential of the node 41 starts to fall from the VDD potential. Next, in the output buffer, the potentials of the gates PG11 and NG11 start to decrease, and N
In the channel transistor TN01, N-channel transistors TN14, TN connecting between the divided gates
By turning on 15, N-channel transistors T51 to T51
56 turns off quickly, preventing shoot-through current. Thereafter, in the P-channel transistor TP01 of the output buffer, when the P-channel transistors TP11 to TP13 connecting between the divided gates are turned on, the transistors T41 to T48 are gradually turned on. At this time, the on-resistance of the P-channel transistors TP11 to TP13 rises due to the back gate bias effect as the gate potential of the P-channel transistors T43 to T48 decreases, and the rise of the gate potential becomes gentle. Also transistor TN
11 to TN13 function to finally bring the gate potential to a complete "0" level.

FIG. 3 shows a different embodiment of the present invention. In FIG. 3, the gate of the P-channel transistor of the output buffer is divided into PG11 to PG14, the gate of the N-channel transistor is divided into NG11 to NG13, and between adjacent gates, the gate side of the P-channel transistor is the input side and P-channel transistors TP11 to TP13 whose output sides are commonly connected and the input IN is given to the gate, and VDD potential is given to the gate and connected using N-channel transistors TN11 to TN13, and the gate side of the N-channel transistor is , P-channel transistors TP14 and TP15 whose input side and output side are connected in common and whose gate is supplied with GND potential, and an N-channel transistor whose gate is supplied with input IN
P-channel transistors connected using TN14 and TN15, connecting the gates of P-channel transistors
The gm of each of TP11 to TP13 is larger than the gm of each of the P-channel transistors TP14 and TP15 connecting between the N-channel transistors, and the gm of each of the N-channel transistors TN14 and TN15 connecting between the gates of the N-channel transistors is , And gm of each of the N-channel transistors TN11 to TN13 connecting the gates of the P-channel transistors.

The drains D are commonly connected by an output line 42, and the output 41 of the prebuffer IV10 by the CMOS inverter having the node 40 as an input point is the output buffer P10.
It is connected to the gate PG11 of the channel transistor and the gate NG11 of the N-channel transistor.

Now, in the circuit of FIG. 3, when the signal input IV is lowered from the VDD potential to the GND potential, the P of the CMOS inverter IV10 is reduced.
The channel transistor is turned on, and the potential of the node 41 becomes
The potential starts to rise from the GND potential, and in the output buffer, the potential of the gates PG11 and NG11 starts to rise. In the P-channel transistor TP01, the gates of the P-channel transistors TP11 to TP13 connecting between the divided gates are given "0" level, and when these transistors are turned on, the P-channel transistors T41 to T41 are turned on. T48 turns off quickly. Thereafter, in the N-channel transistor TN01 of the output buffer, when the P-channel transistors TP14 and TP15 connecting between the divided gates are turned on, the transistors T51 to T56 are gradually turned on. At this time, the gates of the N-channel transistors TN14 and TN15 are given the "0" level of the input node 40, so that TN14 and TN15 are off. Then, contrary to the above,
When the signal input IN is raised from GND potential to VDD potential, CMOS
The N-channel transistor of the inverter IV10 turns on, the potential of the node 41 starts to fall from the VDD potential, and the potential of the gates PG11 and NG11 in the output buffer starts to fall. In the N-channel transistor TN01, an N-channel transistor TN connecting between the divided gates
In 14 and TN15, the "1" level of the input node 40 is given to the gate, and when these transistors are turned on, the N-channel transistors T51 to T56 are rapidly turned off. Then the output buffer P-channel transistor TP01
In, the N-channel transistors TN11 to TN13 connecting between the divided gates are turned on, so that the transistors T41 to T48 are gradually turned on. At this time, since the "1" level of the input node 40 is given to the gates of the P-channel transistors TP11 to TP13,
Is in the off state.

FIG. 4 shows a different embodiment of the present invention. Here, the gate of the P-channel transistor TP01 of the output buffer is
Connect the gate of N-channel transistor TN01 to PG11
NG13, and between the gates, the gate side of the P-channel transistor is connected by N-channel transistors TN21 to TN23 whose gates are supplied with a VDD potential. The drains of the P-channel transistors TP21 to TP23, to which the output 40 is connected and the output 41 of the inverter IV10 is connected to the source, are connected. The gate side of the N-channel transistor TN01 is connected to P-channel transistors TP24 and T
Connect with P25, each divided gate NG12, NG13
Connect the input point 40 to the gate and the inverter IV to the source.
N-channel transistors TN24, TN with 10 outputs 41 connected
25 drains are connected respectively. The gm of each of the P-channel transistors TP21 to TP23 is TP24, TP
25, the N-channel transistor TN2
4. Each gm of TN25 is set larger than that of T21-TN23. The drains of the transistors T41 to T48 and T51 to T56 are commonly connected by an output line 42, and the output 41 of the pre-buffer IN10 by the CMOS inverter having the node 40 as an input point is the gate PG11 of the P-channel transistor of the output buffer and It is connected to the gate NG11 of the N-channel transistor.

Now, in the circuit of FIG.
When the potential is lowered from the potential to the GND potential, the P
The channel transistor is turned on, and the potential of the node 41 becomes
Start rising from GND. Since the "0" level of the input point 40 of TP21 to TP23 is given to the P-channel transistor TP01 of the output buffer, the P-channel transistor T41 is turned on by turning on these transistors.
~ T48 turns off rapidly. Thereafter, in the N-channel transistor TN01 of the output buffer, when the P-channel transistors TP24 and TP25 connecting between the divided gates are turned on, the transistors T51 to T56 are gradually turned on. At this time, N-channel transistors TN24 and TN25
Is in the off state because the “0” level of the gate input node 40 is given. Next, contrary to the above, the signal input node
When 40 is raised from the GND potential to the VDD potential, the N-channel transistor of the CMOS inverter IV10 is turned on and the node
The potential of 41 starts to fall from VDD. In the N-channel transistor TN01 of the output buffer, the input point 40 "1" level is given to the gates of the transistors TN24 and TN25. To turn off. After this, the P-channel transistor TP01 of the output buffer
In, the N-channel transistors TN21 to TN23 connecting between the divided gates are turned on, so that the transistors T41 to T48 are gradually turned on. At this time, the P-channel transistors TP21 to TP23 are in the off state since the gate is supplied with the “1” level of the input node 40.

In the embodiment shown in FIGS. 2 to 4, the on-resistance value of the transistor can be freely set by changing the gm of the transistor used as the resistance element. As shown in the embodiment, by setting gm of each transistor used as a resistance element to a predetermined value, charging and discharging (switching) of the off-side transistor gate at the time of output buffer switching is fast, and charging of the on-side transistor gate is performed. By slowing the discharge, VDD-output buffer P-channel transistor TP01-output buffer N-channel transistor TN01-G during switching
The through current flowing between ND is reduced.

FIG. 5 shows a modification of FIG. 2, in which the pre-buffer section is constituted by an N-channel transistor T1 and a P-channel transistor T2. These transistors are controlled by the gate input IN. When the transistor T1 is on, the P-channel output buffer TP01 is controlled. When the transistor T2 is on, the N-channel output buffer TN01 is controlled.

FIG. 6 is also a modification of FIG. 2, in which a gate and pre-buffer sections of G1 to G3 are used, and the output buffer circuit is a tri-state circuit. That is, according to the combination of the inputs IN and EN, the output buffer transistors TP01 and TN01 are turned on and off, and the outputs of the gates G2 and G3 simultaneously turn off the TP01 and TN01. It is possible to be.

FIGS. 7 and 8 are examples of an output buffer of one channel each of which is considered in the course of the present invention. FIG. 7 shows a P-channel transistor and FIG. 8 shows an output buffer of an N-channel transistor. It is what constituted. That is, in FIG. 7, the gm of the transistor to be turned on among the transistors TN11 to TN13 and TP11 to TP13 for connecting the split gate, and in FIG. 8 among the transistors TN14, TN15, TP14 and TP15 is small and gradually turned on. The through current (current between power supplies via the transistor TP01 or TN01) is reduced by increasing the gm of the transistor to be turned off and increasing the gm of the transistor to be turned off earlier.

It should be noted that the present invention is not limited to the circuits shown in the embodiments, and various other modifications can be made.

[Effects of the Invention] As described above, according to the present invention, the transistor for signal output can be turned on gradually by dividing the transistor gate of the output buffer and connecting the gates with transistors, so that the output line The charging and discharging of the load capacity connected to the power supply can be performed slowly. Further, by setting the size of the transistor connected between the gates in a predetermined relationship, it is possible to reduce a through current generated at the time of output buffer switching.

As described above, according to the present invention, the overshoot and undershoot phenomena occurring during the output buffer switching in the conventional output buffer with the increase in the speed of the semiconductor device are suppressed, and the penetration between VDD and GND during the output buffer switching is suppressed. Since the current can be prevented, it is possible to prevent a malfunction or a latch-up phenomenon of another element sharing the power supply. Further, according to the present invention, since the total output buffer size is not different from the conventional one, the same output current characteristic can be obtained as compared with the conventional one. Even if the resistance of the gate electrode is reduced, a separate resistance element is connected to the divided gate, so that no problem occurs and the signal delay time can be made more accurate.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output buffer circuit considered in the course of the present invention, FIGS. 2 to 6 are circuit diagrams of respective embodiments of the present invention, and FIGS. 9 is a circuit diagram of a conventional output buffer circuit, FIG. 10 is an input / output characteristic diagram thereof, and FIGS. 11 and 12 are circuits which further illustrate FIG. FIG. TP01 …… P-channel transistor of output buffer, TN01
…… Output buffer N-channel transistor, PG11 to PG
14: P-channel split gate, NG11 to NG13: N-channel split gate, S: source, D: drain, DF
01 to DF03, DF11, DF12 ...... Resistance element, TN11 to TN15, TP11
~ TP15 ... Resistance element transistor, IV10 ... CMOS inverter.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Masazumi Shioji 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Semiconductor System Technology Center Co., Ltd. (56) References JP-A-63-292647 (JP, A) JP-A-62-48806 (JP, A) JP-A-2-203618 (JP, A) JP-A-2-246513 (JP, A) JP-A-62-282817 (JP, A) JP-A-62-82817 −299111 (JP, A)

Claims (3)

(57) [Claims] 1. A first P-channel MOS transistor having an output connected to an output line and a gate divided into a plurality, and a first P-channel MOS transistor having an output connected to the output line and a gate divided into a plurality. A second P-channel MOS transistor connected between the N-channel MOS transistor and the gate of the first P-channel MOS transistor, having an input side and an output side commonly connected, and a low-level potential applied to the gate;
The second in which a high level potential is applied to the transistor and the gate
A third P-channel MOS transistor, which is connected between the gates of the N-channel MOS transistor and the first N-channel MOS transistor, has an input side and an output side commonly connected, and has a low-level potential applied to the gate.
Third where a high-level potential is applied to the transistor and the gate
And the gm of the second P-channel MOS transistor is the third N-channel MOS transistor.
An output buffer circuit wherein the gm of the third N-channel MOS transistor is larger than the gm of the second N-channel MOS transistor. 2. A first P-channel MOS transistor having an output connected to an output line and a gate divided into a plurality, and a first P-channel MOS transistor having an output connected to the output line and a gate divided into a plurality. An N-channel MOS transistor, an input signal connected between the gates of the first P-channel MOS transistors, an input side and an output side commonly connected, and an input signal for controlling conduction of the first P-channel and N-channel MOS transistors, A second P-channel MOS transistor having a gate supplied with a signal of opposite phase, a second N-channel MOS transistor having a high-level potential applied to the gate, and a gate connected to the gate of the first N-channel MOS transistor , An input side and an output side are commonly connected, and a third P-channel MOS having a gate supplied with a low-level potential
Transistor and the first P-channel and N-channel MO
A third N-channel MOS transistor having a gate supplied with a signal having a phase opposite to that of an input signal for controlling conduction of the S transistor, wherein gm of the second P-channel MOS transistor is the third N-channel MOS transistor.
An output buffer circuit wherein the gm of the third N-channel MOS transistor is larger than the gm of the second N-channel MOS transistor. 3. A first P-channel MOS transistor having an output connected to an output line and a gate divided into a plurality, and a first P-channel MOS transistor having an output connected to the output line and a gate divided into a plurality. An N-channel MOS transistor, an input side of which is commonly connected to an input signal for controlling conduction of the first P-channel and N-channel MOS transistors, and an output side of a first stage among a plurality of gates of the first P-channel MOS transistor Connected to the remaining gates except the gate, and the gate is connected to the first P-channel and N-channel MOs.
An input / output is connected between a gate of the second P-channel MOS transistor and a gate of the first P-channel MOS transistor, which are commonly connected to a signal having a phase opposite to an input signal for controlling conduction of the S transistor. A third P-channel MOS transistor in which the input and output are connected between the gate of the second N-channel MOS transistor to which a high-level potential is applied and the gate of the first N-channel MOS transistor, and whose gate is supplied with a low-level potential A transistor, an input side of which is commonly connected to an input signal for controlling conduction of the first P-channel and N-channel MOS transistors, and an output side of the plurality of gates of the first N-channel MOS transistor other than the first-stage gate Connected to the remaining gates, where the gates are the first P-channel and N-channel MOs.
A third N-channel MOS transistor commonly connected to a signal having a phase opposite to that of the input signal for controlling the conduction of the S transistor, wherein gm of the second P-channel MOS transistor is
An output buffer circuit wherein the gm of the third N-channel MOS transistor is larger than the gm of the second N-channel MOS transistor.