JP2695983B2 - Solid-state imaging device - Google Patents

Solid-state imaging device

Info

Publication number
JP2695983B2
JP2695983B2 JP2279807A JP27980790A JP2695983B2 JP 2695983 B2 JP2695983 B2 JP 2695983B2 JP 2279807 A JP2279807 A JP 2279807A JP 27980790 A JP27980790 A JP 27980790A JP 2695983 B2 JP2695983 B2 JP 2695983B2
Authority
JP
Japan
Prior art keywords
type
solid
state imaging
imaging device
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2279807A
Other languages
Japanese (ja)
Other versions
JPH04152675A (en
Inventor
敏雄 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2279807A priority Critical patent/JP2695983B2/en
Publication of JPH04152675A publication Critical patent/JPH04152675A/en
Application granted granted Critical
Publication of JP2695983B2 publication Critical patent/JP2695983B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION 【産業上の利用分野】[Industrial applications]

この発明は固体撮像装置に関し、より詳しくは、イン
ターライン転送CCD(電荷転送素子)型の固体撮像装置
に関する。
The present invention relates to a solid-state imaging device, and more particularly to an interline transfer CCD (charge transfer device) type solid-state imaging device.

【従来の技術】[Prior art]

一般に、この種のインターライン転送CCD型の固体撮
像素子は、第2図に示すように構成されている。N型半
導体基板21の表面21aに低不純物濃度のP-型ウエル22が
設けられ、このP-型ウエル22内に、N型不純物領域28か
らなる光電変換部202が等間隔に複数並べて設けられて
いる。さらに、P+型の画素分離領域25を挾んで上記各光
電変換部202に隣接して、転送部201が設けられている。
各転送部201は、N-型の転送チャネル24,ゲート絶縁膜26
およびゲート電極27からなっている。各光電変換部202
とこれに隣接する転送部201とでそれぞれ1つの列200を
構成している。そして、各列200の光電変換部202が入射
光を信号電荷に変換し、生じた信号電荷を上記列200の
転送部201がそれぞれ転送する。 従来、各列200間の隙間30の基板表面21aにはP-型ウエ
ル22が覗く状態となっており、転送部201のゲート電極2
7がこの隙間30上に延在している。このゲート電極27の
端部27aの電界によって各列200の間を電気的に分離して
いる。 なお、23,29はそれぞれP型不純物層を示している。2
9は省略可能である。
Generally, this type of interline transfer CCD type solid-state imaging device is configured as shown in FIG. A P - type well 22 having a low impurity concentration is provided on a surface 21a of an N-type semiconductor substrate 21. In the P - type well 22, a plurality of photoelectric conversion units 202 including N-type impurity regions 28 are provided at equal intervals. ing. Further, a transfer unit 201 is provided adjacent to each of the photoelectric conversion units 202 with the P + type pixel isolation region 25 interposed therebetween.
Each transfer unit 201 includes an N - type transfer channel 24, a gate insulating film 26.
And a gate electrode 27. Each photoelectric conversion unit 202
And a transfer unit 201 adjacent thereto constitute one column 200, respectively. Then, the photoelectric conversion units 202 in each column 200 convert the incident light into signal charges, and the generated signal charges are transferred by the transfer units 201 in the above-mentioned column 200, respectively. Conventionally, the P - type well 22 is in a state of peeping on the substrate surface 21a of the gap 30 between each row 200, and the gate electrode 2 of the transfer unit 201 is
7 extends over this gap 30. Each column 200 is electrically separated by the electric field at the end 27a of the gate electrode 27. 23 and 29 indicate P-type impurity layers, respectively. Two
9 can be omitted.

【発明が解決しようとする課題】[Problems to be solved by the invention]

ところで、近年の固体撮像装置は、使用レンズのサイ
ズが1/2インチから1/3インチ、さらには1/4インチへと
小型化される傾向にあり、これに伴って上記半導体基板
21のサイズ(チップサイズ)を縮小することが望まれて
いる。ここで、上記転送部201,光電変換部202のサイズ
を縮小することは、最大信号電荷量,感度など性能の低
下を招くため好ましくない。このため、性能を落とさず
にチップサイズを縮小するためには、各列200間の隙間3
0を狭くすることが必要となる。しかしながら、単に各
列200間の隙間30を狭くすると、短チャネル効果が生じ
て、しきい値Vthを制御することが困難となり、各列200
間を制御性良く分離できなくなる。 そこで、この発明の目的は、各列間の隙間を狭くした
としても短チャネル効果が生じるのを抑制でき、したが
って、性能を低下させることなくチップサイズを縮小で
きる固体撮像装置を提供することにある。
By the way, in recent solid-state imaging devices, the size of a lens used tends to be reduced from 1/2 inch to 1/3 inch, and further down to 1/4 inch.
It is desired to reduce the size of 21 (chip size). Here, reducing the size of the transfer unit 201 and the photoelectric conversion unit 202 is not preferable because performance such as the maximum signal charge amount and sensitivity is reduced. Therefore, in order to reduce the chip size without deteriorating the performance, the gap 3 between each row 200 is required.
It is necessary to make 0 narrow. However, if the gap 30 between the columns 200 is simply narrowed, a short channel effect occurs, making it difficult to control the threshold value Vth.
The separation cannot be performed with good controllability. Therefore, an object of the present invention is to provide a solid-state imaging device that can suppress the occurrence of the short channel effect even if the gap between the columns is narrowed, and can therefore reduce the chip size without lowering the performance. .

【課題を解決するための手段】[Means for Solving the Problems]

上記目的を達成するために、この発明は、半導体基板
またはウエルの表面に、光電変換部と転送部とを隣接さ
せて構成した各列を所定距離だけ離間させて複数並べて
配置し、上記各列間の隙間上に上記転送部のゲート電極
を延在させて、このゲート電極の電界によって上記各列
間を電気的に分離するようにした固体撮像装置におい
て、上記基板またはウエルの全表面に、上記光電変換部
で発生した信号電荷と逆の導電型であって上記基板また
はウエルよりも高濃度の不純物層を設けたことを特徴と
している。
In order to achieve the above object, the present invention provides a semiconductor substrate or a well, in which a plurality of columns each having a photoelectric conversion unit and a transfer unit arranged adjacent to each other are arranged at a predetermined distance from each other, and In a solid-state imaging device in which the gate electrode of the transfer unit is extended over a gap between the columns and the columns are electrically separated by the electric field of the gate electrode, on the entire surface of the substrate or well, The semiconductor device is characterized in that an impurity layer having a conductivity type opposite to that of the signal charges generated in the photoelectric conversion portion and a higher concentration than the substrate or the well is provided.

【作用】[Action]

各列間の隙間の基板またはウエル表面に信号電荷と逆
の導電型であって上記基板またはウエルよりも高濃度の
不純物層が設けられた場合、上記各列間の隙間は反転し
にくくなる。したがって、上記各列間の隙間を狭くした
としても、短チャネル効果が生じるのが抑制され、従来
に比して上記各列間は制御性良く分離される。したがっ
て、性能を低下させることなくチップサイズを縮小でき
るようになる。
When an impurity layer having a conductivity type opposite to that of the signal charge and a higher concentration than the substrate or the well is provided on the surface of the substrate or the well in the gap between the columns, the gap between the columns is unlikely to be inverted. Therefore, even if the gap between the rows is narrowed, the short channel effect is suppressed from occurring, and the rows are separated from each other with better control compared to the related art. Therefore, the chip size can be reduced without lowering the performance.

【実施例】【Example】

以下、この発明の固体撮像装置を図示の実施例により
詳細に説明する。 第1図に示すように、この固体撮像装置は、従来と同
様に、N型半導体基板11の表面11aに低不純物濃度のP-
型ウエル12を設けている。このP-型ウエル12内にN型不
純物領域18からなる光電変換部102を等間隔に複数並べ
て設けている。さらに、P+型の画素分離領域15を挾んで
上記各光電変換部102に隣接して、転送部101を設けてい
る。各転送部101は、N-型の転送チャネル14,ゲート絶縁
膜16およびゲート電極17からなっている。各光電変換部
102とこれに隣接する転送部101とでそれぞれ1つの列10
0を構成している。さらに、各列100間の隙間20を含んで
この基板11の表面(P-型ウエル12の表面でもある)11a
全面に、P-型ウエル12より高不純物濃度のP型不純物層
40を他の層よりも浅く設けている。各列100間の隙間20
上には各列の転送部101のゲート電極17を延在させてい
る。なお、13,19はそれぞれ転送チャネル14下,N型不純
物領域14上に形成されたP型不純物層を示している。 入射光があった場合、従来と同様に、各列100の光電
変換部102が入射光を信号電荷に変換する。そして、生
じた信号電荷を上記列100の転送部201がそれぞれ転送す
る。 また、各列100間は、各列から隙間20上に延在するゲ
ート電極17の端部17aの電界によって電気的に分離す
る。ここで、各列100間の隙間20に、P-型ウエル12より
も高濃度のP型不純物層40を設けているので、上記隙間
20は従来に比して反転しにくくなっている。したがっ
て、この隙間20を狭くしたとしても、短チャネル効果が
生じるのを抑制することができ、従来に比して各列100
間を制御性良く分離することができる。したがって、性
能を低下させることなくチップサイズを縮小させること
ができる。
Hereinafter, a solid-state imaging device according to the present invention will be described in detail with reference to the illustrated embodiments. As shown in FIG. 1, the solid-state imaging device, like the conventional, a low impurity concentration on the surface 11a of the N-type semiconductor substrate 11 P -
A mold well 12 is provided. In the P - type well 12, a plurality of photoelectric conversion units 102 each including an N-type impurity region 18 are provided at equal intervals. Further, a transfer unit 101 is provided adjacent to each of the photoelectric conversion units 102 with the P + type pixel isolation region 15 interposed therebetween. Each transfer unit 101 includes an N type transfer channel 14, a gate insulating film 16, and a gate electrode 17. Each photoelectric conversion unit
102 and one adjacent transfer unit 101 each have one column 10
0 is configured. Further, the surface of the substrate 11 (which is also the surface of the P - type well 12) 11a including the gaps 20 between the rows 100 is provided.
P-type impurity layer with a higher impurity concentration than P - type well 12 on the entire surface
40 is provided shallower than the other layers. Gap 20 between each row 100
The gate electrodes 17 of the transfer units 101 in each column extend above. Reference numerals 13 and 19 denote P-type impurity layers formed below the transfer channel 14 and on the N-type impurity region 14, respectively. When there is incident light, the photoelectric conversion units 102 in each row 100 convert the incident light into signal charges, as in the related art. Then, the generated signal charges are transferred by the transfer units 201 of the column 100, respectively. The columns 100 are electrically separated from each other by the electric field at the end 17a of the gate electrode 17 extending over the gap 20 from each column. Here, since the P-type impurity layer 40 having a higher concentration than the P -type well 12 is provided in the gap 20 between each row 100,
20 is less likely to be inverted than before. Therefore, even if the gap 20 is narrowed, the short channel effect can be suppressed from occurring, and each row 100
The separation can be performed with good controllability. Therefore, the chip size can be reduced without lowering the performance.

【発明の効果】【The invention's effect】

以上より明らかなように、この発明の固体撮像装置
は、光電変換部と転送部とからなり信号電荷を転送する
各列間の隙間の基板またはウエル表面に、P型またはN
型のうち上記信号電荷と逆の導電型であって、上記基板
またはウエルよりも高不純物濃度のP型不純物層を設け
ているので、各列間の隙間を狭くしたとしても短チャネ
ル効果が生じるのを抑制することができる。したがっ
て、性能を低下させることなくチップサイズを縮小する
ことができる。
As is clear from the above, the solid-state imaging device according to the present invention has a P-type or N-type on the surface of the substrate or well in the gap between each row, which includes the photoelectric conversion unit and the transfer unit and transfers signal charges.
Since the P type impurity layer is of a conductivity type opposite to that of the signal charge and has a higher impurity concentration than the substrate or the well, a short channel effect occurs even if the gap between the columns is narrowed. Can be suppressed. Therefore, the chip size can be reduced without lowering the performance.

【図面の簡単な説明】[Brief description of the drawings]

第1図はこの発明の一実施例の固体撮像装置の構成を示
す断面図、第2図は従来のインターライン転送CCD型固
体撮像装置の構成を示す断面図である。 11……N型半導体基板、12……P-型ウエル、13,19……
P型不純物層、14……N-型転送チャネル、15……P+型画
素分離領域、16……ゲート絶縁膜、17……ゲート電極、
18……N型不純物領域、20……隙間、40……P型不純物
層、100……列、101……転送部、102……光電変換部。
FIG. 1 is a cross-sectional view showing the configuration of a solid-state imaging device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the configuration of a conventional interline transfer CCD type solid-state imaging device. 11 ... N-type semiconductor substrate, 12 ... P - type well, 13,19 ...
P-type impurity layer, 14 ...... N - -type transfer channel, 15 ...... P + -type element isolation region, 16 ...... gate insulating film, 17 ...... gate electrode,
18 N-type impurity regions, 20 gaps, 40 P-type impurity layers, 100 columns, 101 transfer units, 102 photoelectric conversion units.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体基板またはウエルの表面に、光電変
換部と転送部とを隣接させて構成した各列を所定距離だ
け離間させて複数並べて配置し、上記各列間の隙間上に
上記転送部のゲート電極を延在させて、このゲート電極
の電界によって上記各列間を電気的に分離するようにし
た固体撮像装置において、 上記基板またはウエルの全表面に、上記光電変換部で発
生した信号電荷と逆の導電型であって上記基板またはウ
エルよりも高濃度の不純物層を設けたことを特徴とする
固体撮像装置。
1. A plurality of rows each having a photoelectric conversion unit and a transfer unit arranged adjacent to each other and separated by a predetermined distance on the surface of a semiconductor substrate or a well, and the transfer unit is disposed in a gap between the rows. In the solid-state imaging device in which the gate electrodes of the portions are extended to electrically separate the columns by the electric field of the gate electrodes, the photoelectric conversion portions are generated on the entire surface of the substrate or the well. A solid-state imaging device, which is provided with an impurity layer having a conductivity type opposite to that of signal charges and a higher concentration than the substrate or the well.
JP2279807A 1990-10-17 1990-10-17 Solid-state imaging device Expired - Fee Related JP2695983B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2279807A JP2695983B2 (en) 1990-10-17 1990-10-17 Solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2279807A JP2695983B2 (en) 1990-10-17 1990-10-17 Solid-state imaging device

Publications (2)

Publication Number Publication Date
JPH04152675A JPH04152675A (en) 1992-05-26
JP2695983B2 true JP2695983B2 (en) 1998-01-14

Family

ID=17616194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2279807A Expired - Fee Related JP2695983B2 (en) 1990-10-17 1990-10-17 Solid-state imaging device

Country Status (1)

Country Link
JP (1) JP2695983B2 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0294568A (en) * 1988-09-30 1990-04-05 Sony Corp Manufacture of solid-state image sensing device

Also Published As

Publication number Publication date
JPH04152675A (en) 1992-05-26

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