JPH04152675A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To enable an image pickup device to be lessened in chip size without deteriorating it in performance by a method wherein a P-type impurity layer higher than a substrate or a well in impurity concentration is provided. CONSTITUTION:A P<->-type well 12 of low impurity concentration is provided to the surface 11a of an N-type semiconductor substrate 11. Photoelectric conversion parts 102 formed of an N-type impurity region 18 are disposed inside the P<->-type well 12. Furthermore, a transfer section 101 is provided adjacent to each of photoelectric conversion sections 102 interposing a P<+>-type pixel isolating region 15. The transfer section 101 is composed of an N<->-type transfer channel 14, a gate insulating film 16, and a gate electrode 17. Furthermore, a P-type impurity layer 40 higher than the P<->-type well 12 in impurity concentration is provided to all the surface 11a of the substrate 11 including a gap 20 between rows 100. A gate electrode 17 of the transfer 101 of each row 100 is made to extend over the gap 20 between the rows 100.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a solid-state imaging device, and more particularly to an interline transfer C0D (charge transfer device) type solid-state imaging device.

[Conventional technology]

Generally, this type of interline transfer CCD type solid-state imaging device is configured as shown in FIG. N-type semiconductor substrate 2! A P-type well 22 with a low impurity concentration is provided on the surface 21a, and within this P-type well 22, a plurality of photoelectric conversion sections 202 each consisting of an N-type impurity region 28 are arranged at equal intervals. Furthermore, a P′ type pixel isolation region 2
A transfer unit 201 is provided adjacent to each of the photoelectric conversion units 202 with 5 in between. Each transfer unit 201 has an N-type transfer channel 24 . It consists of a gate insulating film 26 and a gate electrode 27. Each photoelectric conversion section 202 and the transfer section 201 adjacent thereto constitute one column 200. Then, the photoelectric conversion unit 202 of each column 200 converts the incident light into a signal charge, and the generated signal charge is transferred to the column 200.
The transfer unit 201 transfers the respective information. Conventionally, the substrate surface 21a in the gap 30 between each row 200 is filled with P.
- The mold well 22 is visible, and the transfer section 201
A gate electrode 27 extends over this gap 30. The electric field at the end 27a of the gate electrode 27 causes each column 20 to
0 is electrically isolated. Note that 23 and 29 each indicate a P-type impurity layer. 29 can be omitted.

[Problem to be solved by the invention]

By the way, in recent years, the size of lenses used in solid-state imaging devices has tended to be reduced from 172 inches to 1/3 inch, and even to 174 inches, and the size of the semiconductor substrate 21 (chip size) has accordingly increased. It is desired to reduce the size of Here, the transfer unit 201. Reducing the size of the photoelectric conversion unit 202 is not preferable because it causes a decrease in performance such as maximum signal charge amount and sensitivity. For this reason,
In order to reduce the chip size without reducing performance, it is necessary to narrow the gap 30 between each row 200. However, if the gap 30 between each row 200 is simply narrowed, a short channel effect will occur, making it difficult to control the threshold value vth, and making it impossible to separate each row 200 with good controllability. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a solid-state imaging device that can suppress the short channel effect even if the gap between each row is narrowed, and can therefore reduce the chip size without degrading the performance. .

[Means to solve the problem]

In order to achieve the above object, the present invention arranges a plurality of rows each including a photoelectric conversion section and a transfer section adjacent to each other on the surface of a semiconductor substrate or a well, spaced apart by a predetermined distance, and each row In the solid-state imaging device, the gate electrode of the transfer section is extended over the gap between the columns, and the columns are electrically isolated by the electric field of the gate electrode.
N on the surface of the substrate or well in the gap between each row.
The semiconductor device is characterized by providing an impurity layer having a conductivity type opposite to that of the signal charges generated in the photoelectric conversion section, either type or P type, and having a higher concentration than the substrate or well.

[Effect]

If an impurity layer having a conductivity type opposite to that of the signal charge and having a higher concentration than the substrate or well is provided on the surface of the substrate or well in the gap between each column, the gap between each column becomes difficult to reverse. Therefore, even if the gap between the rows is narrowed, the short channel effect is suppressed, and the rows are separated with better controllability than in the past. Therefore, the chip size can be reduced without reducing performance.

【Example】

DESCRIPTION OF THE PREFERRED EMBODIMENTS The solid-state imaging device of the present invention will be described in detail below with reference to illustrated embodiments. As shown in FIG. 1, this solid-state imaging device has a P-type well 12 with a low impurity concentration on the surface 11a of an N-type semiconductor substrate II, as in the conventional case. This P-type well! A photoelectric conversion section consisting of an N-type impurity region 18 within 2! 02 are arranged side by side at equal intervals. Further, a transfer section 101 is provided adjacent to each of the photoelectric conversion sections 102 with a P'''' type pixel isolation region 15 in between. Each transfer unit 101 has an N-type transfer channel 14 . It consists of a gate insulating film 16 and a gate electrode 17. Each photoelectric conversion section 102 and the adjacent transfer section +01 constitute one column 100. Furthermore, each column 100
A P-type impurity layer 40 with a higher impurity concentration than the P-type well I2 is formed on the entire surface of the substrate 11 (which is also the surface of the P-type well 12) including the gap 20 between the substrates 11 and 20, and is shallower than the other layers. It is set up. The gate electrodes 17 of the transfer sections 101 of each column extend over the gaps 20 between the columns 100. Note that +3.19 indicates a P-type impurity layer formed under the transfer channel 14 and on the N-type impurity region 14, respectively. When there is incident light, the photoelectric conversion unit 102 in each column +00 converts the incident light into signal charges, as in the conventional case. and,
The transfer units 201 of the columns 100 transfer the generated signal charges, respectively. Furthermore, the columns 100 are electrically isolated by the electric field of the end portion 17a of the gate electrode 17 extending over the gap 20 from each column. Here, since the P-type impurity layer 40 with a higher concentration than the P- type well 12 is provided in the gap 20 between each column 100, the gap 20 is more difficult to invert than in the past. Therefore, even if the gap 20 is narrowed, it is possible to suppress the short channel effect from occurring, and it is possible to separate each row 100 with better controllability than in the past. Therefore, the chip size can be reduced without reducing performance.

【Effect of the invention】

As is clear from the above, the solid-state imaging device of the present invention is
The surface of the substrate or well in the gap between each column, which is composed of a photoelectric conversion section and a transfer section and transfers signal charges, is of the conductivity type opposite to the signal charge among P-type or N-type, and is better than the substrate or well. Since a P-type impurity layer with a high impurity concentration is also provided, even if the gap between each row is narrowed, the short channel effect can be suppressed from occurring. Therefore, the chip size can be reduced without reducing performance.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a solid-state imaging device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing the structure of a conventional interline transfer CCD type solid-state imaging device. 11...N-type semiconductor substrate, 12...P-type well, 1
3.19... P type impurity layer, 14... N- type transfer channel, I5... P" type pixel isolation region, 16... gate insulating film, 17... gate electrode,
I8...N-type impurity region, 20...Gap, 40...
- P-type impurity layer, 100...column, +01...transfer section, +02...photoelectric conversion section.

Claims (1)

[Claims] (1) On the surface of a semiconductor substrate or well, a plurality of rows each consisting of adjacent photoelectric conversion sections and transfer sections are arranged side by side with a predetermined distance apart, and the transfer section is placed in the gap between each row. In a solid-state imaging device in which a gate electrode is extended to electrically isolate the columns by an electric field of the gate electrode, N is applied to the surface of the substrate or well in the gap between the columns.
A solid-state imaging device, comprising an impurity layer having a conductivity type opposite to that of the signal charge generated in the photoelectric conversion section, among type or P type, and having a higher concentration than the substrate or well.