JP2681948B2 - Block decomposition memory control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is applied to the reproducing side of a digital VTR which converts a digital image signal into a block structure, encodes each block and records the encoded data on a recording medium. The present invention relates to a control circuit of a block decomposition memory. [Prior Art] Various attempts have been made to satisfactorily perform special reproduction of a VTR using a digital memory. For example, when reproducing a still image, only one field is output in order to eliminate rattling of the screen. However, the control using these memories is for the case of direct recording without data compression. The applicant of the present application has proposed dynamic range adaptive coding (ADRC) as one of high efficiency codes capable of compressing a high data rate digital image signal to a low data rate. ADRC converts a digital image signal into a block structure, obtains a dynamic range (difference between the maximum value and the minimum value of a block) for each block, and according to this dynamic range, pixel data after removal of the minimum value is converted into the original quantum data. Quantization is performed with a smaller number of bits than the number of encoded bits. A digital VTR using ADRC coding has the schematic structure shown in FIG. In FIG. 1, a digital video signal of which one sample is 8 bits is supplied to an input terminal indicated by 1. This input digital video signal is supplied to the blocking circuit 2. In the blocking circuit 2, a screen of 2 frames is, for example, (4 pixels × 4 lines × 2
Frame) is subdivided into blocks. The output signal of the blocking circuit 2 is supplied to the signalization circuit 3. The encoding circuit 3 is, for example, an ADRC encoding circuit, and the input digital video signal is highly efficiently encoded for each block. When the encoding circuit 3 performs variable-length encoding, a buffering circuit that suppresses the rate of output data to a predetermined value or less is provided in association with the encoding circuit 3. The output data of the encoding circuit 3 is supplied to the framing circuit 4, converted into the form of recording data, and the error correction code is encoded. The output signal of the framing circuit 4 is supplied to the rotary heads 7A and 7B via the recording amplifier 5, the terminal R of the recording / reproducing changeover switch and the rotary transformer (not shown). Recording signals are recorded on the magnetic tape 8 by the rotary heads 7A and 7B. The signal reproduced from the magnetic tape 8 by the rotary heads 7A and 7B is supplied to the frame decomposing circuit 10 via the rotary transformer (not shown), the reproducing side terminal P of the recording / reproducing changeover switch 6 and the reproducing amplifier 9. . Frame disassembly circuit 10
Then, the error correction code is decoded, and the frame decomposition circuit
The output signal of 10 is supplied to the decoding circuit 11. Decoding circuit
The original digital video signal is restored from 11 and the output signal of the decoding circuit 11 is supplied to the block decomposition circuit 12. The block decomposing circuit 12 restores the block order restoration data to the television scanning order. The output signal of the block decomposition circuit 12 is supplied to the error correction circuit 13 for recording / recording.
The error that occurred in the process of reproduction is made inconspicuous. A reproduced digital video signal is obtained at the output terminal of the error correction circuit 13. The blocking circuit 2 and the block decomposition circuit 12 described above are
The memory has a capacity of 4 frames, and two memories having a capacity of 2 frames are provided. At the time of blocking, two frames of digital video signals are written and the already written two frames of digital video signals are read out in the order of blocks. In the block disassembling circuit 12, the digital video signals for two frames written in the order of blocks are read out in the order of scanning. [Problems to be Solved by the Invention] The present invention provides a read address of a memory provided in the block decomposing circuit 12 on the reproducing side of the above digital VTR.
By controlling according to the VTR playback mode, special playback can be performed without any problems. [Means for Solving the Problems] In the present invention, a digital image signal is converted into a block structure, encoded for each block, encoded data is recorded in a recording medium, and reproduced from the recording medium. Used for a system that decodes data and restores the decoded data to its original order by a block decomposition memory.
In the block decomposition memory control circuit, generate a write address counter for storing decoded data of multiple fields and a start address of the field number preset for the block decomposition memory read address counter in the block decomposition memory In addition, the preset address generating means is provided with a reproduction mode signal indicating each of the normal reproducing operation, the high speed reproducing operation and the slow reproducing operation. An address is generated, the start address of a specific field number is repeatedly generated in the high-speed playback operation, and the start address of the field number that is repeated a number of times according to the slow ratio is generated in the slow playback operation. Is a Li of the control circuit. [Operation] The data reproduced by the digital VTR is decoded and then supplied to the block decomposing circuit. This block decomposing circuit is composed of a memory and its control circuit. A vertical counter for counting pulse signals of a field cycle synchronized with the reproduction data is provided, and an output signal of the vertical counter is supplied to the preset ROM. Preset R
A mode signal corresponding to the reproduction mode is supplied to the OM, and an output signal corresponding to the reproduction mode is generated. The output signal of the preset ROM is loaded as a head address to a read address counter that generates a read address of the memory of the block decomposition circuit. This head address corresponds to a reproduction mode such as normal reproduction, high speed reproduction, and slow motion reproduction. Therefore, the read operation of the memory for block decomposition can be controlled according to the reproduction mode, and a high quality reproduced image can be obtained. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This one embodiment is for controlling the memory of the block decomposition circuit, and the configuration of one embodiment is shown in FIG. In this embodiment, as shown in FIG. 2, one block consists of an area (4 pixels × 4 lines) of the first frame FR1 and an area (4 pixels × 4 lines) of the same position of the second frame FR2. And a region. In FIG. 2, L1 and L3 are first
Lines belonging to the field, L2 and L4 are lines belonging to the second field, L5 and L7 are lines belonging to the third field, and L6 and L8 are lines belonging to the fourth field. In Fig. 1, the frame ID signal from the input terminal 21
The FRID is supplied, and this signal FRID is differentiated by the differentiating circuit 22 to form a pulse signal FPLS generated every two frames. This pulse signal FPLS is supplied to one input terminal of the selector 23. Further, a signal DTEN ^* indicating the valid period of the reproduced data is supplied from the input terminal 24, and this signal DTEN ^* is supplied to the slow enable signal generation circuit 25. The signal SLEN generated by the slow enable signal generating circuit 25 is supplied to the differentiating circuit 26, and the output signal SPLS of the differentiating circuit 26 is selected.
23 is supplied to the other input terminal. The selector 23 is controlled by the playback mode signal from the input terminal 27, and is a pulse signal except during slow motion playback.
FPLS is selected, pulse signal during slow motion playback
SPLS is selected. The output signal of the selector 23 is supplied to the clear terminal of the vertical counter 28. This vertical counter 28
Counts the pulse signal VPLS from the input terminal 29 and generates an output signal VC. The output signal VC of the vertical counter 28 is supplied to the preset ROM 30 and the field number ROM 31. A reproduction mode signal from the input terminal 27 is supplied to the preset ROM 30 and the field number ROM 31. The output signal of the field number ROM 31 is taken out to the output terminal 32 as the output field number signal. The output signal PRR of the preset ROM 30 is supplied to the read address counter 33 of the block decomposition memory. The preset ROM 30 outputs the start address of the block decomposition memory corresponding to an arbitrary field number to the output VC of the vertical counter 28, and this start address is preset in the read address counter 33. The read address counter 33 is supplied with the pulse signal VPLS from the inverter 34 at its load terminal and counts the sample clock from the input terminal 35. The output signal of the read address counter 33 is supplied to one input terminal of the multiplexers 36 and 37. The output signals of the write address generation circuit 38 are supplied to the other input terminals of the multiplexers 36 and 37. These multiplexers 36 and 37 form an address selector of a block decomposition memory, and an output terminal 39 takes out an address signal for one of the two frame memories and an output terminal 40 takes out an address signal for the other two frame memories. FIG. 3 shows a basic timing clock in this embodiment. 3A shows an ID signal 2FRID whose level is inverted every two frames, FIG. 3B is an ID signal FRID whose level is inverted every frame, and FIG.
Is an ID signal FLID whose level is inverted for each field. FIG. 3D shows the pulse signal VPLS of the field cycle supplied from the input terminal 29, and FIG. 3E shows the differentiation circuit 22.
Pulse signal FP generated from the beginning of 2 frames
It is LS. ID signal 2FRI whose level is inverted every two frames
D is included in the reproduced signal. Each operation in the reproduction mode will be described with reference to FIGS. 4, 5, and 6. In the case of the normal reproduction operation, the data of 4 fields will be read out sequentially and regularly. FIG. 4 is a timing chart at the time of normal reproduction operation. Signal DTEN
^* Is a signal indicating a valid section of the input data to the block decomposition memory, which is a signal of two frame periods. The output signal VC of the vertical counter 28 repeatedly changes to 0, 1, 2, and 3. By supplying the output signal of the vertical counter 28 to the preset ROM 30, the head address PRR loaded from the preset ROM 30 to the read address counter 33 sequentially changes to 0, FLD, 2FLD, 3FLD. Each of 0, FLD, 2FLD, and 3FLD is the start address of the data of the first field, the second field, the third field, and the fourth field in the block decomposition memory space. In this way, the output signal P from the preset ROM 30
By generating RR, 4-field data is sequentially read from the block decomposition memory. During normal reproduction, the selector 23 selects the pulse signal FPLS generated every two frames from the differentiating circuit 22, and the pulse signal FPLS clears the vertical counter 28. During high-speed playback, as shown in the timing chart of FIG. 5, for the signal DTEN ^* that changes every two frames,
The output signal VC of the vertical counter 28 is 0, 1, 2, 3 for each field.
And change. For example, if only the first field data is read, the output signal PRR of the preset ROM 30 is always 0. Since the reproduction mode signal is supplied to the preset ROM 30, the output signal PRR as described above can be generated. The operation during slow motion reproduction will be described with reference to FIG. During slow motion playback, signal DTEN
^* Does not occur regularly every two frames. Eg ¹
At the / ₂ throw ratio, the signal DTEN ^* becomes high level every four frames, as shown in FIG. Generally 1 / N
At the slow ratio, the signal DTEN ^* has a 1 / N cycle as compared with the normal reproduction. Since the data has a block structure, a good quality reproduced image cannot be obtained unless the VTR is controlled so that the slow ratio is a whole number. When the data written in one cycle of the signal DTEN ^* is 1 / N slow ratio,
The same field is controlled to be read N times. Examples of FIG. 6 is a _^1/2 slow ratio, by a period of two fields, so as to read the data of the same field, the contents of the preset ROM30 is defined. During slow motion playback, the selector 23 is the differentiation circuit
Select the pulse signal SPLS from 26 and select this pulse signal SPLS
Thereby, the vertical counter 28 is cleared. FIG. 7 shows an example of the slow enable signal generation circuit 25. In FIG. 7, the signal DTEN ^* is supplied from the input terminal 51. This signal DTEN ^* is surrounded by a broken line.
Is supplied to the leading edge detection circuit 52, as shown in FIG.
The pulse signal DPLS generated at the leading edge of the signal DTEN ^* is obtained. The leading edge detection circuit 52 includes an inverter 53, an AND gate 54, and a D flip-flop 55. The pulse signal DPLS is input to the clock of the D flip-flop 56. Data input of D flip-flop 56 is Vcc
(Logically “1”), and its preset input is the pulse signal FPLS. The slow enable signal SLEN is generated at the output of the D flip-flop 56. This slow enable signal SLEN is supplied to the differentiating circuit 26. As shown in FIG. 6, the slow enable signal SLEN becomes "1" in synchronization with the signal DPLS and falls in synchronization with the pulse signal FPLS. The differentiating circuit 26 is composed of an inverter 58, an AND gate 59 and a D flip-flop 60, and generates a negative pulse signal SPLS (see FIG. 6) generated at the trailing edge of the signal SLEN. This pulse signal SPLS is selected by the selector 23 and supplied to the clear terminal of the vertical counter 28. Therefore, the output signal VC of the vertical counter 28 changes from 0, 1, 2, ... 7 for each field as shown in FIG. The output signal PRR of the preset ROM 30 is (0,0, FLD, FLD, ... 3FLD, 3FL, as shown in FIG.
The same start address is output for every two fields of D). Thus, when the _^1/2 slow ratio can be read the same field by 2 degrees. FIG. 8 shows another example of blocks to which the present invention can be applied. As shown in FIG. 8, the first frame FR
Two blocks are formed from a region of (4 lines × 8 pixels) of 1 and a region of (4 lines × 8 pixels) of the second frame FR2 at the same position as this region. That is, two blocks are formed by each of the pixels indicated by ◯ and the pixels indicated by ×, which are distributed in the five-eye grid pattern of the chive. With the block configuration shown in FIG. 8, the data in one block can be satisfactorily modified by the data in one block. In the output control of the memory of the block disassembling circuit, a process of restoring the two blocks having the relationship shown in FIG. 8 is performed. In this case, in the case of the block structure shown in FIG. 8, since the order of the pixel of ◯ and the pixel of × is different for each field, the output terminal 32 is determined by the field number ROM31.
The playback field number signal is generated at. [Advantages of the Invention] In the present invention, a preset ROM is provided when reproducing data is read from the memory of the block decomposing circuit, and the pulse signal and the reproducing mode signal of the field cycle are supplied to the preset ROM. Therefore, the head address according to the reproduction mode can be generated from the preset ROM, and special reproduction can be performed without any trouble.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a schematic diagram used for explaining an example of a block, FIG. 3 is a waveform diagram of a timing signal, and FIG. FIG. 5 is a timing chart used for explaining the normal reproduction operation, FIG. 5 is a timing chart used for explaining the high speed reproduction operation, FIG. 6 is a timing chart used for explaining the slow reproduction operation, and FIG. 7 is one embodiment of the present invention. 8 is a schematic block diagram of another example of a block to which the present invention can be applied, and FIG. 9 is a schematic block diagram of a digital VTR to which the present invention can be applied. Description of main symbols in the drawings 1: Blocking circuit, 3: Encoding circuit, 11: Decoding circuit, 12:
Block disassembly circuit, 28: vertical counter, 30: preset RO
M, 31: Field number ROM, 33: Read address counter.

Claims (1)

(57) [Claims] A digital image signal is converted into a block structure, encoded for each block, the encoded data is recorded on a recording medium, the data reproduced from the recording medium is decoded, and the decoded data is a block decomposition memory. In the control circuit of the block decomposing memory, which is used in a system adapted to restore the original order, a write address counter for storing the decoded data of a plurality of fields in the block decomposing memory, and A preset address generating means for generating a start address of a field number preset for the read address counter of the block decomposition memory and supplying a reproduction mode signal indicating each of a normal reproduction operation, a high speed reproduction operation and a slow reproduction operation is provided. The preset address generating means is In the normal playback operation, the start address of the field number that changes sequentially is generated, in the high-speed playback operation, the start address of the specific field number is repeatedly generated, and in the slow playback operation, the field that repeats a number of times according to the slow ratio is generated. A control circuit for a block decomposition memory, characterized in that a start address of a number is generated.