JPH07162799A - Digital video signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To record the plural input signals of an encoding rate and intra-frame encoding cycle and to provide the high-speed reproducing pictures of improved picture quality. CONSTITUTION:This device is composed of a semiconductor memory 51 for storing plural format patterns, a format flag generation circuit 52 for selecting an optimum format pattern for the digital video signals of inter-frame (field) difference encoding from the plural format patterns stored in the semiconductor memory 51 and generating a format flag, a formatter 56 for rearranging the digital video signals, a multiplexer 55 for multiplexing the digital video signals with the format flag, an error correction encoder 14, a modulator 15, a recording head 16, a magnetic tape 17, a demultiplexer 57 for demultiplexing reproducing signals into the format flag and the video signals and a deformatter 58 for reading the format pattern corresponding to the format flag from the semiconductor memory 51 and rearranging the video signals in an original order.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a recording / reproducing apparatus,
In particular, it relates to a digital video signal recording / reproducing apparatus for recording a digital video signal on a magnetic tape.

[0002]

2. Description of the Related Art In recent years, MPEG (motion picture image)
For example, a method of recording a digital video signal, which has been subjected to high-efficiency encoding using a difference between frames or fields, on a magnetic tape, such as a calling expert group), is being studied. The following is a description of a conventional digital video signal recording / reproducing apparatus for digital recording VTR (video tape recorde).
Take r) as an example. FIG. 6 is a block diagram of a video signal recording / reproducing system of a conventional digital recording VTR. In FIG. 6, 11 is an A / D converter, 12 is a video signal encoder, 13 is a formatter, 14 is an error correction encoder, 15 is a modulator, 16 is a recording head, 17 is a magnetic tape, 18
Is a reproducing head, 19 is a demodulator, 20 is an error correction decoder, 21
Is a deformatter, 22 is a video signal decoder, and 23 is D / A
It is a converter.

Digital recording V constructed as described above
Regarding TR, the operation of recording and reproducing the video signal will be described below. First, the input video signal is A / D converted by the A / D converter 11, and is differentially encoded between frames (fields) by the video signal encoder 12. The encoded video signal is rearranged according to a predetermined format pattern by the formatter 13, error-correction encoded by the error-correction encoder 14, modulated by the modulator 15, and then recorded on the magnetic tape 17 by the recording head 16. It When reproducing the digital video signal recorded in this way, first, the signal reproduced by the reproducing head 18 is demodulated by the demodulator 19 and the error correction decoder 20 performs error correction decoding. Then, after being rearranged in the original order by the deformatter 21, the video signal is decoded by the video signal decoder 22, and the video signal D / A converted by the D / A converter 23 is output.

Here, the signal input / output is an analog video signal, but the digital video signal differentially encoded between frames (fields) by a video signal encoder other than the digital recording VTR is switched to the input of the formatter 13. The input of the D / A converter 23 can be output as it is. An example of the format pattern will be described with reference to the track pattern formed on the magnetic tape 17 shown in FIG. The video signal in this example is inter-frame differentially encoded by the video signal encoder 12,
It is encoded within a frame every 5 frames. The solid line arrow represents the locus of the reproducing head 18 at 5 × speed, and the broken line arrow represents the locus of the reproducing head 18 during normal reproduction.
High-speed reproduction images are obtained by intensively arranging the data encoded in the frame in the shaded area in the figure. The formatter 13 has a circuit configuration that rearranges the input signals into such a data arrangement.

[0005]

However, in the above-mentioned conventional configuration, the formatter is designed to record the signal coded in a specific coding format so that the format pattern is optimum for special reproduction, particularly high-speed reproduction. This circuit has the problem that when recording signals with different coding rates or intra-frame (field) coding periods for high-speed playback, it is not possible to obtain a playback image with good image quality. Was. In order to solve the above-mentioned conventional problems, the present invention provides a digital video signal recording / reproducing apparatus capable of recording an input signal having a different coding rate or an intra-frame coding period to achieve high-speed reproduction with good image quality. The purpose is.

[0006]

In order to achieve the above object, the first aspect of the present invention is to provide a memory in which at least two or more kinds of predetermined format patterns are stored in advance, and a digital coded between frames (fields). The optimum format pattern for the video signal is selected from at least two types of predetermined format patterns stored in the memory, and the selected format pattern is set to 1
A flag generation circuit that generates a format flag corresponding to pair 1, a formatter that rearranges the digital video signals that have been subjected to interframe (field) differential encoding according to the selected format pattern, an output signal of the formatter, and the format Recording means for recording a flag on a recording medium, format flag detecting means for detecting the format flag from a reproduction signal, format pattern corresponding to the format flag is read from the memory, and the digital video signal is reproduced in the original order. A digital video signal recording / reproducing apparatus having a deformatter for rearranging.

A second aspect of the present invention is a digital video signal recording / reproducing apparatus which receives as input a digital video signal which is differentially encoded between frames (fields).
A format pattern generation circuit that generates an optimum format pattern for a (field) difference-encoded digital video signal, an auxiliary recording unit that stores the generated format pattern, and 1 in the generated format pattern. A flag generation circuit for generating a format flag corresponding to 1: 1, a formatter for rearranging the digital video input signal subjected to interframe (field) differential encoding according to the optimum format pattern, and an output digital video signal of the formatter Recording means for recording the format flag on a recording medium, format flag detecting means for detecting the format flag from a reproduced signal, and reading the format pattern corresponding to the format flag from the auxiliary storage means A digital video signal recording / reproducing apparatus having a deformatter for rearranging digital video signals in the original order.

[0008]

Therefore, in the first aspect of the present invention, the optimum format pattern for the input video signal is selected from the plurality of format patterns stored in advance in the memory, and the video signals are arranged in the format pattern. The data is changed and recorded, and at the time of reproduction, the format flag recorded together with the video signal is detected, the format pattern corresponding to the format flag is read from the memory, and the video signals are rearranged in the original order. In the second invention,
An optimum format pattern is generated for the input video signal, the video signal is rearranged and recorded by the format pattern, and the format pattern is stored in the memory. At the time of reproduction, the format flag recorded together with the video signal is detected, the format pattern corresponding to the format flag is read from the memory, and the video signals are rearranged in the original order.

[0009]

1 is a block diagram of a video signal recording / reproducing system of a digital recording VTR in a first embodiment of the present invention. In FIG. 1, an error correction encoder 14 and a modulator 1
5, the recording head 16, the magnetic tape 17, the reproducing head 18, the demodulator 19, and the error correction decoder 20 are the same as those used in the conventional example of FIG. 56 is a formatter, 52 is a format flag generation circuit, 58 is a deformatter, 51 and 53 are semiconductor memories, 55 is a multiplexer, 57 is a demultiplexer, 54 is a format pattern reference circuit, and the semiconductor memory 51
Is built in the VTR, and the semiconductor memory 53 is attached to the magnetic tape cassette. The error correction encoder 14, the modulator 15, and the recording head 16 constitute recording means.

Digital recording V constructed as described above
In TR, the format flag generation circuit 52 detects the cycle of the intra-frame coded frame and the coding rate of the input video signal, and reproduces at the time of high-speed reproduction at an integer multiple speed of the intra-frame coding cycle. The semiconductor memory 51 has a format pattern in which intraframe-coded frame data is intensively arranged on the locus scanned by the head.
A format flag corresponding to the selected format pattern is generated. The format pattern is a pattern such that a reproduced image of good image quality can be obtained with respect to an input video signal, at a high speed reproduction at a double speed that can be allowed by the VTR mechanical system and control system. . The format flag generated by the format flag generation circuit 52 is stored in the semiconductor memory 53, and
It is sent to the format pattern reference circuit 54 and the multiplexer 55. The format pattern reference circuit 54 reads the format pattern corresponding to the sent format flag from the semiconductor memory 51 and sends it to the formatter 56. The formatter 56 rearranges the input signals according to the format pattern. The output of the formatter 56 is multiplexed with the format flag by the multiplexer 55, error-correction encoded by the error-correction encoder 14, modulated by the modulator 15, and recorded on the magnetic tape 17 by the recording head 16. .

The signal reproduced by the reproducing head 18 is
It is demodulated by the demodulator 19, subjected to error correction decoding, and input to the demultiplexer 57. The demultiplexer 57 separates the input signal into a video signal and a format flag, and outputs the video signal and the format flag. The format flag is sent to the format pattern reference circuit 54. The format pattern reference circuit 54 reads the format pattern corresponding to the sent format flag from the semiconductor memory 51 and deforms the formatter 58.
Send to. When the format flag is not reproduced due to a scratch on the tape or a tracking error, the demultiplexer 57 sends information to the format pattern reference circuit 54 to instruct the format pattern reference circuit 54 to read the format flag from the semiconductor memory 53. The deformatter 58 rearranges the video signals in the original order by the operation opposite to that of the formatter 56 according to the format pattern, and outputs the rearranged video signals. Here, the signal input is a digital video signal, but this digital recording V
A video signal encoder may be built in TR, and a digital video signal differentially encoded between frames (fields) by the video signal encoder may be input. An example of the format pattern will be described using the track pattern formed on the magnetic tape 17 shown in FIG. The video signal in this example is an inter-frame differential encoded signal, and is intra-frame encoded every two frames. The dashed arrow indicates the trajectory of the reproducing head 18 during normal reproduction, and the solid arrow indicates 2
The loci of the reproducing head 18 at double speed are shown respectively. By arranging the intra-coded data intensively in the shaded area in the figure, a high-speed reproduction image with good image quality is obtained. Further, when recording a video signal having the same coding rate and an intra-frame coding period of 5 frames, select from the semiconductor memory 51 a format pattern such that the data arrangement shown in FIG. Can be dealt with. Therefore, in the first aspect of the present invention, based on the coding characteristics of the input signal such as the coding rate and the intra-frame coding period,
By selecting an optimum format pattern stored in the memory and rearranging and recording the input signals according to the format pattern, it is possible to obtain a reproduced image of good image quality during high speed reproduction. Note that the format pattern selection method shown in the example is an example, and an optimum format can be obtained by an arbitrary selection method. The block structure of the digital recording VTR of this embodiment is an example, and the same effect can be obtained with any structure. FIG. 3 is a block diagram of a video signal recording / reproducing system of the digital recording VTR according to the second embodiment of the present invention. In FIG. 3, an error correction encoder 14, a modulator 15, a recording head 16, a magnetic tape 17, a reproducing head 18, a demodulator 19, and an error correction decoder 20 are the same as those used in the conventional example, and , Formatter
56, multiplexer 55, demultiplexer 57 and deformatter 58 are the same as those used in the first embodiment of the present invention. 61 is a format pattern and format flag generation circuit, and 62 is a semiconductor memory.
Is attached to a magnetic tape cassette. The error correction encoder 14, the modulator 15, and the recording head 16 constitute recording means.

Digital recording V constructed as described above
In TR, the format pattern and format flag generation circuit 61 detects the cycle and the coding rate of the intra-coded frame of the input video signal, and performs high-speed reproduction at a speed that is an integer multiple of the intra-frame coding cycle. , A format pattern in which the data of the intra-coded frame is arranged intensively on the locus scanned by the reproducing head, and 1 is added to the generated format pattern.
A format flag corresponding to the pair 1 is generated. The format pattern is stored in the semiconductor memory 62, the format flag is stored in the semiconductor memory 62, and the format pattern reference circuit 54 and the multiplexer 55 are also stored.
Sent to. The format pattern reference circuit 54 reads the format pattern corresponding to the sent format flag from the semiconductor memory 62 and sends it to the formatter 56. The formatter 56 follows the format pattern
Reorder the input signals. The output of the formatter 56, after being multiplexed with the format flag by the multiplexer 55,
The data is error-correction coded by the error-correction encoder 14, modulated by the modulator 15, and recorded on the magnetic tape 17 by the recording head 16.

The signal reproduced by the reproducing head 18 is
It is demodulated by the demodulator 19, subjected to error correction decoding, and input to the demultiplexer 57. The demultiplexer 57 separates the input signal into a video signal and a format flag, and outputs the video signal and the format flag. The format flag is sent to the format pattern reference circuit 54. The format pattern reference circuit 54
The format pattern corresponding to the sent format flag is read from the semiconductor memory 62 and deformed.
Send to 58. When the format flag is not reproduced due to a scratch on the tape or a tracking error, the demultiplexer 57 sends information to the format pattern reference circuit 58 to instruct to read the format flag from the semiconductor memory 62. The deformatter 58 rearranges the video signals in the original order by the operation opposite to that of the formatter 56 according to the format pattern, and outputs the rearranged video signals. Here, the signal is input as a digital video signal, but a video signal encoder is built in this digital recording VTR, and a digital video signal that is differentially encoded between frames (fields) by the video signal encoder is input. May be An example of the format pattern will be described using the track pattern formed on the magnetic tape 17 shown in FIG. The video signal in this example is a signal that has been subjected to inter-frame differential encoding, and is 4
Intra-frame coding is performed for each frame. The broken line arrow represents the locus of the reproducing head 18 during normal reproduction, and the solid line arrow represents the locus of the reproducing head 18 at quadruple speed. By arranging the intra-coded data intensively in the shaded area in the figure, a high-speed reproduction image with good image quality can be obtained. Further, FIG. 5 shows an example of a format pattern in the case of recording video signals having the same intra-frame coding cycle and a coding rate of 1/2. When the coding rate is 1/2, the same intra-frame coded data is intensively arranged twice in the same area as that shown in FIG. obtain.

Therefore, according to the second aspect of the present invention, an optimum format pattern is generated based on the coding characteristics of the input signal such as the coding rate and the intra-frame coding period, and the input signal is generated according to the format pattern. By rearranging and recording, a reproduced image of good image quality can be obtained at high speed reproduction. Note that the format pattern generation method shown in the example is an example, and an optimum format can be obtained by an arbitrary generation method. The block structure of the digital recording VTR of this embodiment is an example.
The same effect can be obtained with any configuration.

[0015]

As described above, in the first aspect of the present invention, the optimum format pattern for the input video signal is selected from the plurality of format patterns stored in the memory in advance, and By rearranging and recording video signals in the format pattern, multiple types of input signals with different coding rates and intra-frame (field) coding periods can be displayed with good image quality without changing the circuit configuration of the formatter itself. It is possible to play at high speed. Further, in the second aspect of the present invention, an optimum format pattern is generated for an input video signal, and the video signal is rearranged and recorded in the format pattern so that the format pattern is stored in the memory in advance. , The coding rate and frame (field) of the video signal input in a more optimal format pattern.
It is possible to reproduce a plurality of types of input signals having different inner coding cycles at high speed with good image quality.

[Brief description of drawings]

FIG. 1 is a digital recording VTR of a first embodiment of the present invention.
3 is a block diagram of a recording / reproducing system for the video signal of FIG.

FIG. 2 is a digital recording VTR of the first embodiment of the present invention.
It is a figure which shows an example of the track pattern of.

FIG. 3 is a digital recording VTR of a second embodiment of the present invention.
3 is a block diagram of a recording / reproducing system for the video signal of FIG.

FIG. 4 is a digital recording VTR of the second embodiment of the present invention.
It is a figure which shows the 1st example of the track pattern of.

FIG. 5 is a digital recording VTR of the second embodiment of the present invention.
It is a figure which shows the 2nd example of the track pattern of.

FIG. 6 is a block diagram of a video signal recording / reproducing system of a conventional digital recording VTR.

FIG. 7 is a diagram showing an example of a track pattern of a conventional digital recording VTR.

[Explanation of symbols]

11 ... A / D converter, 12 ... Video signal encoder, 1
3, 56 ... Formatter, 14 ... Error correction encoder, 15 ...
Modulator, 16 ... Recording head, 17 ... Magnetic tape, 18 ... Playback head, 19 ... Demodulator, 20 ... Error correction decoder,
21, 58 ... Deformatter, 22 ... Video signal decoder,
23 ... D / A converter, 51, 53, 62 ... Semiconductor memory,
52 ... Format flag generation circuit, 54 ... Format pattern reference circuit, 55 ... Multiplexer, 57 ... Demultiplexer, 58 ... Deformatter, 61 ... Format pattern and format flag generation circuit.

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H04N 5/93 7734-5C H04N 5/93 Z

Claims (6)

[Claims] 1. A memory in which at least two or more predetermined format patterns are stored in advance, and a frame
An optimum format pattern for the (field) difference-encoded digital video signal is selected from at least two kinds of predetermined format patterns stored in the memory, and 1 is selected for the selected format pattern.
A flag generation circuit that generates a format flag corresponding to pair 1, a formatter that rearranges the digital video signals that have been subjected to interframe (field) differential encoding according to the selected format pattern, an output signal of the formatter, and the format Recording means for recording a flag on a recording medium; format flag detecting means for detecting the format flag from a reproduction signal reproduced from the recording medium; and a format pattern corresponding to the format flag read from the memory and digitally recorded. A digital video signal recording / reproducing apparatus having a deformatter for rearranging video signals in the original order. 2. A digital video signal recording / reproducing apparatus which receives a digital video signal which is differentially coded between frames (fields), and which is an optimum format for the digital video signal which is differentially coded between frames (fields). A format pattern generation circuit that generates a pattern, auxiliary recording means that stores the generated format pattern, a flag generation circuit that generates a format flag corresponding to the generated format pattern in a one-to-one correspondence, and the frame ( From the recording medium, a formatter that rearranges the inter-field differentially encoded digital video input signal according to the generated format pattern, recording means that records the output signal of the formatter and the format flag on the recording medium, and the recording medium. The former is reproduced from the reproduced signal. A digital video signal, comprising: a format flag detecting means for detecting a set flag; and a deformatter for reading out the format pattern corresponding to the format flag from the auxiliary storage means and rearranging the digital video signals in the original order. Recording / playback device. 3. The digital video signal recording / reproducing apparatus according to claim 1, wherein the format flag is recorded in an auxiliary data area on the recording medium. 4. The digital video signal recording / reproducing apparatus according to claim 1 or 2, wherein the format flag is recorded on a recording medium by being multiplexed with the digital video signal. 5. The digital video signal recording / reproducing apparatus according to claim 3 or 4, further comprising auxiliary recording means for recording the format flag on an auxiliary recording medium other than the recording medium. 6. The digital video signal recording / reproducing apparatus according to claim 5, wherein the auxiliary recording medium is a semiconductor memory attached to a cassette for accommodating a recording medium for recording a digital video signal.