JP2674969B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2674969B2 JP2674969B2 JP7095090A JP9509095A JP2674969B2 JP 2674969 B2 JP2674969 B2 JP 2674969B2 JP 7095090 A JP7095090 A JP 7095090A JP 9509095 A JP9509095 A JP 9509095A JP 2674969 B2 JP2674969 B2 JP 2674969B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding wire
- semiconductor device
- chip
- insulating film
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7865—Means for transporting the components to be connected
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にＩＣチップとリードフレームをボンディング
ワイヤにて接続する半導体装置の製造方法に関する。The present invention relates relates to a method of manufacturing a semiconductor device, a method of manufacturing a semiconductor device in particular connecting an IC chip and the lead frame at bonding wires.
【０００２】[0002]
【従来の技術】従来のボンディングワイヤの短絡防止方
法としては特開平４−１５４１３３号公報に開示されて
いる技術がある。この従来技術は、図５に示すように、
ＩＣチップ３，リードフレーム４及びボンディングワイ
ヤ２に絶縁皮膜７をコーティングして短絡を防止しよう
とするものである。この絶縁皮膜７の形成には、図６に
示すように、リードフレーム４に搭載されボンディング
ワイヤ２にて接続されたＩＣチップ３をステップ送りし
ながら絶縁剤９をスプレー８で噴霧する方法である。ス
プレー６の下部には粉散した絶縁剤９を補集するため
に、フィルターと連結された真空吸引装置１０が配置さ
れている。もう１つの絶縁皮膜７の形成方法は、図７に
示すように、内筒１３と外筒１２を同心的に立設した絶
縁剤噴流装置１１を用いて内筒１０内から絶縁剤９を盛
り上がるように噴流させリードフレーム４に搭載されボ
ンディングワイヤ２にて接続されたＩＣチップ３を表裏
逆さまにした状態でステップ送りしながら噴流する絶縁
剤９に直接、要被覆部分を接触させる方法である。2. Description of the Related Art As a conventional method for preventing a short circuit of a bonding wire, there is a technique disclosed in Japanese Patent Laid-Open No. 4-154133. This conventional technique, as shown in FIG.
The IC chip 3, the lead frame 4 and the bonding wire 2 are coated with an insulating film 7 to prevent a short circuit. As shown in FIG. 6, the insulating film 7 is formed by spraying the insulating agent 9 with the spray 8 while stepwise feeding the IC chip 3 mounted on the lead frame 4 and connected by the bonding wire 2. . A vacuum suction device 10 connected to a filter is arranged below the spray 6 in order to collect the dispersed insulating agent 9. Another method of forming the insulating film 7 is to swell the insulating agent 9 from the inside of the inner cylinder 10 by using an insulating agent jet device 11 in which an inner cylinder 13 and an outer cylinder 12 are erected concentrically as shown in FIG. In this way, the IC chip 3 mounted on the lead frame 4 and connected by the bonding wire 2 is jetted in such a manner that the IC chip 3 is turned upside down and is fed stepwise while the insulating agent 9 jetted directly contacts the portion to be covered.
【０００３】[0003]
【発明が解決しようとする課題】この従来の絶縁剤を噴
霧したり、浸漬したりして形成した絶縁皮膜は膜厚にむ
らが発生し易く、薄くなった部分でボンディングワイヤ
の流れによる短絡を起すという問題点があった。The insulating film formed by spraying or immersing the conventional insulating agent easily causes unevenness in the film thickness, and a short circuit due to the flow of the bonding wire occurs at the thinned portion. There was a problem of getting up.
【０００４】本発明の目的は、絶縁皮膜の膜厚にむらが
なく均一でボンディングワイヤ間の流れによる短絡のな
い信頼性の高い半導体装置を提供することにある。An object of the present invention is to provide a highly reliable semiconductor device in which the film thickness of the insulating film is uniform and uniform and which does not cause a short circuit due to the flow between bonding wires.
【０００５】[0005]
【０００６】[0006]
【課題を解決するための手段】 本発明の特徴は、 ＩＣチ
ップとリードフレームのインナリードをボンディングワ
イヤにて接続し、このボンディングワイヤに絶縁皮膜を
形成する工程を有する半導体装置の製造方法において、
前記ボンディングワイヤに前記絶縁皮膜を形成する工程
が、前記ＩＣチップにキャピラリにてワイヤボンディン
グする工程と、このキャピラリが移動するときに絶縁物
のスリーブを前記キャピラリの外側から供給し前記ボン
ディングワイヤを被覆し所定長さに切断する工程と、前
記ボンディングワイヤに固定する工程とを含む半導体装
置の製造方法にある。 Feature of the present invention SUMMARY OF] connects the inner leads of the IC chip and the lead frame at the bonding wires, the manufacturing method of a semiconductor device having a step of forming an insulating film on the bonding wire,
The step of forming the insulating film on the bonding wire includes a step of wire bonding the IC chip with a capillary, and a sleeve of an insulating material is supplied from the outside of the capillary to cover the bonding wire when the capillary moves. Then, the semiconductor device is cut into a predetermined length and fixed to the bonding wire.
In the method of manufacturing the device.
【０００７】本発明の他の特徴は、ＩＣチップとリード
フレームのインナリードをボンディングワイヤにて接続
し、このボンディングワイヤに絶縁皮膜を形成する工程
を有する半導体装置の製造方法において、前記ボンディ
ングワイヤに前記絶縁皮膜を形成する工程が、前記ＩＣ
チップと前記リードフレームのインナリードをキャピラ
リにてワイヤボンディングする工程と、接続された前記
ボンディングワイヤを所定長さの切り込みのある絶縁物
のスリーブで被覆し固定する工程とを含む半導体装置の
製造方法にある。 Another feature of the present invention is that in the method of manufacturing a semiconductor device, the method comprises the steps of connecting an IC chip and an inner lead of a lead frame with a bonding wire and forming an insulating film on the bonding wire. The step of forming the insulating film is the IC
A semiconductor device including a step of wire-bonding a chip and an inner lead of the lead frame with a capillary, and a step of covering and fixing the connected bonding wire with an insulative sleeve having a notch of a predetermined length .
In the manufacturing method.
【０００８】[0008]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Next, embodiments of the present invention will be described with reference to the drawings.
【０００９】図１（ａ）〜（ｃ），図２（ａ）〜（ｂ）
は本発明の第１の実施例の半導体装置の製造方法を説明
する工程順に示した側面図である。本発明の第１の実施
例は、まず、図１（ａ）に示すように、ボンディングワ
イヤ２をキャピラリ１にてリードフレーム４上に搭載さ
れたＩＣチップ３にワイヤボンディグする。次に、図１
（ｂ）に示すように、キャピラリ１が移動する時に絶縁
物５のスリーブをキャピラリ１の外側から供給しボンデ
ィングワイヤ２を被覆した後、所定の長さに切断する。
次に、図１（ｃ）に示すように、ボンディングワイヤ２
をリードフレーム４のインナーリードにワイヤボンディ
ングする。次に、図２（ａ）に示すように、プレス装置
６にて絶縁物５のスリーブを挟み込み、図２（ｂ）に示
すように、押しつぶして所定の位置に固定する。このよ
うに構成することによって、ボンディングワイヤ２が均
一の厚みの絶縁物５の皮膜に被覆されているので、流れ
てボンディングワイヤ２同志が接触しても短絡すること
はない。1A to 1C and 2A to 2B.
FIG. 3B is a side view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention in the order of steps. In the first embodiment of the present invention, first, as shown in FIG. 1A, the bonding wire 2 is wire bonded to the IC chip 3 mounted on the lead frame 4 by the capillary 1. Next, FIG.
As shown in (b), when the capillary 1 moves, the sleeve of the insulator 5 is supplied from the outside of the capillary 1 to cover the bonding wire 2 and then cut into a predetermined length.
Next, as shown in FIG. 1C, the bonding wire 2
Is wire-bonded to the inner lead of the lead frame 4. Next, as shown in FIG. 2A, the sleeve of the insulator 5 is sandwiched by the pressing device 6, and is crushed and fixed in a predetermined position as shown in FIG. 2B. With this configuration, the bonding wire 2 is covered with the film of the insulating material 5 having a uniform thickness, so that even if the bonding wires 2 come into contact with each other and flow, they will not be short-circuited.
【００１０】図３（ａ）〜（ｂ），図４（ａ）〜（ｂ）
は本発明の第２の実施例の半導体装置の製造方法を説明
する工程順に示した断面図である。本発明の第２の実施
例は、まず、図３（ａ）に示すように、絶縁物５として
切り込みの入ったスリーブを用い所定の長さに切断す
る。一方、ＩＣチップ３とリードフレーム４のインナリ
ードをボンディングワイヤ２にて接続する。次に、図３
（ｂ）に示すように、スリーブの切り込みからボンディ
ングワイヤ２を挿入し絶縁物５をボンディングワイヤ２
に被覆する。次に、図４（ａ）に示すように、プレス装
置６にて絶縁物５のスリーブを挟み込み、図４（ｂ）に
示すように、押しつぶして所定の位置に固定する。この
ように構成することによっても第１の実施例と同じ効果
が得られる。3 (a)-(b) and FIGS. 4 (a)-(b)
6A to 6D are cross-sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps. In the second embodiment of the present invention, first, as shown in FIG. 3A, a sleeve having a notch as the insulator 5 is used to cut it into a predetermined length. On the other hand, the IC chip 3 and the inner lead of the lead frame 4 are connected by the bonding wire 2. Next, FIG.
As shown in (b), the bonding wire 2 is inserted from the notch of the sleeve and the insulator 5 is attached.
To cover. Next, as shown in FIG. 4A, the sleeve of the insulator 5 is sandwiched by the pressing device 6, and is crushed and fixed at a predetermined position as shown in FIG. 4B. With this structure, the same effect as that of the first embodiment can be obtained.
【００１１】[0011]
【発明の効果】以上説明したように本発明は、ボンディ
ングワイヤに絶縁物のスリーブを被覆し固定することに
より、ばらつきのない均一な絶縁皮膜が形成できるの
で、流れによるボンディングワイヤ同志の短絡を完全に
防止し半導体装置の信頼性を高めることができるという
効果がある。As described above, according to the present invention, by covering and fixing a sleeve of an insulating material on a bonding wire, a uniform insulating film without variations can be formed, so that a short circuit between bonding wires due to a flow can be completely eliminated. Therefore, there is an effect that it is possible to improve the reliability of the semiconductor device.
【図１】（ａ）〜（ｃ）は本発明の第１の実施例の半導
体装置の製造方法を説明する工程順に示した側面図であ
る。1A to 1C are side views showing a method of manufacturing a semiconductor device according to a first exemplary embodiment of the present invention in the order of steps.
【図２】（ａ）〜（ｂ）は本発明の第１の実施例の半導
体装置の製造方法を説明する工程順に示した側面図であ
る。2 (a) and 2 (b) are side views showing the order of steps for explaining the method for manufacturing the semiconductor device of the first embodiment of the present invention.
【図３】（ａ）〜（ｂ）は本発明の第２の実施例の半導
体装置の製造方法を説明する工程順に示した側面図であ
る。FIG. 3A to FIG. 3B are side views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.
【図４】（ａ）〜（ｂ）は本発明の第２の実施例の半導
体装置の製造方法を説明する工程順に示した側面図であ
る。FIG. 4A to FIG. 4B are side views showing the order of steps for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
【図５】従来の絶縁皮膜が形成された半導体装置の一例
の部分拡大断面図である。FIG. 5 is a partially enlarged cross-sectional view of an example of a conventional semiconductor device having an insulating film formed thereon.
【図６】図５の絶縁皮膜形成方法の一例を説明する絶縁
剤噴霧装置の概略構成図である。6 is a schematic configuration diagram of an insulating agent spraying device for explaining an example of the insulating film forming method of FIG.
【図７】図５の絶縁皮膜形成方法の他の例を説明する絶
縁剤噴流装置の概略構成図である。7 is a schematic configuration diagram of an insulating agent jetting device for explaining another example of the insulating film forming method of FIG.
１ キャピラリ ２ ボンディングワイヤ ３ ＩＣチップ ４ リードフレーム ５ 絶縁物 ６ プレス装置 ７ 絶縁皮膜 ８ スプレー ９ 絶縁剤 １０ 真空吸引装置 １１ 絶縁剤噴流装置 １２ 外筒 １３ 内筒 1 Capillary 2 Bonding Wire 3 IC Chip 4 Lead Frame 5 Insulator 6 Pressing Device 7 Insulating Film 8 Spray 9 Insulating Agent 10 Vacuum Suction Device 11 Insulating Agent Jet Device 12 Outer Cylinder 13 Inner Cylinder
Claims (2)
ードをボンディングワイヤにて接続し、このボンディン
グワイヤに絶縁皮膜を形成する工程を有する半導体装置
の製造方法において、前記ボンディングワイヤに前記絶
縁皮膜を形成する工程が、前記ＩＣチップにキャピラリ
にてワイヤボンディングする工程と、このキャピラリが
移動するときに絶縁物のスリーブを前記キャピラリの外
側から供給し前記ボンディングワイヤを被覆し所定長さ
に切断する工程と、前記ボンディングワイヤに固定する
工程とを含むことを特徴とする半導体装置の製造方法。 1. A method of manufacturing a semiconductor device, comprising the step of connecting an IC chip and an inner lead of a lead frame with a bonding wire and forming an insulating film on the bonding wire, wherein the insulating film is formed on the bonding wire. A step of wire-bonding to the IC chip with a capillary; a step of supplying an insulating sleeve from the outside of the capillary to cover the bonding wire and cut to a predetermined length when the capillary moves; And a step of fixing the bonding wire to the bonding wire.
ードをボンディングワイヤにて接続し、このボンディン
グワイヤに絶縁皮膜を形成する工程を有する半導体装置
の製造方法において、前記ボンディングワイヤに前記絶
縁皮膜を形成する工程が、前記ＩＣチップと前記リード
フレームのインナリードをキャピラリにてワイヤボンデ
ィングする工程と、接続された前記ボンディングワイヤ
を所定長さの切り込みのある絶縁物のスリーブで被覆し
固定する工程とを含むことを特徴とする半導体装置の製
造方法。 2. A method for manufacturing a semiconductor device, which comprises a step of connecting an IC chip and an inner lead of a lead frame with a bonding wire and forming an insulating film on the bonding wire, wherein the insulating film is formed on the bonding wire. The step includes a step of wire-bonding the IC chip and an inner lead of the lead frame with a capillary, and a step of covering and fixing the connected bonding wire with an insulating sleeve having a notch of a predetermined length. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7095090A JP2674969B2 (en) | 1995-04-20 | 1995-04-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7095090A JP2674969B2 (en) | 1995-04-20 | 1995-04-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08288328A JPH08288328A (en) | 1996-11-01 |
| JP2674969B2 true JP2674969B2 (en) | 1997-11-12 |
Family
ID=14128224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7095090A Expired - Fee Related JP2674969B2 (en) | 1995-04-20 | 1995-04-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2674969B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0786324A (en) * | 1993-09-16 | 1995-03-31 | Hitachi Ltd | Method and device of bonding |
-
1995
- 1995-04-20 JP JP7095090A patent/JP2674969B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08288328A (en) | 1996-11-01 |
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| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970624 |
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| LAPS | Cancellation because of no payment of annual fees |