JP2657128B2 - Edge signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method for displaying a character (character, symbol, picture) for channel display, volume display, etc. on a screen of a television receiver or the like. The present invention relates to a trimming signal generating circuit for rubbing.

[0002]

2. Description of the Related Art A display device for displaying a character on a CRT screen is conventionally known. In this apparatus, for example, when displaying 24 characters × 12 lines on a screen as shown in FIG. 2, a RAM (for one screen) having addresses equal to the maximum displayable number (288 characters = 24 × 12) And a so-called character ROM having dot pattern data (FIG. 3) of all the characters to be displayed. Then, a required character code is written from the microcomputer to each address of the RAM. Then, the RAM is read out separately from the head address and applied to the character ROM to output dot pattern data of a required character from the ROM. The dot pattern data is displayed after being mixed with the video signal. In displaying characters in this manner, bordering is performed by constantly observing the output dot pattern data of the character ROM described above. For example, consider a horizontal border. FIG. 4 shows three consecutive horizontal dots of the dot pattern data of FIG.
Now, considering the reference dots D _A horizontal dot line Y _n in FIG. 4, the dot D _A itself there is no data (D _A = 0
When no data exists in one of the preceding and succeeding bits (D _C and D _B ) (D _C or D _B = 1 and dot display is performed), the dot DA is bordered. Also, the vertical direction to compare the vertical direction between the upper and lower horizontal dot line Y _{n ± 1,} based on the dot DA horizontal dot line Y _n as shown in FIG. Figure 5 there is no data in the dot DA itself, if there is at least 1 data into six one bit of the horizontal dot line Y _{n ± 1,} straining facilities edging the dot D _A. By bordering the dots in the horizontal and vertical directions in this way, a character bordered as shown in FIG. 6 can be obtained, for example. FIG. 6 shows “A”, and the rough hatched portion indicates the border.

[0003]

However, when the vertical edging is performed as shown in FIG.
M is accessed three times for each dot (one time to read the dot pattern (Y _n ) of the display character, and two times to read the dot pattern for the border (Y _n-1 and Y _{n + 1} ))
Therefore, there is a problem that the operation speed is reduced. There is also a problem that three shift registers for storing the respective dot pattern data are required for the three readings.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has a decoder for decoding vertical address data of a character to be displayed and a dot pattern data for all characters to be displayed. A memory array that stores data corresponding to a word line and, when two word lines are simultaneously selected, outputs a logical sum of corresponding two dot pattern data, and is disposed between the decoder and the memory array. After selecting an nth or n ± 1st word line in response to a control signal, the ROM including a gate circuit for selecting the n ± 1st or nth word line, and an address of a character to be displayed are stored in the ROM. ROM
And a first shift register to which dot pattern data corresponding to the nth word line of the ROM is applied, and a RAM for n ± 1st word of the ROM. A second shift register to which a logical sum output of dot pattern data corresponding to a line is applied, and first comparison means for comparing output signals of the first and second shift registers.

[0005]

According to the present invention, a gate circuit capable of switching a word line is provided between a memory decoder and a decoder of a ROM storing a dot pattern of a character to select an n-th dot line of the character. Immediately after the selection, the (n ± 1) -th dot line is simultaneously selected. Therefore, the first shift register stores the nth dot pattern data, and the second shift register stores the n ± 1st dot pattern data. Therefore, a vertical border signal can be obtained by comparing the output data of the first and second shift registers.

[0006]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
(1) is a key to a desired display position of an area to be displayed on the screen.
Generates various timing signals to generate characters
The generated display counter, (2) is the maximum table as shown in FIG.
It has an address corresponding to the number of indicated characters (24 characters x 12 lines).
And a microcomputer (not shown)
RAM storing the character code applied from
(3) shows all characters (64 types) displayed on the screen
Class) dot pattern data (12 dots x 18 dots)
), With a vertical dot pattern for each character
Data is stored in each word line (1152 lines = 64 types x 18 dots).
G) and store the two word lines at the same time.
When selected, the corresponding two vertical dot patterns
A memory array (4) for outputting a logical sum of pattern data;
Vertical direction of the character to be displayed from the display counter (1)
Address data (digits of 18 dots from 0 to 17)
And a decoder (5) for decoding the
Of the 18 bits (0 to 17) decoded by the
The data is stored in a certain cache selected in the memory array (4).
Control by applying to 18 word lines (0-17) of lactor
After selecting the nth word line according to the signal, the (n + 1) th and n
A gate circuit for simultaneously selecting the first word line
ROM for character with (6), (7) display
Said gate in response to a timing signal from the counter (1).
The gate circuit (6) selects a word line for character display (n
Line) and word line selection for border (n ± 1 line)
A control circuit for generating a control signal as shown in FIG.
Corresponding to the horizontal dot from the counter (1)
A lock signal is applied, and 12 bits are output from the memory array (4).
12-bit data corresponding to the dot pattern of
Applied in parallel to the control signal from the control circuit (7)
A first shift register for taking in data for display in response to the
(9) is a clock similar to the first shift register (8).
And data are applied, and data for bordering is
The second shift register for capturing data, (10) is the first shift register.
MSB side of the shift register (8) (X in FIG. 6).₁₁Side) Day
A third shift register to which data is serially applied, (1
1) is the data from the MSB side of the second shift register (9).
A fourth shift register to which data is serially applied, (1
2) Is the first detection that detects the vertical border of the character.
Output circuit, (13) Detects the horizontal border of the character
The second detection circuit (14) is output in the vertical and horizontal directions.
A first OR gate for generating a border signal,
Data D of third shift register (10)_AFrom character
Output terminal for extracting the signal for display16) Is
1st OR gate (14) and output terminal for display (15)
Output signal for displaying the character itself according to these signals
(Reference voltage V_AWhite level for video signal) and key
Output signal for character framing (reference voltage V_BIn video
A signal generating circuit for generating a black level with respect to the signal;
7) switch for character display or border display
This is a second OR gate for switching (18) to the b side.

In FIG. 1, a predetermined address of the RAM (2) is
The code of the character "A" as shown in FIG.
A description will be given of a case where the edging is performed as shown in FIG.
I do. According to the clock signal from the display counter (1)
RAM (2) is read from the start address
The 6-bit data indicating the code of “A” is stored in the memory array.
Applied to (4). The display at this time is “A” 1
The previous character is displayed. Then, 64 types
From the character dot pattern
Turn is selected. From 0 shown in memory array (4)
17 is a word line of the character “A” (Y in FIG. 6).₀, Y₁…
Y₁₇). On the other hand, a display counter (1)
From the RAM (2) to the decoder (5) of the ROM (3)
Character displayed at the same time as the start of reading the start address of
5-bit address to specify the vertical address of the
Dress data is applied. The address data is, for example,
If Y in FIG.₀To Y₁₇Are specified one by one in order from the top
And an 18-bit word from the decoder (5)
Line selection data is generated in parallel. The data
Is "1" for the nth word line selected,
"0" is applied to the word line. Sentence
According to the designation of the letter "A", the control circuit (7)
Control signal S on road (6)₁Is applied. Then the gate times
The path (6) is an 18-bit decoder of the decoder (5).
Output to the 18 word lines of the memory array.
I can. The vertical dot position at this time is indicated by Y in FIG.₁And provisional
Then, "0,0,0,0,0,0,0,0,0,
The dot pattern of “0,0,0” is stored in the memory array (4).
It is read and applied to the first shift register (8). This
, The control circuit (7) controls the second shift register (9)
Does not take in data. Also, the first shift
The register (8) is operated before the data of the character “A” is applied.
Now, memorize the dot pattern of the previous character,
Shift operation, and the dot pattern data is
The third shift is performed according to the clock from the display counter (1).
Applied to the register (10). And that de
Data is data D_AOutput terminal for display (1
Occurs in 5). A signal from the display output terminal (15)
Signal generation (dot display = "1")
Road (16) Switch (19) is closed and switch (1) is closed.
8) is switched to the b side, and the white level signal V _AIs transmitted
You. As a result, dots that form characters in the video signal
Signal is superimposed.

[0008] The final value of the dot pattern of the character immediately before the character "A" is sent from the first shift register (8) to the third shift register (10), and at the same time, from the memory array (4). The 12-bit dot pattern is taken into the first shift register (8) in parallel.
Then, in response to the completion of the capture, the control circuit (7)
Gate circuit (6) switches the gate circuit (6) by a control signal S ₂ to select the Y ₀ and Y ₂ in FIG. Therefore, the gate circuit (6) selects the word lines 0 and 2 of the memory array (4) at the same time. At this time, the control circuit (7)
, Prohibits the first shift register (8) from taking in data and sets the second shift register (9) into a data taking state. Therefore, FIG.
The dot position Y ₀ and Y ₂ of the dot is a logical sum output of the data "0,0,0,0,0,1,1,0,0,0,0,
"0" is generated and applied to the second shift register (9). Then, the display start timing of the character "A" comes,
The dot pattern data of the first shift register (8) starts to be applied to the third shift register (10). at the same time,
The output of the second shift register (9) is also applied to the fourth shift register (11). In a state where the data in the third and fourth shift register (10) and (11) enters all, a comparison between the data D _D to D _F on the basis of the data D _1. Data D _D to D _F indicates the presence or absence of both data in the vertical as shown in Figure 5 to the data D _A, compares both once only can perform a vertical border. For example, the position of (X ₄ , Y ₁ ) in FIG.
_At the time of _A , the data “1” at the position (X ₅ , Y ₂ ) in FIG. 6 exists in the data _DF, and the output of the first detection circuit ( 12 ) becomes “H”, 1 or gate (1
The switch (20) is closed via 4) and the switch (18) is switched to the b side. At the same time, the switch (19) is turned on by a "0" signal from the display output terminal (15).
Open. Therefore, signal V _B of the black level indicating border is generated to the video out.

Therefore, according to the circuit of FIG. 1, it is possible to perform vertical bordering in a short time.

The horizontal edging is performed by a second detection circuit (1
3), Using the third shift register (10) to
It is performed as follows. (X in FIG. 6)_Four, Y_Two) Is data D_A
, Then (X_Five, Y_Two) Position (data D_B)
Since “1” exists, the second detection circuit (13) Outputs
It becomes "H". Subsequent operations are the same as for the vertical case.
is there.

Therefore, both vertical and horizontal border display can be performed on the Y ₂ dot pattern data shown in FIG.

In the above description, the memory array (4)
For reading from, the n ± th word line is performed after the n-th word line is performed, but the reverse is also possible. In that case, the order in which the control signals S ₁ and S ₂ are generated may be switched, and the order in which the first and second shift registers (8) and (9) take in data may be switched.

Next, a specific circuit example of the gate circuit (6) in FIG. 1 will be described with reference to FIG. In FIG. 7, the control signal S
In _one mode, the terminal Y _{n +} 1, Y _n, and applies the signal (0,1,0) to Y _n-1. Further, in the mode of the control signal S _2, it applies the signal (1, 0, 1) to the terminal. By doing so, when the bit "1" of the decoder (5) is selected, the word line "1" and the word lines "0 and 2" of the memory array (4) can be switched and selected.

[0014]

As described above, according to the present invention, the character ROM is used for displaying the outline of the character.
Since the number of times of reading can be reduced as compared with the conventional one, there is an advantage that the processing speed is increased.
Further, since the number of readings is reduced, a shift register or the like for storing the number of readings becomes unnecessary, and the number of elements can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a border signal generation circuit according to the present invention.

FIG. 2 is a diagram showing character display on a CRT screen.

FIG. 3 is a diagram showing a dot pattern of each character.

FIG. 4 is a diagram for explaining a horizontal edging operation.

FIG. 5 is a diagram for explaining a vertical edging operation.

FIG. 6 is a diagram illustrating an example of a bordered character.

FIG. 7 is a specific circuit diagram of the gate circuit (6) of FIG.

[Explanation of symbols]

(1) Display counter (2) RAM (3) ROM (4) Memory array (5) Decoder (6) Gate circuit (7) Control circuit (8) First shift register (9) Second shift register ( 12 ) First detection circuit ( 13 ) Second detection circuit

Claims (2)

(57) [Claims] 1. A border signal generating circuit for displaying a framed character on a screen of a display device, comprising: a decoder for decoding vertical address data of a character to be displayed; and a dot pattern of all characters to be displayed. Data is stored in correspondence with each word line, and when two word lines are simultaneously selected, a memory array for outputting a logical sum of two corresponding dot pattern data, and a memory array between the decoder and the memory array. A ROM provided between the ROM and a gate circuit for selecting an nth or n ± 1 word line in accordance with a control signal and then selecting an n ± 1 or nth word line; A RAM for applying an address to the memory array of the ROM and designating a desired character;
A first shift register to which dot pattern data corresponding to the nth word line of the OM is applied;
A second shift register to which a logical sum output of dot pattern data corresponding to ± first word lines is applied; and first comparing means for comparing output signals of the first and second shift registers. A border signal in a vertical direction of the character is obtained from an output terminal of the first comparing means. And a second comparing means for comparing values before and after the output signal of the first shift register so that a horizontal border signal of the character is obtained from an output end of the second comparing means. 2. The border signal generation circuit according to claim 1, wherein