JPH0219463B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a character pattern reading method for a character generator used in a display device or the like.

(b) Prior Art and Problems A dot display method is one of the means for displaying characters in a character display device. This is for example
This is a method in which characters are displayed in a dot structure within a 24 x 24 (dot) square. As a memory for this character dot pattern, a memory for reading out 8 bits at a time is usually used. Therefore, the kanji (24×24)
The character pattern data displayed as dots is (24×8)
Three bit memories (M) are used.
This will be explained using a diagram. Figure 1a is the character pattern memory for the kanji ``image'', as shown in the figure.
It is composed of three memories M <sub>1</sub> , M <sub>2</sub> and M <sub>3</sub> . In this way, kanji require the maximum number of dots (24 x 24) to make up a character (this is called ``full-width''). On the other hand, alpha alphabets are sometimes displayed as (12 x 24) dots (this is called "half-width") as shown in Figure 1b, and in this case, the alphabet "A" is displayed in the memory (M ₁ +
M ₂ /2), while the alphabetic character "B" uses memory (M ₃ + M ₂ /2) to store the respective character dot pattern signals. At this time, the character pattern on the right side of the alphabet "B" is stored in the right side part of the memory _M2 (using the free space). This results in the following drawbacks. When reading the character pattern of the character "image" in FIG. 1a, the memories M ₁ , M ₂ , M ₃
It is sufficient to read in 8-bit units in this order. On the other hand, when reading the alphabetic character "A" shown in FIG. 1b, the memory _M1 is also read in 8-bit units, and then
Next, it is necessary to read the left half of memory _M2 in units of 4 bits. On the other hand, when reading the character pattern of the alphabet "B", it is necessary to read out the memory _M3 in units of 8 bits, and then read out the right half of the memory _M2 in units of 4 bits. Memory M ₁ ~ _{M 3} like this
Since the access order and the data read unit are different, there is a drawback that the character pattern read control circuit of the character generator becomes complicated.

(c) Purpose of the Invention The present invention was made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a character pattern reading method that facilitates the reading of character pattern data.

(d) Structure of the Invention The present invention has a capacity m×
A character that uses k memory sections of n bits, has a capacity of m x kn bits, constitutes a dot pattern memory section of m bits in the vertical direction and kn bits in the horizontal direction, and stores dot patterns in units of m bits in the vertical direction and kn/2 bits in the horizontal direction. The pattern generator includes a first register of n bits, a second register of n/2 bits, and means for sequentially reading and setting the contents of the storage section into the first register and the second register. , means for retrieving the contents of the first register and the contents of the second register set in the order determined by the character structure, and the dot pattern read out in units of n bits from the storage section is read out from the first register and the second register. This character pattern reading method is characterized in that after setting the dot patterns in the second register, the dot patterns in the first register and the second register are taken out in a predetermined order determined by the character structure and in units of n/2 bits.

As described above, the present invention uses three (k) storage units with a capacity of (m x n = 24 x 8 bits) to form a full-width
In the character generator that composes characters (m x kn = 24 x 3 x 8 = 24 x 24 bits), one half-width character [m x
(kn/2)] are sorted and stored in random order in the storage section, when reading out the half-width character, the character dot pattern signal in the storage section is read out to the register, and then It is designed to select predetermined data on the output side.

(e) Examples of the invention The present invention will be explained below with reference to the drawings. FIG. 2 is a book diagram illustrating one embodiment of the present invention.

In FIG. 2, character pattern signals (dot signals) of a full-width (24×24 dots) character "image" are stored in three memories (ROMs) M ₁ , M ₂ and M ₃ . Memories M ₁ to _{M 3} have a capacity of (8×24) bits. On the other hand, the character pattern signals of half-width (12×24) characters “A” and “B” are stored in the memories M ₁ ′, M ₂ ′ and
M ₃ ′, but as explained in FIG. 1b, the letter “A” is stored in memories M ₁ ′ and M ₂₁ ′,
The letter "B" is then stored in memories M ₃ ' and M ₂₂ '. Note that the memory M ₂₁ ′ and the memory M ₂₂ ′ have half the capacity of the memory M ₂ ′, and the registers R ₁ and R ₄ are (4×2) bit registers.
Registers R ₂ and R ₃ are 4-bit registers. When reading the character pattern signal of the full-width character "image", the control section 1 issues a control signal _C1 to connect the switching section 2 to contact A, and then issues a control signal _C2 . As a result, the switching units 3 and 4 switch between contacts e~
Since it is switched in the order of h, memory M ₁ to 8
Bit character pattern signal D ₁ is set in register R ₁ and character pattern signal _{D 2} from memory M 2
(8 bits) are divided into two registers _R2 and _R3 and set, and furthermore, the character pattern signal _D3 from memory _M3 is set in register _R4 . The control unit 1 is
A control signal _C3 is issued to the multiplexer 5.
This control signal _C3 is a signal for outputting the data in the registers _R1 to _R4 in units of 4 bits. Therefore, the four output terminals I, J, K of multiplexer 5
A 4-bit signal (video signal) is output from and L and sent to EOR (exclusive OR circuits) 6-9.
A control signal (a control signal for inverting the video signal) P is given to EOR6 to EOR9 from the control unit 1.
This performs video level inversion control. Further, the AND gates 10 to 13 are supplied with a blanking signal Q from the control section 1, thereby performing blanking control. AND gate 10
The video signals from ~13 are sent to parallel-to-serial conversion register 1.
4, and is sent as a serial video signal S to the display control section 15. This serial video signal S is applied to a brightness modulation circuit (not shown), and the character "image" is displayed on the display section 16.

On the other hand, in the case of half-width characters "A" and "B", the control section 1 issues the control signal C ₁ to switch the switching section 2 to the contact point B, and then issues the control signal C ₂ .
Since the switching units 4 and 17 are switched in the order of contacts e to h, the character pattern signal from the memory M ₁ '
D ₁ ' is set in register R ₁ and also
Character pattern signal D ₂₁ ′ from M ₂₁ ′ and M ₂₂ ′ and
D ₂₂ ' are set in registers R ₂ and R ₃ , respectively. Furthermore, the character pattern signal from memory M ₃ ′
D ₃ ' is set in register R ₄ . this register
When reading the signals set in _R1 to _R4 , the control section 1 issues a selection signal Z. When reading the character "A", this selection signal Z changes the signal in register _R1 by 4 bits, then the signal in register _R2 (4 bits).
bits) are output from output terminals I to L. On the other hand, in the case of the letter "B", from the output terminals I to L of the multiplexer 5, the signal of the register R ₄ (8 bits) is first read out 4 bits at a time, and then the signal of the register R ₃ (4 bits) is read out. ) is read out.
The circuit operations after EOR 6 to 9 are the same as described above, so the explanation will be omitted. As is clear from the above, memory
The character pattern signals stored in random order in _M1 ' to _M3 ' are taken out by the multiplexer 5 in video signal units of a predetermined number of bits (4 bits).

The block diagram shown in FIG. 2 has the following features and effects. The parallel-to-serial conversion register 14 in FIG. 2 requires the use of circuit elements that operate at high speed.
. In the conventional system, the video processing circuit 18 was connected after the register 14, which required high-speed circuit control.

(f) Effect of the invention The present invention has the following advantages.

(1) The ROM in which the character dot signals are stored can be read out sequentially (cyclically) regardless of the order in which they are stored, so the cycle time can be slow.

(2) ROM read control can be performed at relatively low transfer rates;
Furthermore, the read order can be controlled using registers that can operate at higher speeds than ROMs.

(3) Since the video processing circuit is located before the parallel-to-serial conversion register, the video signal can be controlled by low-speed elements, making it easy to control the display of dots on the screen.

[Brief explanation of drawings]

FIG. 1 is a memory pattern configuration diagram for explaining the present invention, and FIG. 2 is a block diagram for explaining an embodiment of the present invention. Reference symbols used in the figures are as follows. 1 is a control unit, 2, 3, 4, and 17 are switching units, 5 is a multiplexer, 6, 7, 8, and 9 are EOR (exclusive OR circuits), 10, 11, 12, and 13 are AND gates, and 14 is a register. , 15 is a display control unit, 16 is a display unit, C ₁ , C ₂ , C ₃ are control signals, CL is a clock pulse (for shifting), D ₁ , D ₂ , D ₃ , D ₁ ′, D ₂₁ ′,
D ₂₂ ′, D ₃ ′ are character pattern signals, e, f, g, h,
A and B are contacts, I, J, K, and L are output terminals, M ₁ ,
M ₂ , M ₃ , M ₁ ′, M ₂₁ ′, M ₂₂ ′, M ₃ ′ are memories (read-only memory), P is a control signal, Q is a blanking signal, R ₁ and R ₄ are registers (8-bit ), R ₂ ,
_R3 is a register (4 bits), and Z is a selection signal.

Claims (1)

[Scope of Claims] 1. Using k storage units each having a capacity of m×n bits and reading data in units of n bits, the capacity is set to m×kn bits,
In a character pattern generator that constitutes a dot pattern storage unit of m bits in the vertical direction and kn bits in the horizontal direction and stores dot patterns in units of m bits in the vertical direction and kn/2 bits in the horizontal direction, the first register of n bits and the n/2 a second register of bits; means for sequentially reading and setting the contents of the storage section in the first register and the second register; means for retrieving the contents of the second register, and after setting the dot pattern read out in units of n bits from the storage section in the first register and the second register, A character pattern reading method characterized in that a dot pattern of a register is extracted in a predetermined order determined by the character structure and in units of n/2 bits.