JP2653580B2 - Signal processing circuit of liquid crystal projection type video display - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for driving a liquid crystal panel included in a liquid crystal projection type video display.

[0002]

2. Description of the Related Art A signal processing circuit of a liquid crystal projection type video display device has to be operated at high speed because the frequency band of a video signal is wide (especially high vision). However, since the operation speed of the liquid crystal driving integrated circuit is low, it is necessary to reduce the frequency per layer by performing a multi-layer development process on the video signal.
At this time, the liquid crystal is driven by, for example, a liquid crystal driving integrated circuit arranged in the horizontal direction with the same number of layers. Further, the signal processing circuit of the device has a correction circuit for optical unevenness (shading) caused by an optical system or the like.

[0003] Furthermore, since the video signal band of Hi-Vision is a very wide band of about 30 MHz, in a system in which source driving integrated circuits (source drivers) are cascaded, the operating frequency of a shift register in the source driver is 30 MHz or more. Something is needed. However, since there is no such high-speed source driver at present, a multilayer development process for operating the source driver in parallel is required to reduce the operating frequency of the source driver.

In a signal processing circuit of this type which has been conventionally known, as shown in FIG. 7, a shading correction circuit 50 first performs shading correction of a video signal with a timing signal generated based on a synchronization signal. After that, the above-described multi-layer development processing is performed by the multi-layer development processing circuit 52.

Here, the multi-layer development processing circuit 52 shown in FIG.
As shown in FIG. 8, the number of memories corresponding to the number of source drivers of the liquid crystal panel (the number is three in the figure for convenience of explanation) is provided, and one line of video signal is divided and written. Thereafter, reading is performed simultaneously in one line period. In other words, the operating frequency is reduced to 1 / N by dividing one line of the video signal into N parts and displaying the divided parts simultaneously in one line period.

[0006]

However, as shown in FIG. 7, since the shading correction of the video signal is conventionally performed before the multi-layer expansion processing, the operating frequency of the shading correction unit must be increased. There is a disadvantage that. Further, it is difficult to perform shading correction for each block obtained by arbitrarily dividing the screen horizontally and vertically.

In addition, such a conventional method has a drawback that it is not possible to correct the variation in the voltage for driving the liquid crystal of the liquid crystal driving integrated circuit of each layer.

[0008]

In order to solve the above-mentioned problems, in the present invention, the output of each layer of the multilayer expansion processing means is subjected to shading correction independently.

[0009]

According to the present invention, the operating frequency can be lowered by performing independent shading correction for each layer output of the multilayer development processing means.

[0010]

Embodiments of the present invention will be described below in detail.

FIG. 1 is a block diagram showing an entire embodiment of the present invention. In the figure, reference numeral 2 denotes an A / D converter for inputting an analog video signal, and 4 denotes an A / D converter from the A / D converter 2.
A synchronizing signal processing unit 6 that performs a synchronizing signal process on the D-converted output and outputs a digital video signal, and a multilayer expansion processing unit 6 described later in detail, receives a digital video signal from the synchronizing signal processing unit 4. Reference numeral 7 denotes a timing signal generator for generating a timing signal (details will be described later) based on the synchronization signal, and 8A.
Reference numerals 8F to 8F denote shading correction units that independently perform shading correction on each of the layer outputs 1 to 6 from the multilayer development processing unit 6, and divide each of the layers in the vertical direction based on the timing signal from the timing signal generation unit 7. Shading correction is performed for each of the divided portions. 12A to 12F are D / A converters for D / A converting the outputs from the shading correctors 8A to 8F, and 14A to 14F are the D / A converters 1
It is a liquid crystal drive unit that inputs each analog output from 2A to 12F.

As shown in FIG. 2, each shading correction unit has a multiplier, a latch, a correction memory (shared by each layer), and an address select. 81A to 81F are multipliers to which respective outputs from the multi-layer developing unit 6 are input, and 83 is one correction memory composed of, for example, a ROM (read only memory), and is a shading for each output from the multi-layer developing unit 6. Correction information is stored. For example, shading correction information of a value from “0” to “2” every 0.001 is stored. Reference numerals 84A to 84F denote address selections, which are performed on the basis of a timing signal from the timing signal generation unit 7 in the correction memory 83 based on a plurality of shading correction information addresses from "0" to "2" for each timing signal. And outputs a signal for selecting an address corresponding to the shading correction value required for. 82A
Latches 82A to 82F are latches for sharing one correction memory 83 in each layer, and correspond to the multipliers 81A to 81F and the address selects 84A to 84F.
No. 3 latches shading correction information from the address selected by the address select.

Each address select outputs a signal for selecting an address of shading correction information required for each timing signal input based on the timing signal, and in response thereto, outputs the shading correction information taken out of the correction memory 83. Is latched by each latch. In each latch, for example, by holding the shading correction information for each scanning line, the shading correction can be easily performed with the number of blocks of (the number of multi-layered development) × (the number of arbitrary horizontal scanning lines). Since the correction is performed on a block basis, a slight positional shift of the correction information due to the latch timing can be ignored. Since the correction memory 83 is shared by each layer, the circuit scale can be reduced.

FIG. 3 shows a detailed circuit configuration of the multi-layer expansion processing section 6 shown in FIG. FIG. 4 is a timing chart showing the operation of FIG.

Next, referring to FIGS. 3 and 4, a specific operation procedure for performing the six-layer development will be described.

(1) First, a digital video signal is divided into six F
Input to an IFO (first in first out) memory.

(2) A write reset signal for resetting an internal pointer is input for writing to each FIFO memory.

(3) Write enable signals 1 to 6 for designating a writing period are input to each FIFO memory.

Here, each write enable signal is sequentially supplied for (video period) / 6 periods in order to divide the video period in 1H (horizontal scanning) of the video signal into six equal parts.

(4) A read reset signal for resetting an internal pointer for simultaneously reading data from all FIFO memories after a certain period is input.

(5) In synchronization with the read clock (1/6 frequency of the write clock), the written data is simultaneously read from all the FIFO memories during 1H of the liquid crystal panel.

FIG. 5 shows progressive scanning (non-interlaced).
FIG. 3 is a block diagram illustrating a multi-layer development processing unit 6 having a conversion function. In the figure, 21 is a line memory for inputting a digital video signal, 22 is a line interpolation adder, and 23 to 2
6 is a D-type flip-flop (FF), A0 to F0, A1
To F1, A00 to F00, A11 to F11 (A to F indicate each layer, 0000 is read in the first half of 1H, and 1, 1
1 indicates that the data is read in the latter half of 1H), respectively, are FIFO (first-in, first-out) memories, and 27 to 38 are D-type flip-flops (FF). Outputs of the D-type FFs 27 to 38 are input to independent shading correction units.

Next, the operation of FIG. 5 will be described with reference to the timing chart shown in FIG. 6 (A to F in FIG. 6 and 0,
1 corresponds to A to F and 0 (00), 1 (11) in FIG. 5, and the frequency of the write clock is の of the frequency f of the operation clock of the line memory 21).

(1) Each FIFO memory resets the write address pointer to 0 at the rise of the write clock when the write reset pulse is "L".

(2) When the write enable of each of A to F which sequentially shifts every H / 6 is "L", the corresponding FIFO memories (A0 to F0, A1 to F1) receive the FIFO memory ( A00-F00, A11-F1
1) is a falling edge of the write clock and each D-type FF 23 to 26
(The data on the input side of the line memory 21 and the data on the output side of the adder 22 are either 0 (1) or 00 (11) for each operation clock f of the line memory 21. F with)
IFO memory). At this time, the value of the write address pointer is increased by one.

(3) When the read reset pulse is "L", all FIFO memories reset the read address pointer to 0 at the rise of the read clock.

(4) When the read enable indicated by 0 or 1 is "L", the value of the read address pointer of the corresponding FIFO memory at the rising edge of the read clock (the read clock frequency is 1/6 of the write clock frequency) Is read out from each address through the respective D-type FFs 27-38. At this time, the value of the read address pointer is increased by one. Here, when the read enable is “H”, the output of the corresponding FIFO memory becomes high impedance,
Disconnected from the data bus.

Thus, data is written into each FIFO memory only for the H / 6 period, and the FIFO corresponding to the next 1H period is written.
By reading data from the memory at the same time every H / 2 period, it is possible to perform 6-time expansion and non-interlace conversion at the same time.

[0029]

As described above, according to the present invention,
The configuration is such that the shading correction is performed independently on each layer output of the multi-layer development processing means, so that the operating frequency can be lowered and the shading correction can be easily performed in blocks arbitrarily divided horizontally and vertically. it can. Further, creation of shading correction information in the correction memory becomes easy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an entire embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a shading correction unit illustrated in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a multilayer development processing unit illustrated in FIG. 1;

FIG. 4 is a timing chart showing the operation of FIG. 3;

FIG. 5 is a diagram illustrating another configuration (with a progressive scan conversion function) of the multilayer development processing unit illustrated in FIG. 1;

FIG. 6 is a timing chart showing the operation of FIG.

FIG. 7 is an explanatory diagram of a conventional technique.

FIG. 8 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

2 A / D conversion unit 4 Synchronization signal processing unit 6 Multi-layer expansion processing unit 7 Timing signal generation unit 8A to 8F Shading correction unit 12A to 12F D / A conversion unit 14A to 14F Liquid crystal driving unit A0 to F0, A00 to F00, A1 ~ F1, A11 ~ F
11 FIFO memory 81A-81F Multiplier 82A-82F Latch 83 Correction memory 84A-84F Address select

Claims (1)

(57) [Claims] 1. A signal processing circuit for driving a liquid crystal panel included in a liquid crystal projection type video display device, wherein a digital video signal is input and a multi-layer development is performed on N layers (N = 2, 3,...). A multi-layer developing means for obtaining an output having an operating frequency of 1 / N; a correction memory storing a plurality of shading correction information; and a plurality of shading correction information stored in the correction memory based on a timing signal. A plurality of address selects for outputting a signal for selecting a corresponding address with respect to each output obtained from the multi-layer developing means from the address; and shading correction information of the address selected by the address select extracted from the correction memory. And a plurality of multipliers for multiplying each output obtained from the multi-layer developing means. The signal processing circuit of the picture display device.