JP2001272969A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display images on plural display screens in parallel by reading out image data from a frame memory. SOLUTION: Image data equivalent to one frame which are read out from a frame memory 2 are written in memories 21a to 24a for every image area based on the write addresses generated by a write address generator 3a and timing pulses for write-in generated by a write pulse generator 4a. Image data for every area are read out from the memories 21a to 24a based on read addresses generated by a read address generator 5a whilst image data equivalent to a next one frame are written similarly in memories 25a to 28a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image display apparatus applied to a personal computer or the like for displaying image data on a plurality of screens.

[0002]

2. Description of the Related Art FIG. 12 shows, for example, a magazine "Interfac".
e "is a block diagram showing a configuration of a conventional image display device published in the December 1997 issue, p. 122. In the figure, reference numeral 101 denotes a CPU, which controls the entire image display device; and 102, a main storage device. A system memory stores programs and data used by the CPU 101. Reference numeral 103 denotes peripheral I / Os, and reference numeral 104 denotes a chipset, which is a CPU 101, system memories 102,
/ O103 is connected.

In FIG. 12, reference numeral 105 denotes a graphics controller for generating image data to be displayed by the image display device, and reference numeral 106 denotes a frame memory used by the graphics controller 105. 108
Reference numeral denotes a DA converter that converts image data output from the graphics controller 105 into digital / analog data and outputs the converted data. Reference numeral 109 denotes a display that displays an analog image signal output from the DA converter.

[0004] Further, in FIG.
(Peripheral Component Int
An I / O bus is used for connection between the I / O 103 and the chipset 104. 122 is AGP
(Advanced Graphics Port), which is a port connected to the graphics control 122 of the image display device.

FIG. 13 is basically the same as FIG.
This is an example in which the frame memory 110 is configured using a two-port memory.
Outputs the image data written in the frame memory 110 from the frame memory 110 directly to the DA converter 108.

Further, for example, the Nikkei microdevice 19
As published in the April 1999 issue, the graphics controller 105 and the frame memory 106 of FIG. 12 are integrated into one LSI, and the graphics controller 105 and the frame memory 110 of FIG. 13 are integrated into one. Graphics LSI 11
In some cases, it is set to 1.

Next, the operation will be described. In FIG. 13, a CPU 101 executes a chip set 104 according to programs and data stored in a system memory 102.
And an instruction for creating image data to the graphics controller 105 via the AGP 122. The graphics controller 105 receives the command from the CPU 101 and uses the image data already stored in the frame
Create image data on top.

Further, the graphics controller 10
5 outputs the image data stored in the frame memory 110 to the DA converter 108. The DA converter 108 converts the image data into an analog signal and outputs the analog signal to the display 109. The display 109 displays the analog image signal.

[0009]

Since the conventional image display device is configured as described above, the graphics LS
When the graphics controller 105 and the frame memory 110 are integrated as I111, for example, an address conversion circuit is provided between the graphics controller 105 and the frame memory 110 to convert the write address to the frame memory 110. Have difficulty. Therefore, by changing the write address to the frame memory 110, data of a plurality of display screens is written to the frame memory 110,
There is a problem that it is difficult to read image data for a plurality of display screens in parallel from 10. This is the same in the case of the graphics LSI 107 in FIG.

The present invention has been made to solve the above-described problems, and has as its object to obtain an image display device capable of reading image data from a frame memory 110 and displaying a plurality of display screens in parallel. .

[0011]

An image display apparatus according to the present invention reads out one frame of image data written in a frame memory and divides the image data into a plurality of areas to display an image. A plurality of memories that divide one frame of image data read from the memory into the plurality of regions and write the image data for each region; and a write address generation that generates a write address when the image data is written to the plurality of memories. A write pulse generator for generating a write timing pulse in accordance with the timing of a write address generated by the write address generator and sequentially outputting the write timing pulse to a memory in which image data for each area is written; To generate a read address when reading image data written to the memory And an image generator for simultaneously reading out image data for each area written in the plurality of memories based on the read address generated by the read address generator and dividing the image data into a plurality of areas for display. Things.

In the image display device according to the present invention, the clock frequency used when writing the image data into the plurality of memories is determined by dividing the number of divided areas into the clock frequency used when reading the image data from the plurality of memories. It is multiplied.

An image display device according to the present invention reads out one frame of image data which is written in a frame memory and is vertically divided into a plurality of display images, and divides the display image in a horizontal direction. And displaying the image by dividing the image data for one frame read from the frame memory into the plurality of regions and writing the image data for each region. A write address generator for generating a write address when writing image data to the memory of the memory, and a write timing pulse generated in accordance with the timing of the write address generated by the write address generator to generate an image for each area. A write pulse generator for sequentially outputting to a memory to which data is written;
A read address generator for generating a read address when reading the image data written to the plurality of memories, wherein the read address is written to the plurality of memories based on the read address generated by the read address generator. The image data of each area is read simultaneously, divided into a plurality of areas and displayed.

In the image display apparatus according to the present invention, the clock frequency used when writing the image data to the plurality of memories is the same as the clock frequency used when reading the image data from the plurality of memories. Is multiplied by the number of divisions.

The image display device according to the present invention comprises a plurality of memories for storing one frame of image data for each area.
While writing one frame of image data into one set of a plurality of memories, one frame of image data already written is read from another set of a plurality of memories.

An image display apparatus according to the present invention reads out one frame of image data which is written in a frame memory and which is divided into a plurality of display images in a vertical direction, and divides the display image in a horizontal direction. A plurality of two-port memories for dividing the image data for one frame read from the frame memory into the plurality of regions and writing the image data for each region; A write address generator that generates a write address when writing image data to the plurality of two-port memories; and a write timing pulse generated in accordance with the timing of the write address generated by the write address generator. Write pulse generator for sequentially outputting to a two-port memory where image data for each area is written Reads the image data of each area which has been written to the plurality of memories at the same time, and displays in a plurality of regions.

In the image display device according to the present invention, the clock frequency used when writing image data to the plurality of two-port memories is the same as the clock frequency used when reading image data from the plurality of two-port memories. It is obtained by multiplying the number of divisions of the image in the horizontal direction.

In the image display device according to the present invention, the period for reading out one frame of image data from the frame memory is the same as the period for reading out one frame of image data from the plurality of two-port memories.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a configuration of an image display device according to Embodiment 1 of the present invention. In the figure, reference numeral 1a denotes a graphics controller for simultaneously writing image data for one pixel, that is, 4 bytes, to the frame memory 2, and corresponds to the conventional graphics controller 105 in FIG.

In FIG. 1, reference numeral 2 denotes a frame memory. The frame memory 2 is composed of a two-port memory like the conventional frame memory 110 shown in FIG. 13, and is capable of simultaneously writing four bytes of image data from the graphics controller 1a. It is possible to read out the image data stored therein in parallel by two pixels (8 bytes) sequentially in a predetermined address order by a display frame timing signal (not shown). That is, if the image data of each pixel is written to a predetermined address of the frame memory 2, the image data of the adjacent even-numbered pixels and the image data of the odd-numbered pixels are successively arranged in parallel for each line. Can be output to

Further, in FIG. 1, 11a to 18a
Represents the image data read from the frame memory 2,
These are 8-byte data buffers for controlling writing to the memories 21a to 28a normally.
Reference numeral 8a denotes a memory capable of simultaneously writing image data output from the data buffers 11a to 18a for two pixels (8 bytes) in one clock. The memories 21a to 24a have a capacity to write one frame of image data, and the memories 25a to 28a have a capacity to write one frame of image data.

Further, in FIG. 1, 3a is a memory 21.
The write address generator 4a generates a write address when writing image data to the memory devices a to 28a. Reference numeral 4a denotes image data to be written when the image data is written to the memories 21a to 28a, and the write address generator 4a generates the image data. A write pulse generator that generates a write timing pulse in accordance with the timing of an address to be written, and a read address generator 5a that generates a read address when reading image data from the memories 21a to 28a.

In FIG. 1, reference numeral 6 designates one of the write address generated by the write address generator 3a and the read address generated by the read address generator 5a, and
An address selector 7 outputs an address to the memory 25a to select one of the write address generated by the write address generator 3a and the read address generated by the read address generator 5a. This is an address selector for outputting to the address selector 28a.

Further, in FIG.
A data selector for selecting either the output 8 bytes of the memory 1a or the output 8 bytes of the memory 25a and outputting the data in 8 bytes.
6a is a data selector which selects one of the 8 bytes of the output of 8a and outputs it in 8 bytes.
A data selector that selects either the byte or the output 8 bytes of the memory 27a and outputs the data in 8 bytes. The data 34a selects either the output 8 bytes of the memory 24a or the output 8 bytes of the memory 28a and outputs the data in 8 bytes. It is a selector.

Further, in FIG.
Are drivers for converting 8-byte width image data output from the data selectors 31a to 34a into display image signals that can be transferred by several meters, respectively.
Is a display that captures display image signals output from the drivers 41a to 44a and displays images.

Next, the operation will be described. The graphics controller 1a writes image data up to 4 bytes simultaneously in the frame memory 2 and creates image data corresponding to one frame in the frame memory 2. When a display frame timing signal (not shown) is input from the outside, the frame memory 2 sequentially reads out the image data stored therein in an order of a predetermined address with a width of 8 bytes for two pixels, and reads out the data buffer 11a. ~ 1
8a.

FIG. 2 is a diagram showing a method of dividing a display image. The resolution of the display image is 2a × 2b (a and b are even numbers)
And the coordinates of the pixel on the display screen are (x, y) (x = 0,
1, 2, 3,. . . , 2a, y = 0, 1, 2,
3,. . . , 2b). This 2a × 2b image is
Consider a case where the image is divided into four a × b images. Areas A, B, C, and D respectively are divided into areas.
And In FIG. 2, “A0: 0” indicates the 0th pixel in line 0 of the area A, and “A0: 1” indicates the area A
Indicates the first pixel in the 0 line, and “B0: a”
Indicates the a-th pixel in the 0 line of the area B, and “B
“0: a + 1” indicates the (a + 1) th pixel in the 0 line of the area B. Others are the same.

FIG. 3 is a diagram showing addresses of the frame memory 2 generated by the graphics controller 1a.
The address output by the graphics controller 1a at the time of writing the pixel data at the coordinates (x, y) is determined by the frame memory 2 after the display frame timing is given.
Out of (a × y + int (x / 2))-th image data of 8 bytes, when x is an even number, it is the address of the 0th to 3rd bytes, and when x is an odd number, it is the 4th to 4th bytes. This is a 7-byte address. Here, int (x /
2) indicates the maximum integer not exceeding x / 2, and 8 bytes to be read are 0th to 7th bytes. The graphics controller 1a writes each image data to the above address of the frame memory 2.

The following is an example of this. The graphics controller 1a writes the image data of the leftmost pixel (0th pixel) of the display line (hereinafter referred to as the 0th line) at the top of the display image and the next pixel (1st pixel) on the frame memory 2. The address is an address of the 0th to 3rd bytes and an address of the 4th to 7th bytes of the 8 byte data read out after the display frame timing signal is given. In addition, the address at which the image data of the second pixel and the third pixel of the 0th line is written is the address of the 0th to the 3rd byte of the 8 byte data read first after the display frame timing is given. And the addresses of the fourth to seventh bytes.

Hereinafter, the fourth pixel and the fifth pixel, and the sixth pixel and the seventh pixel are written to the corresponding 0th to 3rd byte addresses and 4th to 7th byte addresses, respectively. First
The 0th pixel and the 1st pixel of the line, the 2nd pixel and the 3rd pixel, etc.
The image data is written in an address to be read after all the image data of the 0th line is output. Hereinafter, the image data of the second line is written to an address to be read after all the image data of the first line is output. This is repeated below.

As described above, the 4-byte image data of the even-numbered pixels is written to the address read from the 0th to the 3rd bytes of the 8 bytes read in parallel from the frame memory 2, and the odd-numbered pixels are written. The 4-byte image data of the pixel is written to the address read from the fourth to seventh bytes of the eight bytes read in parallel from the frame memory 2.

When the display frame timing signal is given to the frame memory 2 into which the image data is written, the frame memory 2 of the 8-byte output of the frame memory 2 outputs
The image data of the even-numbered pixels on each line is read from the 0th to 3rd bytes, and the image data of the odd-numbered pixels on each line is read from the 4th to 7th bytes.
The data is sequentially read in 8 bytes in parallel for each line and output to the data buffers 11a to 18a.

The data buffer 11a passes the 8-byte image data when the image data is written to the memory 21a, and does not output any image data when the image data is read from the memory 21a. The same applies to the data buffers 12a to 18a.

When writing the 8-byte image data read from the frame memory 2 to any of the memories 21a to 28a, the write address generator 3a
A write address to be supplied to any of 1a to 28a is generated.

When writing the 8-byte image data read from the frame memory 2 into any of the memories 21a to 28a, the write pulse generator 4a generates a write address generated by the write address generator 3a. A write pulse is applied to one of the memories to which the image data is to be written, in accordance with the timing given to any of the memories 21a to 28a.

When one of the memories 21a to 24a or one of the memories 25a to 28a is in the read state, the read address generator 5a
Generate a read address given simultaneously equal to 1a-24a or 25a-28a.

The address selector 6 selects one of the write address generated by the write address generator 3a and the read address generated by the read address generator 5a, and supplies the selected address to the memories 21a to 24a.
Similarly, the address selector 7 selects one of the write address generated by the write address generator 3a and the read address generated by the read address generator 5a, and supplies the selected address to the memories 25a to 28a.

Image data of two pixels is read from the frame memory 2 at a time and written to the memories 21a to 24a. Writing and reading are performed to read image data of a total of eight pixels by two pixels from each of the memories 21a to 24a at a time. In order to match the times, the frequency of the clock used for the write operation of the memories 21a to 28a needs to be four times the frequency of the clock used for the read operation of these memories 21a to 28a.

The memory 21a stores the image data of the area A in the image data for one frame read out from the frame memory 2 by the write timing pulse generated by the write pulse generator 4a. The image data of the even-numbered pixels (4 bytes) adjacent to each other on the display line and the image data of the odd-numbered pixels (4 bytes)
At the same time).

The memory 22a stores the image data of the area B of the image data for one frame read from the frame memory 2 by the write timing pulse generated by the write pulse generator 4a. The image data of the even-numbered pixels (4 bytes) adjacent to each other on the display line and the image data of the odd-numbered pixels (4 bytes)
At the same time).

The memory 23a stores the image data of the area C in the image data of one frame read from the frame memory 2 by the write timing pulse generated by the write pulse generator 4a. The image data of the even-numbered pixels (4 bytes) adjacent to each other on the display line and the image data of the odd-numbered pixels (4 bytes)
At the same time).

The memory 24a stores the image data of the area D in the image data of one frame read from the frame memory 2 by the write timing pulse generated by the write pulse generator 4a, The image data of the even-numbered pixels (4 bytes) adjacent to each other on the display line and the image data of the odd-numbered pixels (4 bytes)
At the same time).

As described above, one frame of image data is read from the frame memory 2, and the image data of each of the areas A, B, C, and D of the one frame of image data is When the writing to the memories 21a to 24a is completed, the image data for the next one frame read from the frame memory 2 is written to the memories 25a to 28a.

The memory 25a stores the image data of the area A in the next one frame of image data read from the frame memory 2 by the write timing pulse generated by the write pulse generator 4a. The image data (for 4 bytes) of the even-numbered pixels and the image data (for 4 bytes) of the odd-numbered pixels adjacent on the same display line are simultaneously written.

The memory 26a stores the image data of the area B in the next one frame of image data read from the frame memory 2 by the write timing pulse generated by the write pulse generator 4a. The image data (for 4 bytes) of the even-numbered pixels and the image data (for 4 bytes) of the odd-numbered pixels adjacent on the same display line are simultaneously written.

The memory 27a stores the image data of the area C in the next one frame of image data read from the frame memory 2 by the write timing pulse generated by the write pulse generator 4a. The image data (for 4 bytes) of the even-numbered pixels and the image data (for 4 bytes) of the odd-numbered pixels adjacent on the same display line are simultaneously written.

The memory 28a stores the image data of the area D in the image data of the next one frame read from the frame memory 2 by the write timing pulse generated by the write pulse generator 4a. The image data (for 4 bytes) of the even-numbered pixels and the image data (for 4 bytes) of the odd-numbered pixels adjacent on the same display line are simultaneously written.

While writing image data to the memories 25a to 28a, the memories 21a to 24a store
The image data of each area of the previous frame is parallelized with the image data of the even-numbered pixels (4 bytes) and the image data of the odd-numbered pixels (4 bytes) for each memory, for a total of 8 bytes in parallel for each memory. Read out. The order in which these are read is the order in which they are written in the memories 21a to 24a. Reading from these memories 21a to 24a is performed simultaneously by four memories.

The reading of the image data of the areas A, B, C, and D for one frame from the memories 21a to 24a is completed, and the frame memory 2 is stored in the memories 25a to 28a.
, Areas A, B, C, and
When the writing of the image data of D is completed, the image data for one frame to be read next from the frame memory 2 is written to the memories 21a to 24a, and during that time, the already stored image data is read from the memories 25a to 28a. It is.

Thereafter, the image data read from the frame memory 2 is stored in the memories 21a to 24a for each frame.
And one of the memories 25a to 28a are alternately written into the memory, and the operation of reading image data from the other set is repeated during the writing.

The data selector 31a selects 8-pixel image data of 2 pixels in the area A read from the memory 21a or the memory 25a and outputs it to the driver 41a. Similarly, the data selector 32a is connected to the memory 2
2a or 2 of the area B read from the memory 26a.
The driver 42 selects 8 bytes of image data for pixels.
a, the data selector 33a selects 8-pixel image data of two pixels in the area C read from the memory 23a or the memory 27a and outputs the image data to the driver 43a. Or, for two pixels of the area D read from the memory 28a, 8
Byte image data is selected and output to the driver 44a.

The driver 41a includes a data selector 31a
The image data of 8 bytes corresponding to two pixels of the area A output from is converted into a display image signal and output to the display 51. Similarly, the driver 42a converts the image data of 8 bytes for two pixels of the area B output from the data selector 32a into a display image signal and outputs the display image signal to the display 52, and the driver 43a
Converts the image data of 8 bytes for two pixels in the area C output from the data selector 33a into a display image signal and outputs the display image signal to the display 53, and the driver 44a outputs the data of the area D output from the data selector 34a. The image data of 8 bytes for pixels is converted into a display image signal and output to the display 54.

Each of the displays 51 to 54 has a driver 4
The display image signals of the areas A, B, C, and D output from 1a to 44a are captured and displayed.

In the above example, the processing is performed for each frame of image data. However, when an interlaced scan frame signal is used, the processing may be performed for each field of image data.

In the above example, the display units 51 to 54 are separate display units. However, a single display unit and a display image corresponding to each display portion of the display units 51 to 54 are provided. The signals may be input from the drivers 41a to 44a, respectively.

Further, in the above example, four memories 21
a to 24a (or memories 25a to 28a) and an example in which an image of one frame is divided into four areas A, B, C, and D. However, two or more memories are provided and two or more memories are provided. It is also possible to divide into regions. In this case, the clock frequency used when writing the image data to the plurality of memories is obtained by multiplying the clock frequency used when reading the image data from the plurality of memories by the number of divided regions.

As described above, according to the first embodiment, in order to accumulate the image data read from the frame memory 2, eight memories 21a to 28a capable of simultaneously inputting and outputting 8 bytes are provided. The image data read from the frame memory 2 is stored in four memories 2 for each frame.
1a to 24a or 25a to 28a,
While one frame of image data is being written to the set of four memories 21a to 24a, the other set of four memories 25a to 28a stores one frame of image data that has already been stored in four parallel. Since reading is performed, image data for one frame read from the frame memory 2 can be divided into image data for each of four areas A, B, C, and D and displayed. Is obtained.

Embodiment 2 FIG. 4 is a block diagram showing a configuration of an image display device according to Embodiment 2 of the present invention. In the first embodiment, as shown in FIG.
Although the × 2b image is divided into four a × b images of regions A, B, C, and D, in the second embodiment, the region A, which has already been divided into two in the vertical direction, By dividing an a × 2b image composed of the area C and an a × 2b image composed of the area B and the area D in the horizontal direction, the areas A, B,
C and D are divided into four a × b images.

In FIG. 4, reference numeral 1b denotes a graphics controller capable of simultaneously writing image data for one pixel, that is, 4 bytes, to the frame memory 2.
The image of a × 2b composed of the area A and the area C in FIG.
Is written so as to be divided into two a × 2b images each composed of an area D and an area D.

In FIG. 4, reference numeral 2 denotes a frame memory, which is composed of a two-port memory and can simultaneously write image data of 4 bytes from the graphics controller 1b. The image data stored in the memory is sequentially converted into two pixel data (8 bytes) in a predetermined address order.
It is possible to read out each frame in parallel, which is the same as the frame memory 2 of the first embodiment. That is, if the image data of each pixel is written to a predetermined address of the frame memory 2, the image data of the adjacent even-numbered pixels and the image data of the odd-numbered pixels are successively arranged in parallel for each line. Can be read out.

Further, in FIG. 4, 11b to 18b
Represents the image data read from the frame memory 2,
Each of the data buffers is a 4-byte data buffer that controls writing to the memories 21b to 28b. The data buffers 21b to 28b can simultaneously write image data output from the data buffers 11b to 18b for one pixel (4 bytes) in one clock. Possible memory.

Further, in FIG.
b-28b, a write address generator for generating a write address when writing data to the memory 2b.
When writing the image data into 1b to 28b, a write pulse generator that generates a write timing pulse in accordance with the image data to be written and the timing of the address generated by the write address generator 3b is used as a 5b.
Is a read address generator for generating a read address when reading image data from the memories 21b to 28b.

In FIG. 4, reference numeral 6 designates one of the write address generated by the write address generator 3b and the read address generated by the read address generator 5b, and
Reference numeral 7 denotes an address selector that outputs one of the write address generated by the write address generator 3b and the read address generated by the read address generator 5b. 28b is an address selector for outputting to 28b. The address selectors 6, 7 are the same as the address selectors 6, 7 of the first embodiment.

Further, in FIG. 4, reference numeral 31b denotes a data selector for selecting either the output 4 bytes of the memory 21b or the output 4 bytes of the memory 25b and outputting it in 4 bytes. Similarly, 32b is a data selector that selects either the output 4 bytes of the memory 22b or the output 4 bytes of the memory 26b and outputs the data in 4 bytes.
Output 4 bytes of memory 23b or output 4 of memory 27b
The data selector 34b selects one of the bytes and outputs the data in 4 bytes. The data selector 34b selects either the output 4 bytes of the memory 24b or the output 4 bytes of the memory 28b.
This is a data selector that outputs data in bytes.

Further, in FIG. 4, 41b to 44b
Are data drivers for converting 4-byte image data output from the data selectors 31b to 34b into display image signals that can be transferred by several meters.
Reference numeral 54 denotes a display which captures a display image signal output from each of the drivers 41b to 44b and displays an image.

Next, the operation will be described. The graphics controller 1b writes image data up to 4 bytes simultaneously in the frame memory 2 and creates image data equivalent to one frame in the frame memory 2.
At this time, an area where the areas A and B shown in FIG.
Image data that is vertically divided into two regions, each of which has the regions B and D, is created.

FIG. 5 is a diagram showing addresses of the frame memory 2 generated by the graphics control 1b.
That is, the graphics controller 1b stores the image data in the frame memory 2 as shown in FIG.
When a display frame timing signal (not shown) is input from the outside, the frame memory 2 sequentially reads out the image data stored therein in a predetermined address order for two pixels with a width of 8 bytes and stores the image data in the data buffer 11b.
To 18b.

As shown in FIG. 2 of the first embodiment, the resolution of the display image is 2a × 2b (a and b are even numbers), and the coordinates of the pixels on the display screen are (x, y) (where, x =
0, 1, 2, 3. . . 2a, y = 0, 1, 2, 3. . .
2b), when the image data of the pixel at the coordinates (x, y) is written, the address output by the graphics controller 1b is changed to the frame memory after the display frame timing is given as shown in FIG. From 2, (a
The address (where 0 ≦ x ≦ a−1) or (a × y + (x−)) of the image data of the pixel read out from the 0th to the 3rd bytes of the 8 bytes read out at the number xy + x.
a)) The address (where a ≦ x ≦ 2a−1) of the image data of the pixel read out in the fourth to seventh bytes of the eight bytes output in the number.

The following is an example of this. The address output by the graphics controller 1b when writing the 0th pixel and the 0th pixel to the frame memory 2 is the 8th byte of the image data of the pixel read out at the 0th position after the display frame timing signal is given. 0th of
The address output from the graphics controller 1b when the graphics controller 1b writes the first pixel of the 0th line to the frame memory 2 is read first after the display frame timing signal is given. This is the address of the 0th to 3rd bytes of the 8 bytes of image data of the pixel to be read.

Similarly, the graphics controller 1b
However, the address output at the time of writing the (a-1) th pixel (the rightmost pixel of the area A) of the 0th line to the frame memory 2 is the same as the address (a-1) after the display frame timing signal is given. This is the address of the 0th to 3rd bytes of the 8 bytes of the image data of the pixel to be read first.

The graphics controller 1b
However, the address to be output when writing the 0th line a pixel (the pixel at the left end of the area B) to the frame memory 2 is:
After the display frame timing signal is given, this is the address of the 4th to 7th bytes of the 8 bytes of image data of the pixel read out at the 0th.

When the graphics controller 1 b
The address to be output when the line (a + 1) pixel (the second pixel from the left end of the area B) is written to the frame memory 2 is set to 1 after the display frame timing signal is given.
This is the address of the fourth to seventh bytes of the eight bytes of image data of the pixel to be output.

As described above, when the display frame timing signal is given, the frame memory 2 into which the image data is written, of the 8-byte output of the frame memory 2,
From the 0th to the 3rd bytes, the pixel data of the area A and subsequently the area C are sequentially read out for each line in each area and output to the data buffers 11b to 18b. Thereafter, the pixel data of the first area B and subsequently the pixel data of the area D are sequentially read out for each line in each area and output to the data buffers 11b to 18b.

When data is written into the memory 21b, the data buffer 11b receives a write timing pulse (not shown) generated by the write pulse generator 4b (not shown).
When the image data of 4 bytes of the 0th to 3rd bytes in the area A is passed, and when the memory 21b is read, no image data is output. Therefore, memory 2
The image data of the area A is written in 1b.

The data buffer 12b is provided in the memory 2
2b is written, the write pulse generator 4b
Area B by the write timing pulse generated by
When the memory 22b is read out, it does not output any image data. Therefore, the image data of the area B is written in the memory 22b.

Further, the data buffer 13b stores the write pulse generator 4 when the memory 23b is written.
By the write timing pulse generated by b, the image data of 4 bytes of the 0th to 3rd bytes in the area C is passed, and when the memory 23b is read, no image data is output. Therefore, the image data of the area C is written in the memory 23b.

Further, the data buffer 14b stores the write pulse generator 4 when the memory 24b is written.
By the write timing pulse generated by b, the image data of 4 bytes from the 4th to 7th bytes of the area D is passed, and when the memory 24b is read, no image data is output. Therefore, the image data of the area D is written in the memory 24b.

The same applies to the data buffers 15b to 18b, and the image data of the areas A, B, C and D are written in the memories 25b to 28b, respectively.

The write address generator 3b converts the 8-byte image data read from the frame memory 2 into
A write address to be supplied to any of the memories 21b to 28b when writing to any of the memories 21b to 28b by 4 bytes is generated.

The write pulse generator 4b is generated by the write address generator 3b when writing eight bytes of image data read from the frame memory 2 into any of the memories 21b to 28b, four bytes at a time. In accordance with the timing at which the write address is given to one of the memories 21b to 28b, a write timing pulse is given to the two memories to which the image data is to be written.

For example, the image data of the areas A and B which are first read from the frame memory 2 are stored in the memory 2 respectively.
1b, 22b or the memory 25b, 26b.
22b or the memories 25b and 26b,
After the writing of the image data of B is completed, the image data of the areas C and D to be read next from the frame memory 2 are:
Each of the memories 23b and 24b or the memories 27b and 28
A write timing pulse is applied to the memories 23b and 24b or the memories 27b and 28b so that the data is written to the memory b.

When one of the memories 21b to 24b or one of the memories 25b to 28b is in the read state, the read address generator 5b
Generate a read address given simultaneously and equally to 1b-24b or 25b-28b.

The address selector 6 selects one of the write address generated by the write address generator 3b and the read address generated by the read address generator 5b, and supplies the selected address to the memories 21b to 24b.
Similarly, the address selector 7 selects one of the write address generated by the write address generator 3b and the read address generated by the read address generator 5b, and supplies the selected address to the memories 25b to 28b.

Data for two pixels is read from the frame memory 2 at a time, and the memory
24b, and one pixel is read from each of the memories 21b to 24b at a time for a total of four pixels at a time.
The frequency of the clock used for the write operation of b needs to be twice the frequency of the clock used for the read operation of these memories 21b to 24b. Memory 25b-2
The same applies to 8b.

The image data of the area A output from the 0th to the 3rd bytes of the 8 bytes read from the frame memory 2 is written into the memory 21b.
In 2b, the image data of the area B output from the fourth to seventh bytes of the eight bytes read from the frame memory 2 is written.

Similarly, the image data of the area C output from the 0th to the 3rd bytes of the 8 bytes read from the frame memory 2 is written in the memory 23b, and the frame memory 2 is written in the memory 24b. Of the area D output from the 4th to 7th bytes of the 8 bytes read from.

As described above, one frame of image data is read from the frame memory 2 and the image data of each of the areas A, B, C and D of the one frame of image data is When the writing to the memories 21b to 24b is completed, the image data for the next one frame read from the frame memory 2 is written to the memories 25b to 28b.

The memory 25b stores the 0th byte of the next 1 frame of 8 bytes output from the frame memory 2.
The image data in the area A read from the third byte is written into the memory 26b, and the area output from the fourth to seventh bytes of the next one frame of eight bytes output from the frame memory 2 is written into the memory 26b. Write the B image data.

Similarly, in the memory 27b, the image data of the area C output from the 0th to the 3rd bytes of the next 1 frame of 8 bytes output from the frame memory 2 is written. The image data of the area D output from the fourth to seventh bytes of the next one frame of eight bytes output from the frame memory 2 is written to 28b.

While writing the image data into the memories 25b to 28b, the memories 21b to 24b
The image data of each area of the immediately preceding frame is read with a 4-byte width. The order of reading is the order of writing to each memory. Reading from these memories 21b to 24b is performed simultaneously for four times.

The reading of the image data of the areas A, B, C, and D for one frame from the memories 21b to 24b is completed, and the frame memory 2 is stored in the memories 25b to 28b.
, Areas A, B, C, and
When the writing of the image data of D is completed, the image data for one frame to be read next from the frame memory 2 is written to the memories 21b to 24b, and during that time, the already stored image data is read from the memories 25b to 28b. It is.

Thereafter, the image data read from the frame memory 2 is stored in the memories 21b to 24b for each frame.
, And one of the memories 25b to 28b are alternately written into the memory, while the operation of reading image data from the other set is repeated.

The data selector 31b selects one pixel and four bytes of image data of the area A read from the memory 21b or the memory 25b and outputs the same to the driver 41b. Similarly, the data selector 32b is connected to the memory 2
2b or 1 of the area B read from the memory 26b
The driver 42 selects image data of 4 bytes for pixels.
b, the data selector 33b selects one pixel of the area C read from the memory 23b or the memory 27b, and 4 bytes of image data, and outputs the selected data to the driver 43b. Alternatively, one pixel of the area D read from the memory 28b,
Byte image data is selected and output to the driver 44b.

The driver 41b includes a data selector 31b
The image data of 4 bytes corresponding to one pixel in the area A output from is converted into a display image signal and output to the display 51. Similarly, the driver 42b converts the image data of 4 bytes for one pixel of the area B output from the data selector 32b into a display image signal and outputs the display image signal to the display 52, and the driver 43b
Converts the image data of 4 bytes for one pixel of the area C output from the data selector 33b into a display image signal and outputs the display image signal to the display unit 53. The image data of 4 bytes for pixels is converted into a display image signal and output to the display 54.

The displays 51 to 54 are respectively provided with the driver 4
Display image signals of areas A, B, C, and D output from 1b to 44b are captured and displayed.

In the above example, the processing is performed for each frame of image data. However, when an interlaced scan frame signal is used, the processing may be performed for each field of image data.

In the above example, the display units 51 to 54 are separate display units. However, one display unit and a display image corresponding to each display portion of the display units 51 to 54 are provided. The signals may be input from the drivers 41b to 44b, respectively.

Further, in the above example, four memories 21
b to 24b (or memories 25b to 28b), and the image of one frame divided into two in the vertical direction of the display image is divided into two in the horizontal direction of the display image, so that the areas A, B, and C , D is divided into four, but one frame image divided into two in the vertical direction of the display image having four or more memories is divided into four or more regions. Is also possible. In this case, the clock frequency used when writing the image data to the plurality of memories is obtained by multiplying the clock frequency used when reading the image data from the plurality of memories by the number of regions divided in the horizontal direction of the display image. is there.

As described above, according to the second embodiment, eight memories 21b to 28b capable of simultaneously inputting and outputting 4 bytes are provided for storing the image data read from the frame memory 2. The image data read from the frame memory 2 is stored in four memories 2 for each frame.
1b to 24b or 25b to 28b,
While one frame of image data is being written to the set of four memories 21b to 24b, the other set of four memories 25b to 28b stores one frame of image data that has already been stored in four parallel. Since the image data is read out, the image data for one frame, which is read out from the frame memory 2 and is divided into two, is stored in the four areas A, B, C, and D.
There is an effect that the image data can be divided and displayed for each area.

Embodiment 3 In this embodiment, similarly to the second embodiment, in FIG. 2, an a × 2b image including an area A and an area C already divided in two in the vertical direction, and an area B and an area D are included. The image of a × 2b is divided into four a × b images of areas A, B, C, and D by dividing the image in the horizontal direction.

In the first and second embodiments, the image data read from the frame memory 2 is divided into two sets of memories 21a in order to divide and display the image.
When data is written in one of the storages, the data is read out from the other when the data is written to one of the storages 28a or 21b to 28b. In the third embodiment, a two-port memory is used. Thus, writing and reading are simultaneously performed by one set of memories.

FIG. 6 is a block diagram showing a configuration of an image display device according to Embodiment 3 of the present invention. In the figure,
Graphics controller 1b, frame memory 2,
The drivers 41b to 44b and the indicators 51 to 54 have the same configuration as that of the second embodiment shown in FIG. That is, the graphics controller 1b controls the area A and the area C in FIG.
A × 2b image consisting of a × b consisting of area B and area D
The image is written so as to be divided into two of the image 2b.

In FIG. 6, reference numerals 61 to 64 denote 2-port memories capable of inputting 4 bytes and outputting 4 bytes and having input terminals and output terminals independent of each other. Reference numeral 3c denotes an address for writing the image data of 8 bytes for two pixels read from the frame memory 2 to two of the two-port memories 61 to 64 by four bytes for each pixel. Write address generator
4c is 2 pixels 8 read from the frame memory 2.
When writing byte image data into two 2-port memories of the 2-port memories 61 to 64 by 4 bytes for each pixel, the image data is synchronized with the address generated by the write address generator 3c. It is a write pulse generator that supplies write timing pulses to two 2-port memories to which data is to be written.

Next, the operation will be described. Embodiment 1
As shown in FIG. 2, the resolution of the display image is 2a × 2b.
(A and b are even numbers), and the coordinates of the pixels on the display screen are (x, y) (where x = 0, 1, 2, 3,... 2)
a, y = 0, 1, 2, 3,. . . 2b), the address output by the graphics controller 1b at the time of writing the image data of the pixel at the coordinates (x, y) becomes the frame after the display frame timing signal is given as shown in FIG. The address (where 0 ≦ x) of the image data of the pixel read out from the memory 2 to the 0th to 3rd bytes of the 8 bytes read out at the (a × y + x) th
≦ a−1) or the address of the image data of the pixel read out in the fourth to seventh bytes of the eight bytes read out in the (a × y + (x−a)) number (where a ≦ x ≦ 2a−
1). And the graphics controller 1b
Writes each image data to each address.

As described above, when the display frame timing signal is given, the frame memory 2 into which the image data is written, out of the 8-byte output of the frame memory 2,
From the 0th to 3rd bytes, the image data of the first area A and subsequently the area C are read, and from the 4th to 7th bytes, the image data of the first area B and subsequently the area D are read. The data is sequentially read out for each line (a pixel) in each area and output to the two-port memories 61 to 64.

FIG. 7 is a timing chart showing the read operation of the frame memory 2. The operation clock at this time is C1. After the display frame timing signal is given, after T1 clocks including the display frame timing signal, in a clock period, image data (1a) corresponding to a pixel in the A region and 2a pixel in the B region is a pixel. (For the line).
Then, after stopping reading for T2 clock periods,
Again in a clock periods, the image data of 2a pixels (1
(For the line).

Thereafter, the reading of the image data of 2a pixels is repeated every (T2 + a) clock periods in this manner, whereby the image data of 1a × 2b pixels (1
When the reading of (for the frame) is completed, the reading is stopped for T3 clock periods from that point in time, and then the next display frame timing signal is input to the frame memory 2. After this display frame timing signal is given, after a lapse of T1 clock periods including the display frame timing signal,
Reading of image data is performed in the same manner as described above.

When the two-port memories 61 to 64 are supplied with a display frame timing signal (not shown) (different from the display frame timing signal supplied to the frame memory 2), the two-port memories 61 to 64 store the image data stored therein. It has the function of sequentially reading out one pixel at a 4-byte width in the determined address order.

FIG. 8 is a timing chart showing the read operation of the two-port memories 61 to 64. The operation clock at this time is C2. In a certain two-port memory, after a display frame timing signal is given,
After T4 clock periods including the display frame timing signal, image data for a pixel is read out in a clock periods. Then, after stopping reading for T5 clock periods, image data for a pixel is read again in a clock periods.

Thereafter, by repeating the reading of the image data for the a pixel at every (T5 + a) clocks, when the reading of the image data for the a × b pixels is completed, the reading is started at the time T6. Then, the next display frame timing signal is input to the two-port memory. After the display frame timing signal is supplied, after a lapse of T4 clock periods including the display frame timing signal, the image data is read out in the same manner as described above.

As described above, the image data for two pixels is read out from the frame memory 2 at a time, and is written to the two-port memories 61 to 64 by one set of two two-port memories, and one pixel at a time from the two-port memories 61 to 64. Since a total of four pixels are read at one time, the clock frequency C1 used for the write operation of the two-port memories 61 to 64 is used for the read operation of the two-port memories 61 to 64 so that the write and read times are matched. Twice as high as the frequency C2 of the clock to be generated.

The cycle of the display frame timing signal applied to the frame memory 2 and the cycle of the display frame timing signal applied separately to the two-port memories 61 to 64 are the same. The number of clocks (T2 + a) in FIG. 7 is equal to the number of clocks (T5 + a) in FIG. 8, and the frequency of the clock C1 is twice the frequency of the clock C2.
The time required for a) is one half of the time required for the number of clocks (T5 + a).

The areas A, B,
Each image data belonging to C and D is written to the two-port memories 61 to 64, respectively. At this time, when a display frame timing signal is given to the two-port memories 61 to 64, the write address generator 3c generates an address that is read out by four bytes for one pixel in the order of sequential writing. In accordance with the timing of the address generated by the write address generator 3c, the write pulse generator 4c
4 bytes of image data for each pixel to be written 2
Image data is written by supplying a write timing pulse to the two 2-port memories.

Therefore, when the display frame timing signal is given to the frame memory 2 and the image data starts to be output from the frame memory 2, the area A and the area B
Is read, and the write address generator 3
Write address from c and write pulse generator 4c
The image data of the area A is written to the two-port memory 61 and the image data of the area B is written to the two-port memory 62 by the timing pulse of writing from.

After the reading of the area A and the area B from the frame memory 2 is completed, the reading of the image data of the area C and the area D starts, and the image data of the area C is written by the write address from the write address generator 3c. And the write timing pulse from the write pulse generator 4c, the data is written to the two-port memory 63, and the image data in the area D is written to the two-port memory 64.

All the image data in the area C and the area D are read from the frame memory 2 and the write address generator 3
Write address from c and write pulse generator 4c
When these image data are written into the two-port memories 63 and 64 by the timing pulse of writing from the frame memory 2, the reading of the frame memory 2 is stopped.

When the next display frame timing signal is newly given to the frame memory 2, first, the area A
And the image data in the area B are read, and the write address from the write address generator 3c and the write timing pulse from the write pulse generator 4c determine
The data is written to the two-port memories 61 and 62, respectively. Next, when the image data of the area C and the area D are read from the frame memory 2, the two-port memories 63 and 64 are respectively read.
Is written to. Thereafter, the above operation is repeated.

While writing to the two-port memories 61 to 64 is being performed, these two-port memories 61 to 6
The reading of the image data from No. 4 is performed as follows.

When a display frame timing signal is supplied to the frame memory 2, first, the two-port memories 61 and 62
Are written in areas A and B, respectively,
After all the image data of B are written, for example, after the writing of the first a image data of each of the areas C and D is completed in the two-port memories 63 and 64, all the two-port memories 61 are read. By simultaneously providing the display frame timing signals to the .about.64, the reading of the two-port memories 61 to 64 starts simultaneously.

The cycle of the display frame timing signal applied to the frame memory 2 and the cycle of the display frame timing signal applied separately to the two-port memories 61 to 64 are the same. The frequency of the clock C1 used for reading from the frame memory 2 and writing to the two-port memories 61 to 64 is the same as that of the two-port memory 6.
2 of the clock frequency C2 used for reading 1 to 64
Use a frequency that is twice as high. At this time, the period of writing (a (T2 + a) C1 clock periods) image data for a pixel into a certain two-port memory is the period ((T5 + a) number of (T5 + a) image data to be read from the two-port memory). C2 clock).

Further, the period of the display frame timing signal applied to the frame memory 2 is (T1 + (T2 +
a) × 2b + T3) clock periods are equal to (T4 + (T5 + a) × b + T6) clock periods, which are the periods of the display frame timing signals supplied to the two-port memories 61 to 64, so that T1 and T3 are equal. , T4
Select T6. At this time, since the frequency of the clock C1 is twice the frequency of the clock C2, the number of clocks (T
(1 + T3) is twice the number of clocks (T4 + T6).

Areas A, B, C, and D read from each of the two-port memories 61 to 64 by 4 bytes per clock.
Are output to the drivers 41b to 44b, respectively. The drivers 41b to 44b convert the input image data of the areas A, B, C, and D into serial signals that can be transferred by several meters, and output the serial signals to the displays 51 to 54, respectively. The displays 51 to 54 display the images of the areas A, B, C, and D by inputting the serial signal.

In the above example, the processing is performed for each frame of image data. However, when an interlaced scan frame signal is used, the processing may be performed for each field of image data.

In the above example, the display units 51 to 54 are separate display units. However, one display unit and an image corresponding to each display portion of the display units 51 to 54 are displayed. May be input from the drivers 41b to 44b, respectively.

Further, in the above example, one two-port memory 61 to 64 is provided, and one frame image which is divided into two in the vertical direction of the display image is divided into two in the horizontal direction of the display image. Has shown an example in which the image is divided into four regions A, B, C, and D. However, an image of one frame which is provided with a plurality of four or more two-port memories and is divided into two in the vertical direction of the display image, It is also possible to divide into four or more regions. In this case, the clock frequency used when writing the image data to the plurality of two-port memories is the clock frequency used when reading the image data from the plurality of two-port memories, and the number of areas divided in the horizontal direction of the display image. It is multiplied.

As described above, according to the third embodiment, in order to accumulate the image data read from the frame memory 2, the four 2 bytes that can be simultaneously input and output by 4 bytes are used.
A clock used for writing to the two-port memories 61 to 64 by dividing the image data read from the frame memory 2 into four two-port memories 61 to 64 for each frame and storing the divided image data; Frequency C1
Is twice the frequency C2 of the clock used for reading, and the areas A, B, C, and D are stored in each of the two-port memories 61 to 64.
Is the same as the cycle for reading all the image data in the same area from each of the two-port memories 61 to 64, so that it is divided into two that are read from the frame memory 2. The image data for a frame can be divided into image data for each of four areas A, B, C, and D and displayed, and a two-port memory 61 for storing image data output from the frame memory 2 64, and the input data width of the two-port memories 61 to 64 for writing the image data output from the frame memory 2 can be reduced, and the writing and reading of the two-port memories 61 to 64 can be performed. Is easily controlled.

Embodiment 4 FIG. 9 is a block diagram showing a configuration of an image display device according to Embodiment 4 of the present invention. FIG. 10 shows an image dividing method according to the fourth embodiment. In the second embodiment, as shown in FIG. 2, an a × 2b image including an area A and an area C that has already been divided into two in the vertical direction and an a × 2b image including an area B and an area D
The image of x2b was divided into four axb images of areas A, B, C, and D by dividing the image in the horizontal direction. In the fourth embodiment, as shown in FIG. The a × 2b image including the areas A and E, the areas B and F, the areas C and G, and the areas D and H, which are already divided into four in the vertical direction, is divided in the horizontal direction. By doing
The image is divided into eight a × b images of areas A, B, C, D, E, F, G, and H.

In FIG. 9, reference numeral 1c denotes a graphics controller capable of simultaneously writing image data for one pixel, that is, 4 bytes, to the frame memory 2.
The data is written so as to be divided into four areas of a × 2b, which are areas A and E, areas B and F, areas C and G, and areas D and H in FIG.

In FIG. 9, reference numeral 2 denotes a frame memory, which is composed of a two-port memory. Image data from the graphics controller 1c can be simultaneously written for four bytes. , It is possible to sequentially read out four pixel data (16 bytes) in parallel in a predetermined address order. FIG. 11 is a diagram showing addresses of the frame memory 2 generated by the graphics controller 1c. That is, if the image data of each pixel is written to a predetermined address of the frame memory 2, each of the areas A and E, the area B and the area F, the area C and the area G, the area D and the area H Pixels in the area can be read in parallel as shown in FIG.

Further, in FIG. 9, 11c to 14c,
11d to 14d, 15c to 18c, 15d to 18d
The image data read from the frame memory 2 is stored in the memories 21c to 24c, 21d to 24d, and 25c to 25c, respectively.
A 4-byte data buffer for controlling writing to 28c, 25d to 28d, and 21c to 24c, 21d to 2
4d, 25c to 28c and 25d to 28d are data buffers 11c to 14c, 11d to 14d, and 15c, respectively.
18c, 15d-18d is a memory capable of simultaneously writing one pixel (4 bytes) of image data in one clock.

Further, in FIG. 9, 3d is the memory 21
c to 24c, 21d to 24d, 25c to 28c, 25d
Write address generator for generating a write address when writing data to .about.28d.
c to 24c, 21d to 24d, 25c to 28c, 25d
When writing image data to the memory address 28d, a write pulse generator that generates a write timing pulse in accordance with the image data to be written and the timing of the address generated by the write address generator 3d is provided. 24c, 21d to 24d, 25c to 28
c, a read address generator for generating a read address when reading image data from 25d to 28d.

Further, in FIG. 9, reference numeral 6 designates one of the write address generated by the write address generator 3d and the read address generated by the read address generator 5c, and
An address selector 7 outputs one of the write address generated by the write address generator 3d and the read address generated by the read address generator 5c. , Address selectors for outputting to the memories 25c to 28c and 25d to 28d.

Further, in FIG. 9, reference numeral 31c denotes a data selector for selecting either the output 4 bytes of the memory 21c or the output 4 bytes of the memory 25c and outputting it in 4 bytes. Similarly, 32c is a data selector that selects either the output 4 bytes of the memory 22c or the output 4 bytes of the memory 26c and outputs the data in 4 bytes.
Output 4 bytes of memory 23c or output 4 of memory 27c
A data selector that selects either one of the bytes and outputs the data in 4 bytes. The data selector 34c selects either the output 4 bytes of the memory 24c or the output 4 bytes of the memory 28c.
This is a data selector that outputs data in bytes. 35c-38
c is a similar data selector.

Further, in FIG. 9, 41c to 48c
Are data drivers for converting 4-byte image data output from the data selectors 31c to 38c into display image signals that can be transferred by several meters.
Reference numeral 58 denotes a display that captures display image signals output from the drivers 41c to 48c and displays an image.

Next, the operation will be described. The graphics controller 1c writes image data of up to 4 bytes simultaneously in the frame memory 2 and creates image data corresponding to one frame in the frame memory 2. At this time, the areas A and E shown in FIG. Divided into four regions in the vertical direction including a single region, a single region B and F, a single region C and G, and a single region D and H. Create image data.

That is, the graphics controller 1
c stores image data in the frame memory 2 as shown in FIG. When a display frame timing signal (not shown) is input from the outside, the frame memory 2 sequentially reads the image data stored therein in a predetermined address order for four pixels in a 16-byte width, and stores the data in a data buffer. 11c-14c, 11d-14d, 15c
To 18c and 15d to 18d.

As shown in FIG. 10, the resolution of the display image is 4a × 2b (a and b are even numbers), and the coordinates of the pixels on the display screen are (x, y) (where x = 0, 1 , 2,
3. . . 4a, y = 0, 1, 2, 3. . . 2b), when writing the image data of the pixel at the coordinates (x, y), the address output by the graphics controller 1c is changed to the frame memory after the display frame timing is given as shown in FIG. From 2, (a × y + x)
The address of the image data of the pixel read in the 0th to 3rd bytes of the 16 bytes read out in the
0 ≦ x ≦ a−1) or the address of the image data of the pixel read out in the fourth to seventh bytes of the 16 bytes output in the (a × y + (x−a)) number (where a ≦ x ≦
2a-1) or the address of the image data of the pixel read out in the eighth to eleventh bytes of the 16 bytes output in the (a × y + (x−2a)) number (where 2a ≦ x ≦
3a-1) or the address of the image data of the pixel read out at the twelfth to fifteenth bytes of the 16 bytes output at the (a × y + (x−3a)) number (where 3a ≦ x
≦ 4a-1).

The following is an example of this. The address output by the graphics controller 1c when writing the 0th pixel and the 0th pixel to the frame memory 2 is the address of the 16 bytes of image data of the pixel read out at the 0th position after the display frame timing signal is given. The address output from the graphics controller 1b when the graphics controller 1b writes the first pixel on the 0th line to the frame memory 2 is 1 address after the display frame timing signal is given. This is the address of the 0th to 3rd bytes of the 16 bytes of image data of the pixel to be read first.

Similarly, the graphics controller 1c
However, the address output at the time of writing the (a-1) th pixel (the rightmost pixel of the area A) of the 0th line to the frame memory 2 is the same as the address (a-1) after the display frame timing signal is given. The image data 16 of the pixel to be read first
This is the address of the 0th to 3rd bytes of the byte.

Further, the graphics controller 1c
However, the address to be output when writing the 0th line a pixel (the pixel at the left end of the area B) to the frame memory 2 is:
After the display frame timing signal is given, this is the address of the fourth to seventh bytes of the 16 bytes of image data of the pixel read out at the 0th.

Further, the graphics controller 1c
Is the (a + 1) th pixel on the 0th line (2 pixels from the left end of region B).
The address output at the time of writing to the frame memory 2 of the (pixel) is the fourth to seventh bytes of the 16 bytes of image data of the pixel output first after the display frame timing signal is given. Address.

Further, the graphics controller 1c
However, the address output when the 0th line 2a pixel (the left end pixel of the area C) is written to the frame memory 2 is the image data of the pixel read out at the 0th position after the display frame timing signal is given. With the addresses of the 8th to 11th bytes of the 16 bytes, the address that the graphics controller 1c outputs when writing the 0th line 3a pixel (the leftmost pixel of the area D) to the frame memory 2 is: After the display frame timing signal is given, the address is the address of the twelfth to fifteenth bytes of the 16 bytes of image data of the pixel to be read at the 0th.

When the display frame timing signal is supplied, the frame memory 2 into which the image data is written starts from the 0th to the 3rd bytes of the 16-byte output of the frame memory 2 and starts from the area A. , The pixel data of the area E, and from the fourth to seventh bytes, the pixel data of the area B, and then the pixel data of the area F,
From the eighth to eleventh bytes, the pixel data of the first area C and subsequently the area G, and from the twelfth to fifteenth bytes, the pixel data of the first area D and subsequently the area H,
The data is sequentially read out for each line in each area, and the data buffers 11c to 14c, 11d to 14d, and 15c to
18c and 15d to 18d.

When data is written into the memory 21c, the data buffer 11c is turned on by a write timing pulse (not shown) generated by the write pulse generator 4d.
When the image data of 4 bytes of the 0th to 3rd bytes in the area A is passed, and when the memory 21c is read, no image data is output. Therefore, memory 2
Image data of the area A is written in 1c.

The data buffer 12c is provided in the memory 2
When 2c is written, the write pulse generator 4d
Area B by the write timing pulse generated by
When the memory 22c is read out, it does not output any image data. Therefore, the image data of the area B is written in the memory 22c.

Further, when data is written in the memory 23c, the data buffer 13c
By the write timing pulse generated by d, the image data of 4 bytes from the 8th to 11th bytes in the area C is passed, and when the memory 23c is read,
Does not output any image data. Therefore, the memory 23c
Is written with the image data of the area C.

Further, when data is written into the memory 24c, the data buffer 14c
By the write timing pulse generated by d, the image data of 4 bytes of the twelfth to fifteenth bytes of the area D is passed, and when the memory 24c is read, no image data is output. Therefore, memory 2
Image data of the area D is written in 4c.

The same applies to the data buffers 11d to 14d. The memory 21d has an area E, the memory 22d has an area F, the memory 23d has an area G, and the memory 24d has an area H.
Are written respectively.

Further, the data buffers 15c to 18c,
The same applies to 15d to 18d.
To 28c, 25d to 28d, the areas A, B,
Image data of C, D, E, F, G, H is written.

The write address generator 3d converts the 16-byte image data read from the frame memory 2 into the memories 21c to 24c and 21d to 2 by 4 bytes.
4d, 25c to 28c, and memories 21c to 24c, 21d to 24d, and 2 when writing to any of 25d to 28d.
A write address to be supplied to any of 5c to 28c and 25d to 28d is generated.

The write pulse generator 4d converts the 16-byte image data read from the frame memory 2 into
Memory 21c to 24c, 21d to 24d, 25c to 28
c, when writing 4 bytes to any of 25d to 28d, the write addresses generated by the write address generator 3d are stored in the memories 21c to 24c, 21d to 24d,
In accordance with the timing given to any of 25c to 28c and 25d to 28d, write timing pulses are supplied to four memories to which image data is to be written.

For example, write timing pulses are applied to the memories 21c to 24c or the memories 25c to 28c so that the image data of the areas A, B, C, and D which are read first from the frame memory 2 are written to the memories 21c to 24c or the memories 25c to 28c. 24c or memories 25c to 28c,
After the writing of the image data in the areas A, B, C, and D is completed, the areas E,
F, G, and H image data are stored in the memories 21d to 2d, respectively.
4d or written in the memory 25d-28d,
A write timing pulse is applied to the memories 21d to 24d or the memories 25d to 28d.

When one set of memories 21c to 24c, 21d to 24d or one set of memories 25c to 28c, 25d to 28d is in a read state, the read address generator 5c reads the set of memories 21c to 21d. 24c, 21
Read addresses that are given simultaneously and equally to d-24d or 25c-28c, 25d-28d are generated.

The address selector 6 selects one of the write address generated by the write address generator 3d or the read address generated by the read address generator 5c, and selects one of the memories 21c to 24c, 21d to 21c.
Give 24d. Similarly, the address selector 7 selects one of the write address generated by the write address generator 3d and the read address generated by the read address generator 5c, and selects one of the memories 25c to 25c.
8c, 25d to 28d.

The data for four pixels is read out from the frame memory 2 at a time, and the memories 21c to 21c are read by one set of four memories.
24c, 21d to 24d, and each memory 21c to
Since a total of eight pixels are read at a time one pixel at a time from 24c, 21d to 24d, the memories 21c to 24c, 21d to 24d are used to match the writing and reading times.
It is necessary that the frequency of the clock used for the write operation is twice the frequency of the clock used for the read operation of these memories 21c to 24c and 21d to 24d. The same applies to the memories 25c to 28c and 25d to 28d.

The image data of the area A output from the 0th to the 3rd bytes of the 16 bytes read from the frame memory 2 is written into the memory 21c, and the 16 bytes read from the frame memory 2 are written into the memory 22c. The image data of the area B output from the fourth to seventh bytes among the bytes is written.

The memory 23c stores the eighth to the first of the 16 bytes read from the frame memory 2.
The image data of the area C output from one byte is written, and the image data of the area D output from the twelfth to fifteenth bytes of the 16 bytes read from the frame memory 2 is written into the memory 24c.

Similarly, the image data of the area E is written into the memory 21d, the area F is written into the memory 22d, the area G is written into the memory 23d, and the area H is written into the memory 24d.

As described above, the image data for one frame is read from the frame memory 2 and the areas A, B, C, D, E, F,
The image data of each area of G and H is stored in the memory 21c, respectively.
-24c, 21d-24d, the next frame of image data read from the frame memory 2 is written to the memories 25c-28c, 25d-28d.

Similarly to the memories 21c to 24c and 21d to 24d, the memory 25c has the area A, the memory 26c has the area B, the memory 27c has the area C, the memory 28c has the area D, the memory 25d has the area E, The area F is in the memory 26d, the area G is in the memory 27d, and the area H is in the memory 28d.
Are written respectively.

While writing image data to the memories 25c to 28c and 25d to 28d, the memories 21c to 24c
c, 21d to 24d read out the image data of each area of the immediately preceding frame which has already been accumulated, each having a 4-byte width. The order of reading is the order of writing to each memory. The reading of these memories 21c to 24c and 21d to 24d is performed simultaneously for eight times.

From the memories 21c to 24c and 21d to 24d, areas A, B, C, D, E, F,
The reading of the image data of G and H is completed, and the areas A, B, C, and C for the next one frame read from the frame memory 2 are stored in the memories 25c to 28c and 25d to 28d.
When the writing of the image data of D, E, F, G, and H is completed, the image data of one frame read next from the frame memory 2 is stored in the memories 21c to 24c and 21d to 2d.
4d while the memories 25c to 28c, 2
Image data already stored is read from 5d to 28d.

Thereafter, the image data read from the frame memory 2 is stored in the memories 21c to 24c for each frame.
c, 21d to 24d, and memories 25c to 2
8c, 25d to 28d are alternately written to one of the sets, and during that time, the operation of reading image data from the other set is repeated.

The data selector 31c selects one pixel of the area A being read from the memory 21c or the memory 25c and 4 bytes of image data and outputs the same to the driver 41c. Similarly, the data selector 32c is connected to the memory 2
2c or 1 of the area B read from the memory 26c.
The driver 42 selects image data of 4 bytes for pixels.
c, the data selector 33c selects one pixel and 4 bytes of image data of the area C read from the memory 23c or the memory 27c and outputs the 4-byte image data to the driver 43c. Alternatively, one pixel of the area D read from the memory 28c,
Byte image data is selected and output to the driver 44c.

Similarly, data selectors 35c, 36
Each of c, 37c, and 38c selects image data of 4 bytes corresponding to one pixel of the areas E, F, G, and H, and outputs the data to the drivers 45c, 46c, 47c, and 48c, respectively.

The driver 41c includes a data selector 31c
The image data of 4 bytes corresponding to one pixel in the area A output from is converted into a display image signal and output to the display 51. Similarly, the drivers 42c, 43c, 44c, 45c, 4
6c, 47c, 48c are areas B, C, D,
The image data of 4 bytes for one pixel of E, F, G, and H is converted into a display image signal, and the display units 52, 53, and 5, respectively.
4, 55, 56, 57 and 58.

The displays 51 to 58 are respectively provided with the driver 4
Areas A, B, C, D, E, output from 1c to 48c
The display image signals of F, G, and H are captured and displayed.

In the above example, the processing is performed for each frame of image data. However, when an interlaced scan frame signal is used, the processing may be performed for each field of image data.

In the above example, the display units 51 to 58 are separate display units. However, one display unit and a display image corresponding to each display portion of the display units 51 to 58 are provided. The signals may be input from the drivers 41c to 48c, respectively.

Furthermore, in the above example, eight memories 21
c to 24c, 21d to 24d (or memory 25c to 28
c, 25d to 28d), and 4 in the vertical direction of the display image.
By dividing an image of one frame into two in the horizontal direction of the display image, the areas A, B, C, D,
Although an example in which the image is divided into E, F, G, and H by eight is shown, one frame image divided into four in the vertical direction of the display image is provided with a plurality of memories of eight or more. It is also possible to divide into regions. In this case, the clock frequency used when writing image data to a plurality of memories is
This is obtained by multiplying the clock frequency used when reading image data from a plurality of memories by the number of regions divided in the horizontal direction of the display image.

Further, in the above example, the image data read from frame 2 is stored in two sets of memories 21c to 24c,
When data is stored in one of the storages 21d to 24d or 25c to 28c or 25d to 28d, reading is performed from the other when writing is performed on one of the storages.
As in the third embodiment, a two-port memory may be used.

Further, in the above example, four pixels have already been set in the vertical direction.
Although the example of dividing one frame of image divided into two in the horizontal direction has been described, the configuration of the memory read from the frame memory 2 for writing, the writing method, and the reading method correspond to each other. An image of one frame that has already been divided into a plurality in the vertical direction can be divided into a plurality in the horizontal direction.

As described above, according to the fourth embodiment, in order to store the image data read from the frame memory 2, 16 memories 21c to 24c, 21d to 21 can simultaneously input and output 4 bytes. 24d, 25c-28
c, 25d to 28d, and stores the image data read from the frame memory 2 into eight memories 2 for each frame.
1c to 24c, 21d to 24d or 25c to 28c, 2
Divided into 5d to 28d and stored, and a set of eight memories 2
While one frame of image data is being written to 1c to 24c and 21d to 24d, another set of eight memories 25c to 28c and 25d to 28d store the already stored one frame of image data. Are read in eight parallel, so that the image data for one frame read from the frame memory 2 and divided into four parts is stored in the areas A, B, C, D, E, F, G, and H. The effect that the image data can be divided and displayed for each of the eight areas is obtained.

[0174]

As described above, according to the present invention, a plurality of memories for dividing one frame of image data read from a frame memory into a plurality of regions and writing the divided image data for each region, A write address generator that generates a write address when writing image data to the memory, and a write timing pulse generated in accordance with the timing of the write address generated by the write address generator to write image data for each area. A write pulse generator for sequentially outputting to a memory to be read, and a read address generator for generating a read address when reading image data written to a plurality of memories, based on a read address generated by the read address generator. Image data for each area written to multiple memories Reading, by displaying in a plurality of regions, read out from the frame memory 1
An effect is obtained that image data for a frame can be divided and displayed for each of a plurality of areas.

According to the present invention, the clock frequency used when writing image data to a plurality of memories is obtained by multiplying the clock frequency used when reading image data from a plurality of memories by the number of divided areas. By doing so, there is an effect that the writing and reading times of a plurality of memories can be matched.

According to the present invention, one frame of image data read from the frame memory is divided into a plurality of areas, and a plurality of memories are written for each area. A write address generator that generates a write address; and a write that generates a write timing pulse in accordance with the timing of the write address generated by the write address generator and sequentially outputs the write timing pulse to a memory in which image data for each area is written. A pulse generator; and a read address generator for generating a read address when reading image data written to the plurality of memories. The read address is written to the plurality of memories based on the read address generated by the read address generator. Image data for each area, By dividing the image data into regions and displaying the image data, the image data for one frame, which is read out from the frame memory and divided into a plurality of frames in the vertical direction, is divided in the horizontal direction and divided into image data for each of a plurality of regions. There is an effect that can be displayed.

According to the present invention, the clock frequency used when writing image data to the plurality of memories is divided into the clock frequency used when reading image data from the plurality of memories by dividing the display image in the horizontal direction. By multiplying the numbers, there is an effect that writing and reading times of a plurality of memories can be matched.

According to the present invention, two sets of a plurality of memories for storing one frame of image data for each area are provided, while one frame of the image data is written to one set of the plurality of memories. By reading out the already written one-frame image data from the set of a plurality of memories, the one-frame image data can be efficiently divided into a plurality of regions and displayed. This has the effect.

According to the present invention, one frame of image data read from the frame memory is divided into a plurality of areas, and the plurality of two-port memories are written in each area. Address generator for generating a write address when writing data, and a two-port port for generating a write timing pulse in accordance with the timing of the write address generated by the write address generator to write image data for each area A write pulse generator that sequentially outputs to the memory and the image data for each area written to the plurality of memories are simultaneously read and divided into a plurality of areas to be displayed, so that the vertical direction read from the frame memory is displayed. The image data for one frame which is divided into a plurality The image data output from the frame memory can be reduced while the capacity of the two-port memory for storing the image data output from the frame memory can be reduced while the image data output from the frame memory can be reduced. This has the effect of reducing the input data width of the port memory and facilitating writing and reading control of the two-port memory.

According to the present invention, a plurality of 2
The clock frequency used when writing to the port memory is obtained by multiplying the clock frequency used when reading image data from a plurality of two-port memories by the number of divisions of the display image in the horizontal direction. There is an effect that the writing and reading times of the two-port memory can be matched.

According to the present invention, 1
By making the period for reading image data for one frame and the period for reading image data for one frame from a plurality of two-port memories the same, the image data for one frame read from the frame memory can be efficiently stored in a plurality. There is an effect that image data can be divided and displayed for each area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an image display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a display image dividing method according to the first embodiment of the present invention.

FIG. 3 is a diagram showing addresses of a frame memory generated by a graphics controller according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration of an image display device according to a second embodiment of the present invention.

FIG. 5 is a diagram showing addresses of a frame memory generated by a graphics controller according to a second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of an image display device according to a third embodiment of the present invention.

FIG. 7 is a timing chart showing a read operation of a frame memory according to Embodiment 3 of the present invention;

FIG. 8 is a timing chart showing a read operation of a two-port memory according to a third embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of an image display device according to a fourth embodiment of the present invention.

FIG. 10 is a diagram showing a display image dividing method according to a fourth embodiment of the present invention.

FIG. 11 is a diagram showing addresses of a frame memory generated by a graphics controller according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a conventional image display device.

FIG. 13 is a block diagram illustrating a configuration of a conventional image display device.

[Explanation of symbols]

1a, 1b, 1c graphics controller, 2
Frame memory, 3a, 3b, 3c, 3d Write address generator, 4a, 4b, 4c, 4d Write pulse generator, 5a, 5b, 5c Read address generator, 6, 7 Address selector, 11a to 18a, 11
b to 18b, 11c to 18c, 11d to 18d Data buffers, 21a to 28a, 21b to 28b, 21c to
28c, 21d to 28d memory, 31a to 34a, 3
1b-34b, 31c-38c Data selector, 41
a-44a, 41b-44b, 41c-48c Driver, 51-58 Display.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04N 5/66 H04N 5/66 B G09G 5/00 555K F term (Reference) 5B069 CA13 LA12 5C058 AA00 BA21 BB10 BB13 BB17 BB25 5C082 AA01 AA34 BA12 BB15 BB26 CA62 DA54 DA55 DA57 EA18

Claims (8)

[Claims] 1. An image display device for reading image data of one frame written in a frame memory and displaying the image by dividing the image data into a plurality of areas, wherein the image data of one frame read from the frame memory is provided. A plurality of memories that divide data into the plurality of regions and write the data for each region; a write address generator that generates a write address when writing image data to the plurality of memories; and a write address generator that is generated by the write address generator. A write pulse generator that generates a write timing pulse in accordance with a write address timing and sequentially outputs the write timing pulse to a memory in which image data for each area is written; A read address generator for generating a read address of Based on the issued read address generated by the address generator, reads the image data of each area which has been written to the plurality of memories at the same time, the image display apparatus and displaying in a plurality of regions. 2. A clock frequency used when writing image data to a plurality of memories is obtained by multiplying a clock frequency used when reading image data from the plurality of memories by the number of divided areas. The image display device according to claim 1, wherein: 3. The image data for one frame, which is written in a frame memory and is divided into a plurality of pieces in a vertical direction of a display image, is read out, and divided into a plurality of areas by dividing the display image in a horizontal direction. An image display device for displaying an image by dividing the image data of one frame read from the frame memory into the plurality of regions and writing the divided image data for each region; A write address generator for generating a write address when writing data, and a memory for generating a write timing pulse in accordance with the timing of the write address generated by the write address generator to write image data for each area A write pulse generator for sequentially outputting the image data to the plurality of memories. A read address generator that generates a read address when reading the image data.Based on the read address generated by the read address generator, image data for each area written to the plurality of memories is simultaneously read, An image display device, wherein the image is divided into a plurality of areas and displayed. 4. A clock frequency used when writing image data to a plurality of memories is obtained by multiplying a clock frequency used when reading image data from the plurality of memories by the number of divisions of a display image in a horizontal direction. The image display device according to claim 3, wherein 5. Two sets of a plurality of memories for storing one frame of image data for each area, and while writing one frame of image data into one set of a plurality of memories, another set of a plurality of memories is stored. 4. The image display device according to claim 1, wherein one frame of already written image data is read from a plurality of memories. 6. A method of reading one frame of image data, which is written into a frame memory and divided into a plurality of display images in a vertical direction, and divides the display image into a plurality of regions by dividing the display image in a horizontal direction. A plurality of two-port memories for dividing one frame of image data read from the frame memory into the plurality of regions and writing the divided image data for each region; A write address generator for generating a write address when writing image data to the memory; and a write timing pulse generated in accordance with the timing of the write address generated by the write address generator. A write pulse generator for sequentially outputting to a two-port memory into which a plurality of memos are written; Reads the image data for each area being written to at the same time, the image display apparatus and displaying in a plurality of regions. 7. A clock frequency used when writing image data to a plurality of two-port memories,
7. The image display device according to claim 6, wherein a clock frequency used for reading image data from the port memory is multiplied by a division number of a display image divided in a horizontal direction. 8. A cycle for reading one frame of image data from a frame memory, and a cycle for reading one frame from a plurality of two-port memories.
7. The image display device according to claim 6, wherein a cycle of reading image data of a frame is the same.