JPH0564117A - Signal processing circuit for liquid crystal projection type video display device - Google Patents

Abstract

PURPOSE:To reduce the operating frequency and to facilitate the shading correction in the unit of blocks divided optionally horizontally and vertically by applying shading correction independently respectively of each layer output of a multi-layer expansion processing section. CONSTITUTION:The signal processing circuit is provided with a multilayer expansion processing section 6 receiving a digital video signal to apply multi- layer expansion to N layers (N:2,3,...) and to obtain an output whose operating frequency is set to 1/N and a correction means multiplying shading correction information outputted from an address of a correction memory 83 selected by each address selectors 84A-84F based on a timing signal and latched by latches 82A-82F with each output obtained from the multi-layer expansion processing section 6 at multipliers 81A-81F to implement independently of shading correction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for driving a liquid crystal panel included in a liquid crystal projection type image display device.

[0002]

2. Description of the Related Art A signal processing circuit of a liquid crystal projection type image display device is required to operate at high speed because the frequency band of the image signal is wide (especially for high definition). However, since the operating speed of the liquid crystal driving integrated circuit is slow, it is necessary to process the video signal in multiple layers to lower the frequency per layer.
At this time, the liquid crystal is driven by, for example, a liquid crystal driving integrated circuit which is arranged in the lateral direction in an equal number of layers. Further, the signal processing circuit of the device has a correction circuit for optical unevenness (shading) caused by an optical system or the like.

Further, since a high-definition video signal band is about 30 MHz, which is a very wide band, in the method of cascading source driving integrated circuits (source drivers), the operating frequency of the shift register in the source driver is 30 MHz or more. It is necessary to have it. However, since there is currently no such high-speed source driver, in order to reduce the operating frequency of the source driver, a multi-layer expansion process for operating the source drivers in parallel is required.

Therefore, in a signal processing circuit of this type which has been conventionally known, as shown in FIG. 7, first, in a shading correction circuit 50, a video signal is subjected to shading correction by a timing signal created based on a synchronizing signal. After that, the multilayer expansion processing circuit 52 performs the multilayer expansion processing.

Here, the multi-layer expansion processing circuit 52 shown in FIG.
Then, as schematically shown in FIG. 8, the number of memories corresponding to the number of source drivers of the liquid crystal panel is three (in the figure, there are three for convenience of description), and the video signal of one line is divided and written. After that, reading is performed simultaneously in one line period. That is, one line of the video signal is divided into N parts, and the divided parts are simultaneously displayed in one line period to reduce the operating frequency to 1 / N.

[0006]

However, as shown in FIG. 7, since the shading correction of the video signal is conventionally performed before the multi-layer expansion processing, the operating frequency of the shading correction unit must be increased. There is a drawback. Further, it is difficult to perform shading correction for each block obtained by arbitrarily dividing the screen horizontally and vertically.

Moreover, such a conventional method has a drawback in that variations in the voltage for driving the liquid crystal of the liquid crystal driving integrated circuit of each layer cannot be corrected.

[0008]

In order to solve the above-mentioned problems, the present invention is constructed such that shading correction is independently applied to each layer output of the multilayer expansion processing means.

[0009]

In the present invention, the operating frequency can be lowered by performing independent shading correction for each layer output of the multi-layer expansion processing means.

[0010]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 1 is a block diagram showing an entire embodiment of the present invention. In the figure, 2 is an A / D converter for inputting an analog video signal, and 4 is an A / D converter from the A / D converter 2.
A sync signal processing unit 6 which performs sync signal processing on the D conversion output to output a digital video signal, and 6 is a multilayer expansion processing unit which will be described in detail later, and receives the digital video signal from the sync signal processing unit 4. Reference numeral 7 is a timing signal generator for generating a timing signal (details will be described later) based on the synchronization signal, and 8A.
8F is a shading correction unit that performs shading correction independently for each layer output 1 to 6 from the multilayer expansion processing unit 6, and divides each layer in the vertical direction based on the timing signal from the timing signal generation unit 7. Shading correction is performed for each divided portion. 12A to 12F are D / A converters for D / A converting the outputs from the shading correction units 8A to 8F, and 14A to 14F are D / A converters 1.
It is a liquid crystal drive unit for inputting each analog output from 2A to 12F.

As shown in FIG. 2, each shading correction unit has a multiplier, a latch, a correction memory (shared by each layer), and an address select. Reference numerals 81A to 81F denote multipliers to which the respective outputs from the multi-layer expansion processing unit 6 are input, and 83 is one correction memory including, for example, a ROM (read-only memory), and shading for each output from the multi-layer expansion processing unit 6. The correction information is stored, for example, the shading correction information having a value of “2” at every 0.001 to 0.001 is stored. 84A to 84F are address selects, which are based on the timing signal from the timing signal generation unit 7 for each timing signal from the addresses of the plurality of shading correction information "0" to "2" with respect to the correction memory 83. A signal for selecting an address corresponding to the shading correction value required for is output. 82A
.About.82F are latches for sharing one correction memory 83 in each layer and correspond to each multiplier 81A to 81F and each address select 84A to 84F, and the correction memory 8
The address select 3 latches the shading correction information from the selected address.

Each address select outputs a signal for selecting the address of the shading correction information required for each input of the timing signal based on the timing signal, and in response thereto, the shading correction information extracted from the correction memory 83. Is latched in each latch. In each latch, for example, by holding the shading correction information for each scanning line, the shading correction can be easily performed by the number of blocks (the number of multi-layer expansions) × (the number of arbitrary horizontal scanning lines). Since the correction is performed on a block-by-block basis, a slight positional deviation of the correction information due to the latch timing can be ignored. Since the correction memory 83 is shared by each layer, the circuit scale can be reduced.

FIG. 3 shows a detailed circuit configuration of the multilayer expansion processing section 6 shown in FIG. FIG. 4 is a timing chart showing the operation of FIG.

Next, with reference to FIGS. 3 and 4, a specific operation procedure for performing the 6-layer expansion will be described.

(1) First, a digital video signal is converted into six F
Input to IFO (First In First Out) memory.

(2) A write reset signal for resetting the internal pointer is input for writing to each FIFO memory.

(3) The write enable signals 1 to 6 for designating the writing period are input to each FIFO memory.

Here, since each write enable signal divides the video period in 1H (horizontal scanning) of the video signal into six equal parts, they are sequentially supplied for (video period) / 6 periods.

(4) Input a read reset signal for resetting internal pointers for simultaneously reading data from all the FIFO memories after a fixed period.

(5) In synchronization with the read clock (frequency of 1/6 of the write clock), the written data is simultaneously read from all the FIFO memories in 1H time of the liquid crystal panel.

FIG. 5 shows progressive scanning (non-interlace)
It is a block diagram showing a multilayer expansion processing unit 6 having a conversion function. In the figure, 21 is a line memory for inputting digital video signals, 22 is an adder for line interpolation, and 23-2.
6 is a D-type flip-flop (FF), A0 to F0, A1
~ F1, A00 to F00, A11 to F11 (A to F represent each layer, and 0000 is read in the first half of 1H, 1,1
1 indicates that the data is read in the latter half of 1H) is a FIFO (first-in first-out) memory, and 27 to 38 are D-type flip-flops (FF). The outputs of the D-type FFs 27 to 38 are input to the individual shading correction units.

Next, the operation of FIG. 5 will be described with reference to the timing chart of FIG. 6 (A to F and 0 in FIG. 6,
1 corresponds to A to F and 0 (00), 1 (11) in FIG. 5, and the frequency of the write clock is 1/2 of the frequency f of the operation clock of the line memory 21).

(1) Each FIFO memory resets the write address pointer to 0 at the rising edge of the write clock when the write reset pulse is "L".

(2) When each write enable of A to F, which is sequentially shifted for every H / 6, is "L", the corresponding FIFO memory (A0 to F0, A1 to F1) is set to the FIFO memory (at the rising edge of the write clock). A00-F00, A11-F1
1) is the fall of the write clock and each of the D-type FFs 23 to 26
The data on the input side of the line memory 21 and the output side of the adder 22 are written as 0 (1) or 00 (11 ) Attached F
Divided into IFO memory). At this time, the value of the write address pointer is incremented by 1.

(3) When the read reset pulse is "L", all the FIFO memories reset the read address pointer to 0 at the rising edge of the read clock.

(4) When the read enable indicated by 0 or 1 is "L", the value of the read address pointer of the corresponding FIFO memory at the rising edge of the read clock (the frequency of the read clock is 1/6 of the frequency of the write clock). The data is read from each address via the D-type FFs 27 to 38. At this time, the value of the read address pointer is incremented by 1. Here, the output of the corresponding FIFO memory when the read enable is "H" becomes high impedance,
It is separated from the data bus.

In this way, the data is written in each FIFO memory for the H / 6 period, and the FIFO corresponding to the next 1H period is written.
By simultaneously reading data from the memory for each H / 2 period, it is possible to perform 6-time time extension and non-interlace conversion at the same time.

[0029]

As described above, according to the present invention,
Since the shading correction is independently applied to each layer output of the multi-layer expansion processing means, the operating frequency can be lowered, and the shading correction can be easily performed in units of blocks horizontally and vertically arbitrarily divided. it can. Furthermore, it becomes easy to create shading correction information in the correction memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an entire embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a shading correction unit shown in FIG.

3 is a block diagram showing a configuration of a multi-layer expansion processing unit shown in FIG.

FIG. 4 is a timing diagram illustrating the operation of FIG.

5 is a diagram showing another configuration (with a progressive scan conversion function) of the multilayer expansion processing unit shown in FIG.

FIG. 6 is a timing diagram showing the operation of FIG.

FIG. 7 is an explanatory diagram of a conventional technique.

FIG. 8 is an explanatory diagram of a conventional technique.

[Explanation of symbols]

2 A / D converter 4 Sync signal processor 6 Multi-layer expansion processor 7 Timing signal generator 8A-8F Shading corrector 12A-12F D / A converter 14A-14F Liquid crystal driver A0-F0, A00-F00, A1 ~ F1, A11 ~ F
11 FIFO memory 81A to 81F Multiplier 82A to 82F Latch 83 Correction memory 84A to 84F Address select

Claims (1)

[Claims] 1. A signal processing circuit for driving a liquid crystal panel included in a liquid crystal projection type image display device, wherein a digital image signal is input and a multilayer expansion is performed on N layers (N = 2, 3, ...). A multi-layer expansion means for obtaining an output having an operating frequency of 1 / N, a correction memory storing a plurality of shading correction information, and a plurality of shading correction information for the correction memory based on a timing signal. A plurality of address selects for outputting a signal for selecting a corresponding address for each output obtained from the multi-layer expansion means from an address; and shading correction information of the address selected by the address select extracted from the correction memory. , A plurality of multipliers for multiplying each output obtained from the multi-layer expansion means. Signal processing circuit for photo-visual display device.