JP2624119B2 - Manufacturing method of composite semiconductor laminated structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a group IV or III-
The present invention relates to a method for manufacturing a composite semiconductor multilayer structure having a high quality group III-V compound semiconductor single crystal layer on a group V lattice mismatched substrate.

[0002]

2. Description of the Related Art At present, heteroepitaxial growth on a group IV or III-V lattice mismatched substrate, especially Si
GaAs or I on a group IV semiconductor single crystal substrate represented by
Attempts to form a group III-V compound semiconductor single crystal thin film represented by nP have been actively made. This is because if such a thin film structure can be formed, a group III-V compound semiconductor high-performance device can be manufactured on an inexpensive Si substrate,
This is because the performance improvement of the optical element and the like can be expected due to the high thermal conductivity. Further, because a Si ultra-high-integrated circuit and a III-V compound semiconductor ultra-high-speed device or an optical device can be formed on the same substrate, the development of a new high-performance device is expected.

By the way, III-V formed on a Si substrate
In order to apply a group III compound semiconductor thin film to element fabrication, it is important to improve crystal quality. For example, the magazine "Japanese
Journal of Applied Physics (Jpn.
J. Appl. Phys. ) "Vol. 24, No. 6 (198
Using the “two-stage growth” described on page L391-393 in (5 years), a single-domain single-crystal thin film in which the phases of the group III and group V are aligned in the entire substrate plane can be reliably obtained. In addition, the crystallinity is improved as compared with the conventional direct growth. This is a method in which a thin polycrystalline or amorphous buffer layer is first deposited at a low temperature, and then a single-crystal thin film is grown at a normal growth temperature. I do. However, when, for example, GaAs is grown on a Si substrate, much more dislocations and stacking faults occur at the Si / GaAs interface than expected from the lattice mismatch rate, and a part of the dislocations and the stacking layer easily reach the upper layer. It extends and becomes threading dislocation. The dislocation density of the case of two-stage growth method is about 10 ⁸ cm several μm thick growth surface ^- as high as ^2.

[0004] Therefore, in the introduced the distortion super lattice intermediate layer and the thermal cycle annealing, about 10 ⁶ cm by these
^The dislocation density was rapidly improved to -2 (see Applied Physics Letter, Appl. Phys.
t. Vol. 54 No. 1 (1989) 24-26
page). However about 10 ⁶ cm ^{- 2} The below results not easily obtained, Si substrate and the III-V as its cause
The problem of the difference in the coefficient of thermal expansion from the group III compound semiconductor was pointed out (see Applied Physics Letter (Appl.
Phys. Lett. Vol. 56, No. 22 (1990)
Pp. 2225-2227). That 10 ⁵ cm in the growth temperature (650 ° C.), such as by introduction of thermal cycle annealing ^- the dislocation density to ² or less is reduced but,
10 ⁶ by stress due to thermal expansion coefficient difference in cooling (about 450 ° C. or less) after growth cm ^- is that the ^two dislocations are introduced. It is considered that this is because a large number of dislocations remaining near the interface with the Si substrate rise due to thermal strain.

[0005] The above problem is that the lattice constant difference from Si is 8
% And is more pronounced in InP growth on large Si, the dislocation density is still about 10 ⁷ cm ^{- 2} and high (magazine "Journal of Crystal Growth (J.Crystal
Growth), Vol. 99 (1990), 365
-370 pages). Further, if the residual thermal strain is large, even when a high-density current is injected into the manufactured light-emitting device, the growth of defects is caused and the life is remarkably reduced.

On the other hand, as another method of laminating materials having different lattice constants or the like, there is a method of directly bonding different kinds of substrates, and the direct bonding method of Si substrates has been actively studied. As for III-V group compound semiconductors, it has recently been reported that GaAs and InP are directly bonded by heat treatment to produce an InP-based semiconductor laser on a GaAs substrate (Applied Physics Letter (Appl. Phys. Lett.), Vol. 58, No. 18, (1991), Nos. 1961-1963.
page). In this case, dislocations due to lattice mismatch between GaAs and InP are generated at the junction interface. However, since the direction of the Burgers vector is an edge dislocation parallel to the interface, the dislocation is confined only to the interface and penetrates the upper and lower crystal layers. I won't.

Further, an example of a method for producing a substrate by bonding and integrating Si and a compound semiconductor substrate is disclosed in Japanese Patent Laid-Open No. 61-182.
215, JP-A-61-183915 and JP-A-2-194519.

[0008]

SUMMARY OF THE INVENTION The group IV or III
Consider the problems of the above-mentioned prior art employed for obtaining a high-quality III-V compound semiconductor single crystal layer on a -V lattice mismatched substrate.

As described above, in the method of directly heteroepitaxially growing a group III-V compound semiconductor single crystal layer on a group IV or group III-V lattice mismatched substrate, the dislocation density is still high and the difference in thermal expansion coefficient is particularly large. There is a problem in that the growth on large Si has a large residual thermal strain.

On the other hand, in the method in which dissimilar substrates are directly bonded to each other, dislocations due to lattice mismatch are confined only at the bonding interface, so that there is no problem in crystal quality in principle.

In the prior art in which GaAs and InP are directly bonded by heat treatment, a heat treatment at 650 ° C. for 30 minutes and a relatively long time is required.
Very recently, it has also been reported that direct bonding can be performed even at a relatively low temperature of about 450 ° C. (“Technical Report of the Institute of Electronics, Information and Communication Engineers” OQE92-147 (1992)).
In order to keep the electric resistance at the interface low enough,
High temperatures of ° C were required.

Further, Si and III such as GaAs and InP
In order to adhere to the -V crystal, a high temperature of about 1000 ° C. or more is required for good adhesion in which interfacial voids have disappeared in the bonding between Si.
It is expected that a higher temperature heat treatment will be required than the bonding of.

When an Si integrated circuit and a group III-V compound semiconductor device are to be formed on the same substrate, a process temperature of 40 after an Si integrated circuit pattern is already completed.
It is necessary to form a group III-V compound semiconductor layer at 0 ° C. or lower. This is because it is impossible to form a group III-V compound semiconductor layer which becomes a conductive impurity for Si and easily diffuses with each other before the Si high temperature process at 800 ° C. or higher. In addition, in order to utilize the existing established Si process as it is, it is generally desirable to form a group III-V compound semiconductor layer after completing about three layers of Al multilayer wiring. In this case, the melting point of Al and A
Considering the reaction between l and Si, I
It is necessary to form a II-V compound semiconductor layer. Therefore, the conventional direct heteroepitaxial growth at a high temperature and the direct bonding method at a high temperature cannot be applied because it leads to destruction of the Si integrated circuit.

Further, when the heat treatment temperature is high, a large difference in thermal expansion coefficient causes a large thermal strain during cooling, and furthermore, a defect may be generated or multiplied.

It is an object of the present invention to overcome the drawbacks of the prior art and reduce the temperature required for the process to provide a high quality group III-V compound on a group IV or III-V lattice mismatched substrate. An object of the present invention is to provide a method for manufacturing a composite semiconductor multilayer structure having a semiconductor single crystal layer.

[0016]

According to the first aspect of the present invention, there is provided a semiconductor device, comprising: directly on a first semiconductor substrate;
-First InSb contact with a group V compound semiconductor layer interposed
The step of growing a semiconductor layer and directly on the second semiconductor substrate.
Or the second group III-V compound semiconductor layer
Growing an InSb contact layer,
And via the second InSb contact layer the first,
For bonding the laminated structures on the second and second semiconductor substrates
Semiconductor having at least the following steps:
A method of manufacturing a laminated structure is obtained.

According to the invention of claim 5, the first semiconductor substrate
Directly on a plate or first III-V compound semiconductor
The first In-based III-V compound semiconductor layer is sandwiched between the layers.
Growing step, and the first In-based III-V compound
Group V element is thermally evaporated from the semiconductor layer to form the first In-based element.
Converting to a metal contact layer;
Product on the first semiconductor substrate via a metal contact layer
Direct compression bonding of the layer structure and the second semiconductor substrate, or
Formed a second laminated structure on the second semiconductor substrate
At least a step of crimping the two later.
As a result, a method of manufacturing a composite semiconductor multilayer structure can be obtained.
Also, a process for forming a second laminated structure on the second semiconductor substrate
Process directly on the second semiconductor substrate or a second
Second In-based II with a III-V compound semiconductor layer interposed
A step of growing an IV group compound semiconductor layer.
Features. Also, a second laminated structure on the second semiconductor substrate
Is formed directly on the second semiconductor substrate.
Or the second group III-V compound semiconductor layer
For growing In-based III-V compound semiconductor layer
And from the second In-based III-V compound semiconductor layer
Second In-based metal contact by thermally evaporating group V element
And converting to a layer.
You. In addition, the first or second In-based III-V group compound
It is characterized in that the conductor layer is an InP layer. Also first
Or keeping the second In-based metal contact layer above the melting point.
Or the first or second In-based metal contactor
Apply ultrasonic vibration to the layer or use these means together
The first or second In-based metal contact
While melting the shoulder, the laminated structure on the first semiconductor substrate, the second
The second product on the second semiconductor substrate or the second semiconductor substrate
It is characterized in that the layer structure is pressure-bonded.

According to the tenth aspect of the present invention , the first In-based III-V compound semiconductor contact layer is provided directly on the first semiconductor substrate or with the first III-V compound semiconductor layer interposed therebetween. A step of sequentially growing a group III-V compound semiconductor device layer, a step of bonding a support substrate on the group III-V compound semiconductor device layer, a first semiconductor substrate and a first group III-V compound semiconductor layer Removing the surface of the first In-based III-V compound semiconductor contact layer, and directly on the second semiconductor substrate,
Alternatively, the support substrate and the second In-based III-V compound semiconductor contact layer and the second In-based III-V compound semiconductor contact layer may be interposed with a second III-V compound semiconductor layer interposed therebetween. At least a step of pressure-bonding the laminated structures on the second semiconductor substrate to obtain a composite semiconductor laminated structure manufacturing method. Further, the step of bonding the support substrate may be performed by the method of the above III
-Third In-based III on Group V compound semiconductor device layer
Growing a -V group compound semiconductor contact layer and growing a fourth In-based III-V compound semiconductor contact layer directly on the support substrate or with a third III-V compound semiconductor layer interposed therebetween. And a step of pressure-bonding the stacked structures on the first semiconductor substrate and the support substrate via the third and fourth In-based III-V compound semiconductor contact layers. Features. Still further, the step of bonding the support substrate includes forming an organic adhesive material layer on at least one surface of the III-V compound semiconductor device layer and the support substrate, and via the organic adhesive material layer. It is characterized by comprising at least a step of crimping the laminated structure on the first semiconductor substrate and the supporting substrates.

As described above, according to the present invention, the first and second semiconductor substrates and the supporting substrate are each a III-V compound semiconductor substrate or a IV group semiconductor substrate. A method of manufacturing the structure is obtained.

Further, according to the fourteenth aspect of the present invention, a step of forming a group IV device layer on the first group IV semiconductor substrate, and a step of providing an opening partly exposing the surface of the group IV semiconductor crystal, Growing a first In-based group III-V compound semiconductor contact layer directly on the surface of the group IV semiconductor crystal exposed to the opening or with a first group III-V compound semiconductor buffer layer interposed therebetween; Forming a group III-V compound semiconductor device layer and a second In-based group III-V compound semiconductor contact layer directly on the second group IV semiconductor substrate or with a second group III-V compound semiconductor buffer layer interposed therebetween; Growing, forming a mesa by etching using an island-shaped mask pattern, and removing the first In-based III- Group compound semiconductor contact layer and the mesa second In-based Group III-V compound wherein the first through the semiconductor contact layer that remains on the top, and the second I
At least a step of pressure-bonding the stacked structures on the group V semiconductor substrate to obtain a composite semiconductor stacked structure manufacturing method.

As described above, according to the present invention, the In-based III-V
The group III compound semiconductor contact layer is an InP layer, an InAs layer,
One of InSb layers, characterized in that the stacked structures on the two semiconductor substrates are pressed together while being heated to 300 ° C. or higher. The In-based III-V compound semiconductor contact layer is an InSb layer, and the InSb layer is heated and melted at a melting point of 525 ° C. or higher for a short time.
irradiating light having a wavelength that can be absorbed only by the b-layer so as to press-bond the stacked structures on the two semiconductor substrates while heating and melting only the InSb layer at a melting point of 525 ° C. or higher. A method of manufacturing a laminated structure is obtained.

Alternatively, in the present invention, the In-based III-
After growing a group V compound semiconductor contact layer, or
A composite type comprising: converting an n-based III-V compound semiconductor contact layer into an In-based metal contact layer; and pressing the stacked structures on the two semiconductor substrates through the In-based metal contact layer. A method for manufacturing a semiconductor multilayer structure is obtained.

[0023]

[Function] As a mechanism of direct bonding, a hydrophilic surface is formed by a surface treatment with a sulfuric acid-based solution, and the surface is first weakly bonded by a hydrogen bond between OH groups adsorbed here.
Then, it is considered that a dehydration condensation reaction occurs in the process of performing the heat treatment, resulting in strong adhesion. Therefore, when a substrate having an atom having a weaker bond with oxygen as a constituent element is used, the dehydration condensation reaction occurs at a lower temperature, and the heat treatment temperature can be lowered. In other words, GaAs at about 600 ° C. can be used at a lower temperature of about 500 ° C. or less than Si which requires a high temperature of 850 ° C. or more for evaporation of the natural oxide film on the surface. In-based compounds such as InP, InAs, and InSb can be used. Using a semiconductor enables bonding at a lower temperature.

The surface flatness is important to obtain high adhesion without voids and good electrical characteristics. However, Si which requires a high temperature of 1000 ° C. or more for atom surface migration or 650 ° C. or more is required. Compared to GaAs
In an n-type compound semiconductor, mass transfer occurs even at 500 ° C. or less due to migration, so that some gaps at the interface are filled.

As described above, bonding at a lower temperature is possible with an In-based compound semiconductor. Therefore, even when other group IV or non-In group III-V compound semiconductors are bonded together, if a thin In-based compound semiconductor layer is formed in advance on the bonding surface, the bonding temperature can all be lowered.

Among In-based compound semiconductors, InSb
In the case of (2), since the melting point is 525 ° C., which is lower than the melting point of Al, which is 660 ° C., it can be instantaneously melted and bonded in a very short time such as flash annealing, and the influence on Al wiring and the like can be minimized. .

Further, the energy band gap of InSb is 0.18 eV, which is the smallest among the group IV and III-V compound semiconductors, and the lowest melting point. So I
By irradiating light of an appropriate wavelength absorbed only by nSb, I
It is also possible to heat and melt only nSb for bonding.
(The manufacturing method of the invention of claim 1).

In order to enable bonding at a lower temperature, a metal having a low melting point may be interposed at the interface. Above all, for example, metal In is ideal because it has a low elastic modulus and a very low melting point of about 157 ° C. Si and III with large thermal expansion coefficient difference
Even in the case of bonding with a Group V compound semiconductor, if the metal In is sandwiched, the liquid metal
There is an advantage that almost 100% of thermal strain can be absorbed by the intermediate layer.

The method for forming the metal In layer is as follows.
The In-based semiconductor layer can be converted to an In-based metal layer by desorbing the group V element from the based semiconductor crystal layer. InP and InA
In an In-based crystal such as s, it is utilized that the desorption of P and As from the surface occurs very easily. Above all, the desorption of P from the InP surface is based on the removal of As from a Ga-based crystal, for example, GaAs surface. Its desorption rate constant is two to three orders of magnitude greater than desorption. Thin InP formed on the surfaces of two materials to be joined
At least one of the layers is converted to a metal In layer, or only one of the two material surfaces to be joined has a thin I
After forming an nP layer and converting it to a metal In layer, it may be pressed while being heated to a melting point of 157 ° C. or higher of In or by applying ultrasonic vibration, and then press-bonded through the metal In layer (claims 5 and 6 ). Production method of the present invention).

When the surface of a thick epitaxial growth layer on a crystal substrate is used as the bonding surface, it is possible that sufficient surface flatness cannot be ensured due to generation of surface defects or deterioration of morphology. In such a case, a support substrate is first bonded to the front surface side of the epitaxial growth layer, and then a flat interface near the crystal substrate is exposed and used as a final bonding surface. The supporting substrate may be bonded by the manufacturing method of the present invention, or by using an organic adhesive substance that can withstand a heat treatment to be performed later, such as polyimide.

When the difference in thermal expansion coefficient is large, such as when laminating the laminated structures on the Si substrate and the InP substrate,
When high-temperature heat treatment is performed, warpage after cooling becomes a problem. Further, when it is desired to bond a specific position on the InP substrate to a specific position on the Si substrate so as to be bonded, the positional deviation during the heat treatment becomes a problem. In such a case as well, the use of the supporting substrate makes it possible to make the thermal expansion coefficient the same as that of the other substrate (the manufacturing method according to the tenth aspect of the present invention).

Considering the case where a group III-V compound semiconductor layer is formed by a bonding method on a part of a Si substrate on which a Si ultra-high integrated circuit has already been formed, the Si substrate is currently 6
８8 inch large-diameter substrates are standard, while In
For a P substrate or a GaAs substrate, the maximum is 3 to 4 inches.
Poor efficiency due to lack of consistent process. Therefore, III- heteroepitaxially grown on another large-diameter Si substrate
It is efficient if bonding is performed using a group V compound semiconductor layer. Although this method has a problem of reducing defects in the heteroepitaxial layer as a problem, the Si substrate used for growth can be removed after bonding with the Si ultra-high integrated circuit substrate side at a low temperature, and thermal strain generated by high-temperature growth can be reduced. It can be excluded (the manufacturing method of the invention of claim 10 ).

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIGS. 1 (a) to 1 (c) are cross-sectional views at each step showing a manufacturing process as an example of the first aspect of the present invention.

As shown in FIG. 1A, for example, first, a 0.5 μm thick GaAs buffer layer 2, 0.5 μm
A first In Sb contact layer 3 having a thickness of μm is grown. Further, a 0.5 μm thick InGaAs spacer layer 5, a 2 μm thick InP device layer 6, a 0.5 μm thick
A thick second In Sb contact layer 7 is grown. For growth, triethyl gallium (T
EG), triethylaluminum (TEA) and trimethylindium (TMIn), and as group V materials arsine (AsH ₃ ) and trimethylantimony (TMSb)
And a metal organic chemical vapor deposition method (MOCVD method) using phosphine (PH ₃ ).

Next, as shown in FIG. 1B, after performing a surface treatment with a sulfuric acid solution and HF, the Si substrate 1 and the I
The laminated structure on the nP substrate 4 is overlapped on the surfaces via the first In Sb contact layer 3 and the second In Sb contact layer 7, and a light weight is placed thereon and heat-treated at 500 ° C. for 30 minutes in hydrogen. Was. In this process, the laminated structures on both substrates were joined.

Finally, as shown in FIG. 1C, the InP substrate 4 and InGaAs are polished and selectively etched.
The s spacer layer 5 is removed to expose the surface of the InP device layer 6.

Photoluminescence (PL) measurement performed to examine the crystal quality of the obtained InP device layer showed that the emission intensity was comparable to that of the growth layer on the InP substrate.
It was also found that the shift in emission wavelength, that is, the thermal strain caused by the difference in thermal expansion coefficient between InP / Si was small. Also TEM
As a result of the observation, the dislocation density 10 ⁴ cm ^- it was found ^{that 2} very good crystal quality below is obtained.

(Embodiment 2) FIGS. 2 (a) to 2 (c) are cross-sectional views at each stage showing a manufacturing process as an example of the fifth aspect of the present invention.

As shown in FIG. 2A, for example, first, a 0.5 μm thick GaAs buffer layer 2, 0.5 μm
A first InP layer 21 having a thickness of μm is grown. Further GaAs
AlAs spacer layer 2 having a thickness of 0.5 μm on s substrate 22
A GaAs device layer 24 having a thickness of 3, 2 μm and a second InP layer 25 having a thickness of 0.5 μm are grown. For growth, arsine (AsH ₃ ) and phosphine (PH ₃ ) were used as group V materials.
Source molecular beam epitaxy using MB (MB
E method) was used.

Next, as shown in FIG. 2B, the first In is heated to an appropriate temperature of 600 ° C. or less and 450 ° C. or more.
P is desorbed from the P layer 21 and the second InP layer 25 and converted into a first metal In layer 26 and a second metal In layer 27.

Next, as shown in FIG.
At about 157 ° C. or higher, the laminated structure on the Si substrate 1 and the GaAs substrate 22 is formed by the first metal In layer 26 and the second metal I
Pressure bonding is performed via the n-layer 27. Finally, the GaAs substrate 22 and the AlAs spacer layer 23 are removed by polishing and selective etching to expose the surface of the GaAs device layer 24.

The crystal quality of the GaAs device layer obtained in this example was also found to be comparable to the growth layer on the GaAs substrate from PL measurement and TEM observation. Also metal I
It was found that in the present embodiment in which pressure bonding was performed via the n-layer, the strain was completely relaxed without a shift in the emission wavelength.

In Example 1, although a thermal strain remains, an extremely strong adhesive strength can be obtained because a covalent bond interface is formed. On the other hand, in the method of pressure bonding via the metal In layer of Example 2, although the adhesive strength is reduced, the distortion can be completely reduced.

(Embodiment 3) FIGS. 3 (a) to 3 (e) are cross-sectional views at each stage showing a manufacturing process as an example of the tenth aspect of the present invention.

As shown in FIG. 3A, for example, first, In
0.5 μm thick first InGaAs spacer layer 31, 0.5 μm thick first InP contact layer 3, 2 μm thick InP device layer 6, 0.5 μm thick second InGaAs spacer layer on P substrate 4 32, a third InP contact layer 33 having a thickness of 0.5 μm is grown. The gas source MBE method was used for growth. Further, a fourth InP contact layer 35 having a thickness of 0.5 μm is grown on the InP support substrate 34. Further, a second InP contact layer 7 having a thickness of 0.5 μm is grown on the GaAs substrate 22.

Next, as shown in FIG. 3B, after performing a surface treatment with a sulfuric acid-based solution and HF, the laminated structure on the InP substrate 4 and the InP support substrate 34 is changed to the third InP contact layer 33 and the fourth Are superimposed on each other via the InP contact layer 35 of FIG.
Heat treatment was performed at 00 ° C. for 30 minutes. In this process, the laminated structures on both substrates were joined.

Next, as shown in FIG. 3C, the InP substrate 4 and the first InG
The aAs spacer layer 31 is removed, and the lower surface of the first InP contact layer 3 is exposed.

Next, as shown in FIG. 3D, after performing a surface treatment with a sulfuric acid-based solution and HF, the laminated structure on the GaAs substrate 22 and the InP supporting substrate 34 is changed to the second InP.
The surfaces are superimposed on each other via the contact layer 7 and the first InP contact layer 3, and a light weight is placed on the surface in hydrogen,
Heat treatment was performed at 500 ° C. for 30 minutes. In this process, the laminated structures on both substrates were joined.

Finally, as shown in FIG. 3E, the InP supporting substrate 34 and the fourth I
nP contact layer 35, third InP contact layer 3
3. Remove the second InGaAs spacer layer 32 to remove In
The surface of the P device layer 6 is exposed.

In the present embodiment, on the surface of the uppermost layer of the multi-layer structure grown on the InP substrate 4 and the third InP contact layer 33, projections having a diameter of at most 1 to 2 μm due to crystal defects or attached dust are formed. Hundreds were distributed at a density of cm ^-2 .
Therefore, the InP substrate 4 and the InP supporting substrate 3 shown in FIG.
In the bonding of the laminated structures on No. 4, voids remained at the interface, and the bonding strength was weak. However, there is almost no protrusion on the lower surface of the first InP contact layer 3 exposed by polishing and selective etching in FIG. 3C, and the bonding strength is sufficiently strong without leaving voids at the interface in the subsequent bonding. was gotten.

Further, the crystal quality of the InP device layer obtained in this example was determined by PL measurement and TEM observation.
It turned out to be comparable to the growth layer on the substrate.

(Embodiment 4) FIGS. 4 (a) to 4 (e) are cross-sectional views showing a manufacturing process as another example of the tenth aspect of the present invention.

As shown in FIG. 4A, for example, first, In
0.5 μm thick first InGaAs spacer layer 31, 0.5 μm thick first InP contact layer 3, 2 μm thick InP device layer 6, 0.5 μm thick second InGaAs spacer layer on P substrate 4 32, a first InP layer 21 having a thickness of 0.5 μm is grown. Gas source MBE for growth
Method was used.

On the Si support substrate 41, a GaAs buffer layer 2 having a thickness of 0.5 μm and a second InP layer 25 having a thickness of 0.5 μm are grown.

Further, GaAs having a thickness of 2 μm is formed on the Si substrate 1.
The device layer 24 is grown with a second InP contact layer 7 having a thickness of 0.5 μm.

Next, as shown in FIG. 4B, the first In is heated to an appropriate temperature of 600 ° C. or less and 450 ° C. or more.
P is desorbed from the P layer 21 and the second InP layer 25 and converted into a first metal In layer 26 and a second metal In layer 27.

Next, as shown in FIG. 4C, the laminated structure on the InP substrate 4 and the Si support substrate 41 is melted at a melting point of In of about 157 ° C. or more by the first metal In layer 26 and the second metal I.
Pressure bonding is performed via the n-layer 27. Further, the InP substrate 4 and the first InGaAs are polished and selectively etched.
The spacer layer 31 is removed, and the first InP contact layer 3 is removed.
Expose the lower surface.

Next, as shown in FIG. 4D, after performing a surface treatment with a sulfuric acid-based solution and HF, the laminated structure on the Si substrate 1 and the Si support substrate 41 is changed to the second InP contact layer 7 and the second The surfaces are superimposed on each other via one InP contact layer 3 and a light weight is placed on the surface thereof in hydrogen at 500 ° C.
For 30 minutes. In this process, the laminated structures on both substrates were joined.

Finally, as shown in FIG. 4E, the Si support substrate 41, the GaAs buffer layer 2, the second metal In layer 27, the first metal In layer 26, and the second InGaAs spacer are polished and selectively etched. Layer 32 is removed and I
The surface of the nP device layer 6 is exposed.

The crystal quality of the InP device layer obtained in this example was found to be comparable to that of the growth layer on the InP substrate from PL measurement and TEM observation.

The Si support substrate 41 and In
When the bonding of the laminated structure on the P substrate 4 is performed by a high-temperature heat treatment as in the first embodiment, the substrates having a large difference in coefficient of thermal expansion are thick, and thus the substrate after cooling is inevitable. However, in this embodiment, since the substrate is bonded at a low temperature via the metal In layer, there is almost no warpage of the substrate, and there is no adverse effect on the next bonding step.

Further, the InP device layer 6 moved on the Si support substrate 41 in the first bonding step and the G
Even when a specific horizontal position of the aAs device layer 24 is desired to be aligned and bonded, for example, since both substrates are made of Si, there is no problem of displacement due to a difference in thermal expansion coefficient during heat treatment.

(Embodiment 5) FIGS. 5 (a) to 5 (d) are cross-sectional views at each stage showing a manufacturing process as an example of the invention of the fourteenth aspect .

As shown in FIG. 5A, for example, first, a Si device structure layer 52 having a maximum thickness of 3 μm including an Al multilayer wiring layer is formed on a first Si substrate 51, and a first layer is formed on a part thereof. An opening where the surface of the Si substrate 51 is exposed is provided. First, the first InSb contact layer 53 having a thickness of 0.5 μm is formed on the surface of the first Si substrate 51 exposed to the opening.
Grow. Gas source MB with added Sb source cell
After the growth using the E method, the InSb layer other than the surface portion of the first Si substrate 51 is removed.

Next, a GaAs buffer layer 2 having a thickness of 0.5 μm is grown on the second Si substrate 54, and a first GaAs device layer 55 having a thickness of 0.7 μm
It is grown while performing thermal cycle annealing at 50 ° C. about twice, and then the InGaAs / GaAs strained superlattice layer 56 (In
_{. 0 2 Ga 0 8 As:} . 10nm, GaAs: 20n
m, x10 periods), an AlAs spacer layer 23 having a thickness of 0.5 μm is grown, and a second GaAs layer having a thickness of, for example, 3 μm is further formed.
A device layer 57 is grown, and finally a second InSb contact layer 58 having a thickness of 0.5 μm is grown.

Next, as shown in FIG. 5B, using the patterned SiO ₂ film 59 as a mask, the second Si substrate 54 is used.
The mesa is formed by etching the upper compound semiconductor layer. The position of the mesa in the horizontal plane is made to coincide with the position of the opening provided in the first Si substrate 51. At the stage when the multilayer structure is grown on the second Si substrate 54, the entire structure is warped due to thermal strain due to a difference in thermal expansion coefficient, but is flattened by forming a mesa.

[0068] Next, as shown in FIG. 5 (c) SiO ₂ film 5
9 is removed, the laminated structure on the first Si substrate 51 and the second Si substrate 54 is replaced with the first InS provided in the opening.
The surfaces are overlapped with each other via the b-contact layer 53 and the second InSb contact layer 58 on the mesa, and a light weight is placed thereon, and the hydrogen is melted in hydrogen at a melting point of about 525 ° C. or higher.
Lamp heating was performed for a short period of seconds. In this process, the laminated structures on both substrates were joined.

Finally, as shown in FIG. 5D, the second Si substrate 54 and GaAs are formed by polishing and selective etching.
Buffer layer 2, first GaAs device layer 55, InG
The surface of the second GaAs device layer 57 is exposed by removing the aAs / GaAs strained superlattice layer 56 and the AlAs spacer layer 23.

In the crystal quality of the GaAs device layer obtained in this example, a PL measurement showed an emission intensity almost equal to that of the growth layer on the GaAs substrate. It was also found that the shift of the emission wavelength was small and the thermal strain was almost alleviated. This is the patterning by mesa formation and the second S
This is because the i-substrate 54 was removed. The result of TEM observation, the dislocation density much 10 ⁴ ~10 ⁵ cm ^- it was found ^{that 2} good crystal quality is obtained.

In this embodiment, since the compound semiconductor crystal formed by direct epitaxial growth on the second Si substrate 54 is moved onto the first Si substrate 51 by the bonding method, for example, 8
It can be matched with a normal Si VLSI process using a large-diameter Si substrate.

Further, since the InSb contact layer is instantaneously melted and bonded by heat treatment in a very short time, the influence on the Al wiring can be minimized. Furthermore, since the covalent bond interface is basically formed, the bonding strength is increased. Is also strong.

In this embodiment, the first InSb contact layer 53 is formed in the opening where the surface of the first Si substrate 51 is exposed. However, if a crystal layer exists in the Si device structure layer 52, the surface is exposed. The opening may be formed, or may be formed on the surface obtained by further etching from the surface of the first Si substrate 51.

Although the first InSb contact layer 53 is formed only in the opening, the first InSb contact layer 53 may be formed on the entire surface and used only in the opening, or a SiO ₂ mask formed on a surface other than the surface of the opening may be used. And may be selectively grown by MOCVD or the like.

As a mask for mesa etching and further for the selective growth, for example, AlN other than SiO ₂ film is used.
And Si ₃ may be used amorphous film, such as N _4, may be used organic semiconductors crystal or metal, also resist film other as mesa etching.

Further, another method may be used for melting the InSb contact layer. For example, if light of a suitable wavelength that is absorbed only by the InSb layer is applied, only InSb can be heated, melted and bonded. The influence on the Al wiring is completely suppressed, and the occurrence of thermal strain due to the bonding process itself can be avoided.

Although the gas source MBE method or the MOCVD method is used as a growth method in the above five embodiments, another method such as a halogen transport method may be used.

In Examples 2 and 4, when the upper and lower layers are press-bonded via the metal In layer, the melting point of In is heated to about 157 ° C. or more. However, other methods such as applying ultrasonic vibration may be used. good. As the metal layer, metal In which is easy to convert from InP to In was used.
It may be converted into nGaP → In—Ga alloy. Although the desorption of P is slowed by the addition of Ga, the melting point of the In—Ga alloy can be lowered.

In the five embodiments, the case where the InP layer or the GaAs layer is formed on the Si substrate and the case where the InP layer is formed on the GaAs substrate have been described as examples.
Family substrate Ge or Si _x Ge _{1 - x} mixed crystal, also Si _x Ge
_{In the} case of having a _1-x mixed crystal epilayer, or in the case where the III-V substrate is InP or GaP, or in the case of a mixed crystal, further formed III-V compound semiconductor layer is formed of another InAs or GaP,
In the case of a mixed crystal such as InGaP, a plurality of types of III
The present invention can be widely applied to a case where -V group compound semiconductor layers are mixed.

The bonding method is also set according to the purpose.
Different combinations from the one embodiment may be employed. For example, the InSb contact layer may be adhered only by heat treatment at a temperature lower than the melting point for an appropriate time without melting. Further, as a method of bonding the support substrate in the third and fourth embodiments, a heat-resistant organic adhesive material such as polyimide may be used.

[0081]

As described above, according to the present invention, a high-quality III- or III-V lattice mismatched substrate
A composite semiconductor multilayer structure having a group V compound semiconductor single crystal layer can be realized at a low temperature.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a process of an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the steps of the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the steps of the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing the steps of the embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the steps of the embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 Si substrate 2 GaAs buffer layer 3 First In Sb contact layer 4 InP substrate 5 InGaAs spacer layer 6 InP device layer 7 Second In Sb contact layer 21 First InP layer 22 GaAs substrate 23 AlAs spacer layer 24 GaAs device Layer 25 Second InP layer 26 First metal In layer 27 Second metal In layer 31 First InGaAs spacer layer 32 Second InGaAs spacer layer 33 Third InP contact layer 34 InP support substrate 35 Fourth InP contact layer 41 Si support substrate 51 first Si substrate 52 Si device structure layer 53 first InSb contact layer 54 second Si substrate 55 first GaAs device layer 56 InGaAs / GaAs strained superlattice layer 57 second GaAs device layer 58 Second InSb Ntakuto layer 59 SiO ₂ film

Claims (18)

(57) [Claims] 1. The method according to claim 1, wherein the first semiconductor substrate is directly or
First InS sandwiching one III-V compound semiconductor layer
b) a step of growing a contact layer, and a step of:
Directly or the second III-V compound semiconductor layer
Growing a second InSb contact layer with the interposition therebetween;
Via the first and second InSb contact layers
The laminated structures on the first and second semiconductor substrates
And crimping step.
A method for manufacturing a combined semiconductor laminated structure. 2. The composite semiconductor multilayer structure according to claim 1,
In the manufacturing method, the two
Compression bonding of laminated structures on a semiconductor substrate
You. 3. The composite semiconductor multilayer structure according to claim 1.
In the manufacturing method, the InSb contact layer
Two semi-conductors while melting by heating for a short time at a melting point of 525 ° C or higher
Compression bonding of laminated structures on a body substrate
A method for manufacturing a composite semiconductor laminated structure. 4. The composite semiconductor multilayer structure according to claim 1.
In the manufacturing method of the above, only the InSb contact layer
By irradiating light of a wavelength that can be absorbed, the InSb
While heating only the layer at a melting point of 525 ° C or higher,
It is characterized in that the laminated structures on the conductor board are crimped together
Of manufacturing a composite semiconductor laminated structure. 5. The method according to claim 1, wherein the first semiconductor substrate is directly or
A first In-based material with one III-V compound semiconductor layer interposed therebetween
Growing a group III-V compound semiconductor layer;
Group V element from one In-based III-V compound semiconductor layer
Converted to the first In-based metal contact layer by thermal evaporation
Through the first In-based metal contact layer
The laminated structure on the first semiconductor substrate and the second semiconductor substrate
Directly press-bonded to the plate, or the second semiconductor substrate
A step of forming a second laminated structure thereon and then crimping them together
And a composite semiconductor product having at least
Manufacturing method of layer structure. 6. The composite semiconductor multilayer structure according to claim 5.
In the manufacturing method, the second lamination on the second semiconductor substrate
The step of forming a structure is performed by the second semiconductor substrate. Straight on the board
Contact or sandwich the second III-V compound semiconductor layer
To grow a second In-based III-V compound semiconductor layer
Of a composite type semiconductor laminated structure characterized by comprising a process
Production method. 7. The composite semiconductor multilayer structure according to claim 5.
In the manufacturing method, the second lamination on the second semiconductor substrate
Forming a structure directly on the second semiconductor substrate;
Contact or sandwich the second III-V compound semiconductor layer
To grow a second In-based III-V compound semiconductor layer
Step and the second In-based III-V compound semiconductor layer
Group V element is thermally evaporated from
And converting it to a tact layer.
Of manufacturing a composite semiconductor multilayer structure. 8. The method according to claim 5, 6 or 7, wherein
In the method for manufacturing a composite semiconductor laminated structure described above,
Or the second In-based III-V compound semiconductor layer is InP
Manufacture of a composite semiconductor laminated structure characterized by being a layer
Method. 9. The method according to claim 5, 6 or 7, wherein
In the method for manufacturing a composite semiconductor laminated structure described above,
Or keeping the second In-based metal contact layer above the melting point.
Or the first or second In-based metal contactor
Apply ultrasonic vibration to the layer or use these means together
The first or second In-based metal contact
A layered structure on the first semiconductor substrate while melting the layers;
The second product on the second semiconductor substrate or the second semiconductor substrate
Composite semiconductor laminate characterized by crimping layer structure
The method of manufacturing the structure. 10. Directly on the first semiconductor substrate, or
The first In-layer sandwiching the first III-V compound semiconductor layer
III-V compound semiconductor contact layer, III-V
Sequentially growing a group III compound semiconductor device layer;
Connecting a support substrate on a III-V compound semiconductor device layer
Removing the first semiconductor substrate, and further removing the first semiconductor substrate.
III-V compound semiconductor layer, if any, is also removed
To form a first In-based III-V compound semiconductor contactor.
Exposing the surface of the semiconductor layer;
Contact or sandwich the second III-V compound semiconductor layer
And second In-based III-V compound semiconductor contact layer
Growing the first In-based I with the surface exposed
II-V compound semiconductor contact layer and the first Second
Via an In-based III-V compound semiconductor contact layer
Laminated structure on the support substrate and the second semiconductor substrate
Characterized by having at least a step of crimping each other.
Of manufacturing a composite semiconductor multilayer structure. 11. The composite semiconductor layered structure according to claim 10.
In a method of manufacturing a structure, a semiconductor device is formed on a first semiconductor substrate.
III-V compound semiconductor device of the uppermost layer of the laminated structure
Adhering a support substrate on the support layer,
Third In-based III-V group on compound semiconductor device layer
Growing a compound semiconductor contact layer;
Directly on a substrate or a third III-V compound semiconductor
A fourth In-based III-V compound semiconductor
Growing a contact layer, and the third and fourth steps
Via an In-based III-V compound semiconductor contact layer
The first semiconductor substrate, a laminated structure on a supporting substrate, etc.
Specially consist of at least the step of crimping the cattle.
A method for manufacturing a composite semiconductor laminated structure. 12. The composite semiconductor layered structure according to claim 10.
In a method of manufacturing a structure, a semiconductor device is formed on a first semiconductor substrate.
III-V compound semiconductor device of the uppermost layer of the laminated structure
Adhering a support substrate on the support layer,
At least the compound semiconductor device layer and the supporting substrate
The step of forming an organic adhesive substance layer on one surface,
On the first semiconductor substrate through the organic adhesive material layer
Laminated structure, and the step of pressing the supporting substrates together
Composite semiconductor characterized by at least the following:
Manufacturing method of laminated structure. 13. A composite according to claim 5 or claim 10.
In the method of manufacturing a semiconductor multilayer structure, the first and second
The semiconductor substrate and the supporting substrate according to claim 10 may further include a supporting substrate.
III-V compound semiconductor substrate or IV semiconductor
Composite semiconductor, characterized in that it is one of a body substrate
Manufacturing method of laminated structure. 14. The method according to claim 1, wherein the first group IV semiconductor substrate is directly
Alternatively, a group IV device layer may be formed with a group IV buffer layer interposed therebetween.
Forming on the surface of the group IV device layer
Partially before by etching using the mask pattern
The surface of the group IV buffer layer or the first group IV half.
Providing an opening in which the surface of the conductive substrate is exposed;
Directly on the surface of the Group IV crystal exposed at the opening, or
A first group III-V compound semiconductor buffer layer
Of In-based III-V compound semiconductor contact layer
And directly or on the second group IV semiconductor substrate.
Is located across the second III-V compound semiconductor buffer layer.
III-V compound semiconductor device layer and second In
For growing a system III-V compound semiconductor contact layer
And etch using an island-shaped mask pattern
Forming a mesa by etching, and the mask pattern
After removal of the first In-based III-V compound
A conductor contact layer and a second I remaining on the mesa
via an n-type III-V compound semiconductor contact layer
The laminated structure on the first and second group IV semiconductor substrates
And a step of crimping a cattle.
Of manufacturing a composite semiconductor multilayer structure. 15. The claim 10 or claim 11 or claim
14. The method for manufacturing a composite semiconductor multilayer structure according to item 14 , wherein the In-based III-V compound semiconductor contact layer is
any one of an nP layer, an InAs layer, and an InSb layer;
A method for manufacturing a composite semiconductor multilayer structure, comprising: bonding a multilayer structure on two semiconductor substrates while heating the same to a temperature of 00 ° C. or higher. 16. A method according to claim 10 or claim 11.
14. The method for manufacturing a composite semiconductor multilayer structure according to item 14 , wherein the In-based III-V compound semiconductor contact layer is
A method for manufacturing a composite semiconductor multilayer structure, wherein the multilayer structure on two semiconductor substrates is pressure-bonded while heating and melting the InSb layer at a melting point of 525 ° C. or higher for a short time. 17. A method according to claim 10 or claim 11.
14. The method for manufacturing a composite semiconductor multilayer structure according to item 14 , wherein the In-based III-V compound semiconductor contact layer is
The nSb layer is irradiated with light having a wavelength that can be absorbed only by the InSb layer so that only the InSb layer has a melting point of 5.
A method for manufacturing a composite semiconductor multilayer structure, comprising: bonding a multilayer structure on two semiconductor substrates while heating and melting at 25 ° C. or more. 18. A method according to claim 10 or claim 11.
15. The method of manufacturing a composite semiconductor multilayer structure according to item 14 , wherein after growing an In-based group III-V compound semiconductor contact layer, the group-V element is thermally evaporated.
A composite semiconductor laminate comprising: converting a II-V compound semiconductor contact layer into an In-based metal contact layer; and pressing the laminated structures on the two semiconductor substrates through the In-based metal contact layer. The method of manufacturing the structure.