JP2608965B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including a floating gate type field effect transistor and a method of manufacturing the same.

Conventional technology Conventionally, EEPROM (Electric
ally Erasable and Programmable ROM)
2. Description of the Related Art A semiconductor memory device having a floating gate structure that performs writing and erasing by tunneling injection is well known.
In this semiconductor memory device having a floating gate structure, charge tunneling injection is performed through a thin insulating film on a diffusion layer, charges are accumulated in a floating gate electrode on the thin insulating film, and the threshold voltage of the transistor is changed. It is based on the principle that information is stored.

 Hereinafter, a conventional semiconductor memory device will be described.

FIG. 2 is a sectional view of a main part of a conventional floating gate type semiconductor memory device. As shown in FIG. 2, a source region 22 and a drain region 23 made of an N-type diffusion layer are formed in a P-type silicon substrate 21, and a relatively thick silicon oxide film 24 extends over the source region 22 and the drain region 23.
Is formed, and only a portion of the silicon oxide film 24 is opened. A thin silicon oxide film 25 serving as a tunneling medium is formed in the opening, and a floating gate electrode 26 is formed on the silicon oxide films 24 and 25. , A silicon oxide film 27 and a control gate electrode 28 are sequentially laminated.

Conventionally, when a floating gate type semiconductor memory device as shown in FIG. 2 is manufactured, N type diffusion layers 22 and 23, silicon oxide films 24 and 25, floating gate electrode 26 are usually formed on the surface of a P type silicon substrate 21. , Silicon oxide film 2
7 and the control gate electrode 28 were sequentially laminated.

SUMMARY OF THE INVENTION However, in the above conventional configuration, the control gate electrode of the floating gate type semiconductor memory device is not provided.
28 and the floating gate electrode 26 are capacitively coupled by the silicon oxide film 27, so that the control gate electrode
In order to perform erasing and writing efficiently and at a high speed, it is necessary to reduce the thickness of the silicon oxide film 27 between the control gate electrode 28 and the floating gate electrode 26 or to increase the area of the control gate electrode 28. However, since a high voltage is applied to the silicon oxide film 27 between the two electrodes during writing and erasing, the thickness cannot be reduced due to reliability problems. For this reason, it is necessary to increase the area of the control gate electrode 28 in order to perform high-speed writing and erasing, and there is a problem that it is difficult to achieve high integration because the area of the memory cell becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor memory device having a floating gate structure realizing high-speed operation and high integration, and a method of manufacturing the same.

Means for Solving the Problems To achieve this object, a semiconductor memory device according to the present invention includes a source region of the other conductivity type at a bottom of a trench provided in a semiconductor substrate of one conductivity type, and a source region near a surface trench of the semiconductor substrate. On the other hand, a drain region of the conductivity type is provided, and a gate insulating film is provided on the trench side wall and bottom from the surface of the semiconductor substrate except for a thin insulating film serving as a tunneling medium on the source region. And a floating gate electrode is provided on the side wall of the trench, and a control gate electrode is provided on the floating gate electrode via an insulating film.

Operation With this configuration, most of the control gate electrode is formed on the side wall of the trench, so that the area of the control gate electrode can be larger than that of a conventional planar memory cell transistor, and the coupling capacitance between both electrodes increases. I do. Therefore, control efficiency by the control gate electrode is improved, and the speed of writing or erasing data on the floating gate can be improved. In addition, since most of the two electrodes are formed on the side wall of the trench, the two-dimensional area of the memory cell transistor can be reduced as compared with the conventional one.

An embodiment of the present invention will be described below with reference to the drawings.

1 (a) to 1 (d) are cross-sectional views of a semiconductor memory device according to an embodiment of the present invention in the order of manufacturing steps. In the figure,
1 is a P-type semiconductor substrate, 2 is a trench, 3 is a trench bottom, 4 is a source region, 5 is a drain region, 6 is a silicon oxide film, 7 is a thin silicon oxide film, 8 is a floating gate electrode, and 9 is a silicon oxide film. , 10 are control gate electrodes.

Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 1 (a), on a P-type silicon substrate 1 having a specific resistance of 5 to 10 Ωcm, a width of 1.5 × 100 μm and a depth of 3 μm.
Reactive ion etching (RIE method) for trench 2
Formed by a dry etching technique. Using a resist pattern formed by photolithography at the bottom 3 of the trench 2 and a predetermined position on the surface of the P-type silicon substrate 1 as a mask, arsenic is implanted at a dose of 1 × 10 ¹⁴ / c.
Implantation is performed at m ² and an acceleration voltage of 140 KeV, and then annealing is performed in a nitrogen atmosphere at 900 ° C. for 30 minutes to form a diffusion layer serving as the source region 4 and the drain region 5. Next, as shown in FIG. 3B, a silicon oxide film 6 is formed to a thickness of 50 nm on the surface of the P-type silicon substrate 1 and inside the trench in a steam atmosphere of 900 ° C. Further, an opening serving as a tunneling region is formed in the silicon oxide film 6 by photolithography,
A thin silicon oxide film 7 serving as a tunneling medium is formed at 900 ° C. in a steam atmosphere containing 1 mol% of trichloroethane. Next, as shown in FIG. 2C, a polycrystalline silicon film containing 3 × 10 ²⁰ / cm ³ of phosphorus atoms is formed to a thickness of 300 nm by a low pressure CVD method.
The floating gate electrode 8 is formed by depositing and patterning by photolithography. Next, as shown in FIG. 4D, the floating gate electrode 8 is formed by a rapid oxidation method using a lamp in an oxygen atmosphere at 1150 ° C.
A 45 nm silicon oxide film 9 is formed thereon, and a reduced pressure CV
A 200 nm-thick polycrystalline silicon film containing 3 × 10 ²⁰ / cm ³ of phosphorus atoms is formed by the method D, and a pattern is formed by photolithography to form the control gate electrode 10. After that, arsenic was implanted again at a dose of 2 × 10 ¹⁵ / cm ² and an acceleration voltage of 4
Ion is implanted into the drain region 5 at 0 KeV.

In addition, as shown in FIG. 1 (d), a main part of the semiconductor memory device according to one embodiment of the present invention is formed with two memory sensing transistors on the side wall inside the trench, and selects these memory sensing transistors. The transistor has the same drain region as the memory sensor transistor, and is formed on both sides of the trench. At this time, the source region of each memory cell transistor is common at the bottom of the trench.

As described above, according to the present invention, the occupation area of the memory cell transistor can be reduced, and the coupling capacitance between the control gate electrode and the floating gate electrode can be increased. An object of the present invention is to realize an excellent semiconductor memory device capable of achieving higher speed and higher speed and a method of manufacturing the same.

[Brief description of the drawings]

1 (a) to 1 (d) are cross-sectional views in the order of manufacturing steps of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part of a conventional floating gate type semiconductor memory device. DESCRIPTION OF SYMBOLS 1 ... P type semiconductor substrate (semiconductor substrate), 2 ... trench, 3 ... trench bottom part, 4 ... source region (first diffusion region), 5 ... drain region (second diffusion region), 6
... Silicon oxide film (first insulating film), 7... Thin silicon oxide film (second insulating film), 8... Floating gate electrode (first gate electrode), 9. 3 insulating film), 10... Control gate electrode (second gate electrode).

Claims (2)

(57) [Claims] 1. A first diffusion region of the other conductivity type provided at the bottom of a trench provided in a semiconductor substrate of one conductivity type, and a second diffusion region of the other conductivity type provided adjacent to both sides of the trench on the semiconductor substrate. A first insulating film provided over the surface of the semiconductor substrate and the sidewalls and the bottom of the trench, and a thin first insulating film provided at an opening formed in the first insulating film over the second diffusion region. A second gate insulating film, a first gate electrode provided on the surface of the semiconductor substrate including the opening and on the side wall of the trench, and a second gate electrode provided on the first gate electrode with a third insulating film interposed therebetween. And a gate electrode. 2. A step of forming a trench in a semiconductor substrate of one conductivity type, a first diffusion region of the other conductivity type at the bottom of the trench, and a second diffusion region of the other conductivity type at a trench on the semiconductor substrate. Forming a first insulating film covering the surface of the semiconductor substrate and the side wall of the trench; forming an opening of the first insulating film on the second diffusion region; Forming a thin second insulating film in the opening, forming a first gate electrode on the surface of the semiconductor substrate including on the opening and on the side wall of the trench,
Forming a second gate electrode over the first gate electrode with a third insulating film interposed therebetween.