JP2596087B2 - Packet switching method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a technology for configuring an ultra-high-speed packet switch.

(Prior Art) A paper on a conventional ultra-high-speed switch was published in the 1984 International Switching Symposium (Internat
A. Thomas and others at the ional Switching Synposium 1984), "Asynchonous Time Div.
ision Technique) "(Reference 1). Also 198
A paper "Study on ATM switching architecture" presented by Suzuki et al. At IEICE SSE88-60
(Reference 2).

In these papers, packet signals from a plurality of incoming lines are time-division multiplexed and written to a memory to perform an exchange operation. FIG. 5 shows an example.

This switch converts packets 501 to 503 input from an incoming line into a serial / parallel converter (S / P) 509 to 511.
Slow down with. After that, time division multiplexing is performed on the time division bus 500. Here, let V be the speed of the incoming line. When the data is expanded to kbit by the serial / parallel converters 509 to 511, the speed becomes V / K. However, when these N incoming lines are time-division multiplexed, However, operation speed is required. The packet has physical address information indicating to which output line the packet should be output. As a method for this, a case where the packet 600 has the header 601 of the packet 600 as shown in FIG.
02 and may be processed in parallel as in 603. (However, the physical address mentioned here is used only for controlling the switch, and is not a logical address of the packet header.) Each packet which has been time-division multiplexed is broadcast to all outgoing lines on the bus 500. You. Address filter (AF) 512-514
Checks the address (601 or 603) of each packet and receives a packet if it should be output. Otherwise, no packet is received. In this way, reception is performed on the outgoing line described in the address. Then buffer memory (FI
FO) 515-517 written first-in first-out. By reading the packet from the FIFO memory, the packet is output to the outgoing lines 504 to 506.

(Problems to be solved by the invention) In the conventional packet switch, since time division multiplexing is performed,
As the line speed V and the number N of lines increase, the operating speed (NV / K) of the time division multiplexing unit also increases. Since the operating speed of the circuit is limited, it is necessary to increase the number k of parallel bits to suppress the increase in operating speed.

On the other hand, in the current LSI technology, FIG.
It is difficult to integrate the SI into a large N as the amount of memory and the number of gates increase. Therefore, as shown by a broken line in FIG. 5, an LSI is formed by dividing a block to reduce the amount of memory and the number of gates. In such a case, the above-mentioned k-bit bus does not extend between LSIs.
Invites a pin neck. For example, V = 160M N = 32 and LSI
K = 1 to keep the upper limit of I / O operation speed to 40Mbps
It becomes 28. As described above, it is difficult to operate a multi-bit bus extending between LSIs at high speed. Therefore, k cannot be easily increased, and an increase in the I / O speed of the LSI is a bottleneck. That is, there is a problem that it is difficult to increase the line speed or increase the number of lines.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art, and provides a method of configuring a switch that can sufficiently accommodate an ultra-high-speed line and increase the number of lines.

(Means for Solving the Problems) The present invention is a packet switch for outputting a packet signal from a plurality of incoming lines to any of a plurality of outgoing lines based on address information of the packet, and one packet for each incoming line. A signal is serial-to-parallel converted and divided into a plurality of bits, and a packet signal of at least one bit of the plurality of serial-parallel-converted bits is input to an input port corresponding to the input line of the sub-switch. A plurality of pieces of address information respectively corresponding to the packet signals from the switch controller, the switch controller determines which output line each packet signal is to be output from the input address information, For each signal, the sub-switch is notified of the identification information of the outgoing line, and the sub-switch transmits a plurality of packet signals input from the plurality of input ports. And time-division multiplexing the packet signal into one of a plurality of output ports of the sub-switch based on the identification information of the output line to output the packet notified from the switch control unit. A plurality of sub-switches for respectively exchanging a plurality of bit numbers of the serial-to-parallel converted packet signal are operated in parallel, and at each output line, the output of the plurality of sub-switches is output. A plurality of serial-to-parallel converted packet signals output from an output port corresponding to a line are subjected to parallel-to-serial conversion.

Further, the present invention is a packet switch for outputting packet signals from a plurality of incoming lines to any of a plurality of outgoing lines based on address information of the packet, and performs serial / parallel conversion of each one packet signal at each incoming line. And input a packet signal of at least one bit of the serial-to-parallel converted bits to an input port corresponding to the input line of the sub-switch, and convert the packet signal from the plurality of input lines into a packet signal. A plurality of corresponding pieces of address information are input to the switch control unit, and the switch control unit determines which output line each packet is to be output from based on the input address information, and outputs each packet input to the sub-switch. Write / Write packet buffer memory to store signals
A read address is obtained, and for each packet signal, write / read address information of the packet buffer memory is notified to the sub-switch, and the sub-switch divides the plurality of packet signals input from the plurality of input ports into a time-division format. By multiplexing and writing / reading the time-division multiplexed packet signal to / from the buffer memory based on the write / read address information of the packet buffer memory notified from the switch control unit, a plurality of Output to any of the outgoing ports,
The sub-switches for exchanging signals of a plurality of bits of the serial-parallel-converted packet signal are operated in parallel, and at each output line, an output port corresponding to the output line of the plurality of sub-switches. A plurality of serial-to-parallel-converted packet signals to be output are subjected to parallel-to-serial conversion.

Further, the present invention is a packet switch that outputs packet signals from a plurality of incoming lines to any of N outgoing lines based on address information of the packet, and broadcasts each incoming line packet signal to a plurality of sub-switches. The sub-switch has only output circuits corresponding to M outgoing lines (M <N) out of N outgoing lines, and time-division multiplexes a plurality of packet signals input from the plurality of input ports. A packet switch for outputting the time-division multiplexed packet signal to one of M outgoing lines based on address information of the packet.

(Operation) In the present invention, the time-division multiplexing unit requiring the highest speed operation is
It is configured to be closed inside the LSI. This makes it possible to extend the parallel expansion degree k of the time division multiplexing unit to the packet length, and the internal speed of the operation speed can be higher than that of the LSI I / O. It will be easier. However, as described above, the problem is that in order to integrate circuits for N lines into one LSI, the number of gates and the amount of memory to be accommodated in one LSI greatly increase. . The present invention divides a switch into bit slice type sub-switches (first to third inventions). Alternatively, since the gate and the memory are concentrated on the output side circuit, they are divided into sub-switches having a reduced number of outgoing lines (fourth
By reducing the number of gates entering one sub-switch and the amount of memory, the configuration of the present invention is realized.

In the first invention, the time division multiplex switch is divided into bit slices. The P parallel sub-switches operate in parallel, and each sub-switch switches only 1 / P bits when a packet is expanded into parallel bits. In this way, the number of gates for N ports and the number of memories become 1 / P, so that one sub-switch can be inserted in the LSI, and the time-division bus is also LSI.
Because it goes inside, it doesn't become Pin Neck.

The second invention also has a similar bit slice configuration, but the control unit processes the packet address information collectively, and notifies only the processing results to the sub-switches operating in parallel. In the first invention, the same address processing circuit is required for each sub-switch. In the second invention, only one address processing circuit may be concentrated. Therefore, the number of gates is reduced.

In the third invention, the control of the write / read address of the memory for storing the packet is further centralized in the control unit in the second invention, and the sub-switch is made only of the multiplexing device and the memory (RAM). Similarly, the number of gates decreases.

According to a fourth aspect of the present invention, the number of outgoing lines included in one sub-switch is reduced to perform division. That is, it focuses on the fact that the gate and the memory are concentrated at the output. Each sub-switch has a time division multiplexing section with all input lines, but has only M (M <N) outgoing lines less than the total number N of outgoing lines. For example, a 32 × 32 switch is composed of eight 32 × 4 sub-switches. This subswitch is one LSI
Therefore, as in the first invention, it is easy to increase the speed of the time division multiplexing unit.

(Example) Hereinafter, a detailed description will be given with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the first invention. 100 and 101 are sub-switches. The incoming lines 102 to 104 are converted into P × Q bit parallel by serial / parallel converters (S / P) 105 to 107. Here, P and Q are integers of 1 or more. Here the Q
It is assumed that each bit is input to each sub-switch. Therefore, the sub-switch has a P-plane. One sub-switch has the same structure as the conventional switch shown in FIG. That is, the operation in the time division multiplexing unit composed of the serial / parallel converters 108 to 110 and the time division multiplexing bus 111 and the operation of these sub-switches composed of the address filters 113 to 115 and the FiFo memories 116 to 118 have been described with reference to FIG. Same as the one. However, care must be taken here regarding the handling of packet addresses in the switch. The addresses of the packets are as shown in FIGS. 6A and 6B outside the switch. In the case of serial connection as shown in FIG.
Take out only one. Serial / parallel expansion covers only 600 packet parts. In the case of FIG. 6B, 603 is extracted and only the packet part of 602 is subjected to serial / parallel development. The extraction of the address is performed by the serial / parallel converters 105 to 107. Address is address signal line 124-1
At 26, it is sent to each sub-switch in parallel with the packet signal lines 127-129. Although the packet and the address are multiplexed once, the address filters (AF) 113 to 115 detect only the address part. The packets are stored once in the FiFo memories 116 to 118 and then output and returned to the original packets by the parallel-serial converters 119 to 121. The operating speed of the switch in this case is as follows. It is assumed that the line speed is V and the number of lines is N. At the input to the subswitch, the packet is expanded to P × Qbit, so the I / O speed is It has become. Since time division buses are multiplexed by N Of throughput is required. Therefore, if the serial-parallel converter of 108-110 further expands to Kbit, the internal speed will be Becomes

As an example only, and V = 160Mbps N = 32 P = 8 Q = 1 k = 32 to the _{V i / o = V in =} 20Mbps N or P = 16 V even doubled and Q = 2 The increase in operating speed can be avoided.

The number of gates is as follows. In FIG. 5, G is the number of circuit gates (including memory) for one line. In FIG. 5, each block (broken line) has only G gates. In Fig. 1, each sub-switch is Gate amount.

That is, it can be seen that increasing P increases the gate amount per subswitch.

Next, an embodiment of the second invention is shown in FIG. The difference from FIG. 1 is that the address of the packet is processed by the control unit 238 and the write enable of the FiFos 217 to 219 is notified to the sub-switches 220 to 221 through the signal lines 235 to 237. In FIG. 1, the same address filter (AF) 113 must be provided with all sub-switches, and only the control unit is combined. As a result, the number of gates of the sub-switches 220 to 221 is further reduced and the sub-switches operating in parallel can be centrally controlled, so that control management becomes easy. The address information of the packet input from the incoming lines 200 to 202 is separated from the packet by the serial / parallel conversion units 203 to 205 and the control unit 23 is output by 206 to 208.
Entered in 8. The packet is expanded into P × Q bits as in FIG. 1 and input to each of the sub-switches 220 to 221 by Q bits. The control unit 238 time-division multiplexes the address with the serial / parallel (S / P) converters 228 to 230 and the time-division bus 231.
This operation operates in parallel with the S / P converters 212 to 214 of the subswitches 220 and 221 and the time division multiplexing operation of each packet on the time division buses 215 and 216. The address filters 232 to 234 check the address and determine which output port FiFo 217 to 219 should store the packet. The result is notified as 235-237 to each FiFo 217-219 of each sub-switch as a write enable signal. Based on this signal, the sub-switch writes the packet to the FiFo of the desired port. The packet is read out from the FiFo, returned to its original form by parallel / serial (P / S) converters 222 to 224, and output to the output lines 225 to 227. In such a configuration, in addition to the effect of the first aspect, AF on the sub-switch surface is not required, and the number of gates is reduced.

Since the sub-switches operating in parallel can be intensively controlled, synchronization between the sub-switches is facilitated and management becomes easy.

There is an advantage.

 Next, an embodiment of the third invention will be described with reference to FIG.

Basically, the difference from the embodiment of the second invention (FIG. 2) is as follows.
This is a method of controlling the FiFo memory. In FIG. 2, the FiFo of the same output port of each sub-switch is all controlled by the same write / read address. Therefore, if this control circuit is concentrated instead of each sub-switch, the number of gates of the sub-switch is further increased. The subswitch only needs to have RAM. On the other hand, in this case, the synchronous operation management of the sub-switches operating in parallel can be completely concentrated, so that the reliability is further improved. The multiplexing processing of the packets input from the incoming lines 300 to 302 is exactly the same as in FIG. Reference numerals 303 to 305 denote serial / parallel converters, which separate addresses into 306 to 308 and input them to the control unit 343. The packets are input to the sub-switches 320 and 321 at 309 to 311. The time-division multiplexing operation is performed by the serial / parallel converters 312 to 314 and 328 to 330 and the time-division buses 315, 316, and 331. The address of the time-division multiplexed packet is detected by the address filter (AF) 332 to 333, and the AF of the port to be received is set to the write enable RAM.
Notify the controllers 354 to 356. RAM controller is R
This is for managing FiFo of AM317-319. At 337 to 339, a write address is notified to each RAM of each sub-switch.

Thus, the time-division multiplexed packet is stored in the RAM of the desired port. RAM controller 354 of control unit 343
356 outputs the read addresses of the RAMs 317 to 319, whereby the packets are output. Parallel-serial converter 322
The packet output at ~ 324 is returned to the original form and outgoing line 325
To 327.

In the first to third embodiments of the present invention, the output buffer type switch (refer to the literature) in which a memory is separately provided for each output line is shown. Reference). Even in that case, the present invention has its effect.

 Next, an embodiment of the fourth invention will be described with reference to FIG.

According to a fourth aspect of the invention, the sub-switches are configured by reducing the number of outgoing lines, and the incoming lines are broadcast and connected. For example, 32 × 32 switches and eight 32 × 4 sub-switches are created. In the figure, a 4 × 4 switch is composed of two 4 × 2 sub-switches.
This focuses on the fact that most of the number of gates of the switch is concentrated on the address filter and the FiFo memory on the output side, and this is divided into outgoing lines to reduce the number of gates on the sub-switch. Since all the time-division buses are included in the sub-switch, the present invention has an effect of easily coping with an increase in the line speed and the number of lines as in the first to third aspects. The incoming lines 400 to 403 are broadcast and input to the two sub-switches 408 and 409. Each of the sub-switches 408 and 409 has a time-division multiplexing unit including serial-parallel conversion units 410 to 417 and time-division buses 418 and 419, similarly to the switch of FIG. The address filters 420 to 423 and FiFo 424 to 427 for each port are divided into sub-switches.

The N × M (M <N) sub-switch may be a bit slice type in combination with the first invention, the second invention, and the third invention of the present invention. Alternatively, the control unit may be separated. Further, only the control unit may have an N × M (M <N) configuration. The FiFo memories for a plurality of outgoing lines of one sub-switch may be configured by a shared memory. In any case, the present invention has its effect.

(Effects) According to the first to fourth aspects of the present invention, a time-division bus whose speed is severely restricted can be inserted inside the LSI, so that the speed-up of the time-division bus can be easily realized. It can easily cope with an increase in the number. According to the first to third aspects of the present invention, by slicing the sub-switch into bits, it is possible to prevent an increase in the gate amount per LSI even if a time division multiplexing unit is provided inside the LSI. By centralizing the control unit as in the second and third inventions, the gate amount of the sub-switch can be further reduced, and the sub-switches operating in parallel can be centrally controlled and easily managed. Further, according to the fourth aspect, the output side circuit having a large number of gates can be reduced in the sub-switch. As described above, the time-division multiplexing unit can be confined in the LSI and the LSI can be configured with an appropriate gate amount, so that a more economical, high-speed, and large-capacity packet switch can be obtained with the advancement of the LSI technology in the future.

[Brief description of the drawings]

FIG. 1 is a block diagram of a packet switch according to an embodiment of the present invention. FIG. 2 is a block diagram of a packet switch according to the second embodiment of the present invention. FIG. 3 is a block diagram of a packet switch according to the third embodiment of the present invention. FIG. 4 is a block diagram of a packet switch according to an embodiment of the present invention. FIG. 5 is a block diagram of a conventional packet switch. FIG. 6 is a diagram showing how to transfer a packet and its address information. In the figure, 105-110, 203-205, 212-214, 228-230, 303-305, 312-
314,328-330,410-417 ... Serial / parallel converter, 113-115,232-234,332-334,420-423 ... Address filter, 116-118,217-219,424-427 ... First-in first-out (FIFO) memory, 119-121,222-224,322- 324 ... Parallel-serial converter, 354-356 ... RAM controller, 317-319 ... RAM.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-233858 (JP, A) IEICE Technical Report, SE 87-70, (1987-7-17), Shigeo Urushiya (1 other) Examination of self-routing communication channel, p. 31-35

Claims (3)

(57) [Claims] 1. A packet switching method for outputting packet signals from a plurality of incoming lines to one of a plurality of outgoing lines based on address information of the packet, wherein each packet signal is serially / parallel converted at each incoming line. And input a packet signal of at least one bit of the serial-to-parallel converted bits to an input port corresponding to the input line of the sub-switch, and convert the packet signal from the plurality of input lines into a packet signal. A plurality of pieces of corresponding address information are input to the switch control unit, and the switch control unit determines to which output line each packet signal is to be output from the input address information. The sub-switch notifies the sub-switch of line identification information, and the sub-switch performs time division multiplexing on the plurality of packet signals input from the plurality of input ports. The division multiplexed the packet signal,
Based on the identification information of the outgoing line to be output of the packet notified from the switch control unit, to output to any of the plurality of outgoing ports of the sub-switch, a plurality of serial-parallel converted packet signal A plurality of the sub-switches each exchanging a bit number are operated in parallel, and at each output line, a plurality of serial-parallel converted signals output from output ports corresponding to the output lines of the plurality of sub-switches are output. A packet switching method, which converts a packet signal from parallel to serial. 2. A packet switching method for outputting packet signals from a plurality of incoming lines to any one of a plurality of outgoing lines based on address information of the packet, wherein one packet signal is serial-to-parallel converted at each incoming line. Then, a packet signal of at least one bit of the plurality of serially-parallel-converted bits is input to an input port corresponding to the input line of the sub-switch, and a packet signal from the plurality of input lines is A plurality of corresponding address information is input to the switch control unit, and the switch control unit determines which output line each packet is to be output from based on the input address information, and outputs each packet input to the sub-switch. The write / read address of the packet buffer memory for storing packet signals is obtained, and for each packet signal, the packet buffer memory is read. To the sub-switch, the sub-switch time-division multiplexes the plurality of packet signals input from the plurality of input ports, and the packet buffer memory notified from the switch control unit. By writing / reading the time-division multiplexed packet signal to / from the buffer memory based on the write / read address information of
Output to any one of a plurality of output ports, and operate the sub-switch for exchanging signals of a plurality of bits of the serial-parallel-converted packet signal in parallel,
At each outgoing line, a plurality of serial-parallel-converted packet signals output from the outgoing ports corresponding to the outgoing lines of the plurality of sub-switches are subjected to parallel-to-serial conversion. 3. A packet switching method for outputting packet signals from a plurality of incoming lines to one of N outgoing lines based on address information of the packet, wherein each incoming line packet signal is broadcast to a plurality of sub-switches. The sub-switch is
It has only output circuits corresponding to M outgoing lines (M <N) out of the N outgoing lines, and time-division multiplexes a plurality of packet signals input from the plurality of input ports. A packet switching method comprising: outputting the multiplexed packet signal to one of M outgoing lines based on address information of the packet.