JPH0662056A - Packet switch - Google Patents

Abstract

PURPOSE:To construct a flexible network by combining sub switches, thereby realizing the packet switches of flexible configuration from small capacity to large capacity. CONSTITUTION:AFs119-122 of n/z pieces in an SWC 131 judge output lines based on the address information of the n/2 pieces of packets by combining m/2 pieces of SUB-SW 132-133 and one SWC 131. The packet switch of n-2 input and n/2 output configuration is provided by respectively controlling the readout of packets in two FIFO 123 and 124 and two FIFO 125 and 126 while using AF 119 and 121.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switch, and more particularly to a high speed packet switch.

[0002]

2. Description of the Related Art A conventional packet switch serially converts a packet signal into a plurality of bits in n input lines and converts at least one bit of the divided bits into an input port corresponding to an input line of a sub switch. The subswitch time-division-multiplexes packets input from a plurality of input ports, and switches the time-division-multiplexed packets to one of n output lines based on address information and outputs the packet. Thus, a plurality of sub-switches for exchanging a plurality of bits of a serial / parallel converted packet are operated in parallel, and parallel / serial conversion is performed on each output line to realize only an n-input / n-output packet switch. .

[0003]

This conventional packet switch lacks flexibility in switch capacity, and a flexible network cannot be constructed. Also, in the case of an LSI, for example, only switches with n inputs and n outputs can be made,
When trying to realize an n / 2-input n / 2-output switch, it is necessary to design a new LSI, or it is unreasonable to actually use only half of the capacity while doubling the capacity. There was a problem.

[0004]

A packet switch according to the present invention has n (n ≧ 2) input lines and output lines, and outputs a packet input from the input line based on address information. A packet switch for outputting to a line, wherein the packet input from each of the input lines is serial-parallel converted and divided into m bits.
A sub-switch for inputting a packet of at least one of the bits to an input port corresponding to the input line, and a switch control unit for inputting a plurality of address information corresponding to the packets from the n input lines. The switch control unit determines from which outgoing line each corresponding packet is output from the inputted address information, and a decision circuit for notifying the sub-switch of the identification information of this outgoing line for each packet. The sub-switch has time-division multiplexed the n packets input from the n input lines, and the output-line identification information notified from the switch control unit of the time-division multiplexed packets. A FIFO memory circuit for temporarily accumulating corresponding to any of the n output lines based on It was divided into preparative packets in parallel-serial conversion and outputs to the respective output lines.

Also, the m sub-switches are operated in parallel to form an n-input / n-output packet switch, and the k-input port and the k-output port are set to the same line and m /
n / k inputs by operating the k sub-switches in parallel
It is characterized in that a packet switch with n / k output (2 ≦ k <n) can be configured.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a packet switch showing an embodiment of the present invention.

Packet switches input from n input lines I1 to In are divided into m bits by serial / parallel conversion circuits (S / P) 100 and 103, respectively. The packet divided into m bits is time division multiplexed by a time division multiplexing bus (hereinafter referred to as TD-BUS) 112.

The address information sent at the same time as the packet is TD- of the switch control unit (hereinafter SWC) 135.
It is time-division multiplexed by BUS134. Judgment circuits (hereinafter referred to as AF) 104 to 107 judge an output line for outputting a packet based on the time-division multiplexed address information.

The AFs 104 to 107 are respectively corresponding FIFO memory circuits (hereinafter referred to as FIFO) 108 to 111.
Packets are temporarily stored in the parallel serial conversion circuit (P / P
S) 113 and 116 are m of the FIFO 108 and 111.
Convert the packet divided into bits and output line O1,
To On respectively. Sub switch 4 with this configuration
An n-input / n-output packet switch is realized by operating m pieces of (hereinafter, SUB-SW) 136 and 137 in parallel.

Next, FIG. 2 is a block diagram showing an example in which an n / 2 input / n / 2 output packet switch is realized by the packet switch of the present invention. The component abbreviations are the same as in FIG. The packets and address information input from I1 to In / 2 are SUB-SW132 and SWC, respectively.
Time division multiplexing is performed by 131 TD-BUS 129 and 130. Then, the AFs 119 to 122 determine the output line that outputs m / 2 packets based on the time-division multiplexed address information. The AFs 119, 122 control the corresponding FIFOs 123, 126 to S / P.
The packets from 117 are temporarily stored in the FIFOs 123 and 124, and the packets from the S / P 118 are stored in the FIFO 12
5, 126 is temporarily stored, and each S / P 127, to 128 converts the packet divided into m bits to O1, to On.
Output to / 2.

By operating m / 2 pieces of the SUB-SWs 132 and 133 of this configuration in parallel, n / 2 input.n / 2
An output packet switch is realized.

[0012]

As described above, according to the present invention, by using m sub switches or m / 2 sub switches, n inputs and
Since it is possible to configure an n-output packet switch or an n / 2-input / n / 2-output packet switch, it is possible to flexibly configure a network from a small capacity to a large capacity.

In addition, the packet switch of the present invention is an LSI.
When switching to LS, use only the sub switch as a functional unit.
By adopting I, packet switches with various capacities can be realized by combining sub-switches.
It has an effect that the design efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a packet switch of the present invention.

FIG. 2 is a packet switch of the present invention in which n / 2 inputs and n /
It is a block diagram which shows an example which implement | achieved the packet switch of 2 outputs.

[Explanation of symbols]

100, 103, 117, 〜 118 Serial-parallel conversion circuit (S / P) 112, 129, 130, 134 Time division multiplexed bus (TD-BUS) 104, 〜 107, 119, 〜 122 Judgment circuit (A
F) 108, -111,123, -126 FIFO memory circuit (FIFO) 113, -116,127, -128 Parallel-serial conversion circuit (P / S) 131,135 Switch control part (SWC) 132,133,136, 137 Sub switch (S
UB-SW)

Claims (2)

[Claims] 1. A packet switch having n (n ≧ 2) input lines and output lines and outputting a packet input from the input line to the corresponding output line based on address information, A sub-switch for converting the packet input from each input line into serial / parallel and dividing it into m bits, and inputting a packet of at least one bit of the divided m bits to an input port corresponding to the input line; A switch control unit for inputting a plurality of address information respectively corresponding to the packets from the n input lines, and the switch control unit outputs each corresponding packet from the input address information to which output line. A sub-switch for notifying the sub-switch of the identification information of the outgoing line for each packet. Time-division-multiplexed packets input from the n input lines, and the time-division-multiplexed packets are output to the n output lines based on the identification information of the output line notified from the switch control unit. A FIFO memory circuit that temporarily stores data corresponding to either
A packet switch characterized in that a packet divided into m bits in an IFO memory circuit is parallel-serial converted and output to each of the output lines. 2. An n-input / n-output packet switch is configured by operating the m sub-switches in parallel, and at the same time, the k input ports and the k output ports are provided in the same line, and the m / k sub-switches are operated in parallel. N / k input ・ n /
The packet switch according to claim 1, wherein a packet switch having k outputs (2≤k <n) can be configured.