KR100200555B1 - Atm cell sequence protecting circuit in atm exchange - Google Patents

Abstract

The present invention relates to an Asynchronous Transfer Mode Exchange (ATM), and more particularly, to an Asynchronous Transfer Mode (ATM) exchange, in which an ATM cell processing rate of an ATM exchange is higher than an input ATM cell rate, To an ATM cell order guarantee circuit of a channel group in an exchange. A channel group formed of a plurality of ports in a conventional ATM exchange guarantees excellent performance for instantaneous congested traffic, but there is a problem that the order of input and output ATM cells becomes different when the processing speed of the ATM exchange is increased. Even when the processing speed of the ATM exchange is increased by the present invention, it is checked how many ATM cells of the channel group are processed in the counter unit, and the number of processed ATM cells is decoded in the decoder and is applied to the order control unit. The order of the input and output ATM cells can be maintained.

Description

ATM cell order guarantee circuit of a channel group in an ATM exchange

The present invention relates to an Asynchronous Transfer Mode Exchange (ATM), and more particularly, to an Asynchronous Transfer Mode (ATM) exchange, in which an ATM cell processing rate of an ATM exchange is higher than an input ATM cell rate, To an ATM cell order guarantee circuit of a channel group in an exchange.

As the information is being developed rapidly and the amount of information to be exchanged has increased, a high-speed / multiple communication system has become necessary. As a result, the structure of Broadband Integrated Services Digital Network (BISDN) has been proposed, and the ATM exchange has served as an appropriate exchange.

In other words, it is possible to reduce the loss of data even if the channel group is composed of one or more ports, even if the traffic is instantaneously congested, and to reduce the loss of data due to congested traffic even when the exchange speed is faster ATM switching systems have been recently developed.

As shown in FIG. 1, the configuration for providing a channel group in the ATM exchanger according to the related art includes a plurality of input ports I 1 to I 4 for receiving ATM cells and a plurality of input ports I 1 to I 4, A switching unit 10 for switching the ATM cells applied through the switching unit 10 to form a channel group according to the formed channel group and a plurality of output ports (not shown) for outputting the switched ATM cells applied from the switching unit 10. [ 01 to 04).

The ATM exchange configured as described above operates as follows.

As shown in FIG. 1, for example, when an ATM cell input through the first input port I1 is switched to a channel group formed of two output ports 03 and 04 by the switching unit 10 Some of the switched ATM cells are physically output through the third output port 03 and the remaining part of the switched ATM cells are output through the fourth output port 04. [

At this time, the corresponding channel group allows the ATM cells output through the other output ports, for example, the third output port 03 and the fourth output port 04, to be transmitted to the same destination. Therefore, even though the output is output through any other output port (01 to 04) in the corresponding channel group, the final destination is the same, so that the loss of the ATM cell can be reduced even when the traffic is momentarily congested.

The order of the ATM cells output through the third output port 03 and the fourth output port 04 and the order of the ATM cells input through the first input port I1 should be the same. The processing time of one ATM cell in the corresponding switching unit 10 must be constant.

For example, assuming that the five ATM cell processing times as shown in FIG. 1 are respectively t1 to t5, the first ATM cell 1 input through the first input port I1 is connected to the third output port 03 3, 4, 5 at t3, t4, and t5 to the third output port 03 (t3) in such a manner that the second ATM cell 2 is output to the fourth output port 04 at t2, ) And the fourth output port 04 alternately. That is, the time (t1 to t5) for processing one ATM cell in the switching unit 10 must be the same as the arrival time of the ATM cell input through the first input port I1.

However, if the ATM cell processing rate of the switching unit 10 is faster than the arrival rate of the ATM cell input through the first input port I1, the third output port 03 forming the channel group, Output port 04 and can not maintain the order of the ATM cells input through the first input port I1.

For example, as shown in FIG. 2, an ATM cell input through the first input port I 1 is temporarily stored in the input buffer of the switching unit 10, and the switching unit 10 The first ATM cell 1 and the second ATM cell 2 are switched at the same time in the first processing time t1 so that the corresponding output port 03 and 04 can be processed at the same time, And the third ATM cell 3 is switched and output through the third output port 03 at the second processing time t2. If the fourth ATM cell 4 and the fifth ATM cell 5 are switched at the same time in the third processing time t3, they are sequentially transferred through the third output port 03 and the fourth output port 04 When the ATM cell processing rate of the switching unit 10 increases by about 50% compared with the arrival rate of the ATM cell through the first input port I1, The order of the ATM cells output through the third output port 03 and the fourth output port 04 will be 1, 2, 3,

As described above, in the conventional ATM exchange, excellent performance is ensured for traffic that instantaneously congests a channel group formed by a plurality of ports, but there is a problem that the order of input and output ATM cells is different when the processing speed of the ATM exchange is increased.

In order to solve the above problems, the present invention provides a high-performance ATM network in which, when providing a multi-port channel group in an ATM exchange having a higher processing speed than the input ATM cell, It is an object of the present invention to provide an ATM cell order assurance circuit of a channel group in an ATM exchange adapted to be suitable for an exchange.

According to another aspect of the present invention, there is provided an ATM switch comprising a plurality of input ports and a switching unit for forming a plurality of ATM cells through a plurality of input ports, An order controller for adjusting and outputting the order of the switched ATM cells applied from the switching unit according to the value of the decoded NOC; A counter unit for calculating the number of ATM cells applied from the sequence control unit and outputting a value of NOC; A plurality of buffers for temporarily storing the regulated ATM cells applied from the order controller and outputting the stored ATM cells to each output port; And a decoder for decoding the value of the NOC applied from the counter and outputting the decoded value of the NOC to the order controller.

FIG. 1 is a block diagram illustrating a configuration of a channel group in a conventional ATM switch; FIG.

FIG. 2 is a block diagram showing an example in which the ATM cell order is violated in FIG. 1; FIG.

FIG. 3 is a block diagram illustrating an ATM cell order guarantee circuit of a channel group in an ATM switch according to an embodiment of the present invention; FIG.

FIG. 4 is an exemplary view showing a configuration of a sequence control unit in FIG. 3; FIG.

FIG. 5 is an exemplary view of the order control of the ATM cell order in FIG. 3; FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

20: Switching unit 21:

22: Counter 23: Buffer

24: decoder

3, the ATM cell order assurance circuit of the channel group in the ATM switch according to the embodiment of the present invention includes a switching unit 20, a sequence control unit 21, a counter unit 22, Buffers 23, and a decoder 24.

The switching unit 20 forms an ATM cell input through a plurality of input ports I1 to I4 and switches according to the formed channel group.

The order control unit 21 adjusts the order of switched ATM cells applied from the switching unit 20 according to the value of the number of cells (NOC) decoded from the decoder 24 and applies the order.

The counter 22 calculates the number of ATM cells applied from the sequence controller 21 and temporarily stored in the buffer 23 and applies a value of NOC (Number Of Cells) to the decoder 24.

The buffer 23 temporarily stores the adjusted ATM cells applied from the sequence controller 21, and outputs the stored ATM cells to the output ports 01 to 04.

The decoder 24 decodes the value of the NOC applied from the counter 22 and applies the decoded value of the NOC to the order controller 21.

An operation for ensuring the order of ATM cells in a channel group in an ATM exchange according to an embodiment of the present invention will be described as follows.

As shown in FIG. 3, in a channel group formed of four input ports (C1 to C4), ATM cells switched in the switching unit 20 are first connected to four input ports (C1 to C4 To the sequence control unit 21 through the input / Here, the corresponding channel group is physically composed of four input ports (C1 to C4) as shown in FIG. 3, but up to four ATM cells can be logically input to the order controller 21 have. Accordingly, when one ATM cell is input to the order controller 21, the input is input through the first input port C1, and when two ATM cells are input, the second input port C2 is used.

The counter 22 counts the number of ATM cells output from the order controller 21 and stored in each buffer 23. For example, when one ATM cell is output from the order controller 21, When the value of NOC output from the counter 22 is 1 and three ATM cells are output, the value of NOC output from the counter 22 is 3.

The decoder 24 decodes the value of the NOC applied from the counter 22 and applies the decoded value of the NOC to the order controller 21. For example, if the value of the corresponding NOC is 0 The value of the decoded NOC is applied as '000', and if the value of the corresponding NOC is 1, the decoded NOC is applied as '001'.

The order control unit 21 determines the buffer 23 to adjust the order according to the value of the decoded NOC applied from the decoder 24. As shown in FIG. 4, the decoded NOC Since the previous ATM cell is stored in the first buffer 23-1 when the value is '001', the ATM cell input through the first input port C1 is stored in the second buffer 23-2 So that the order of the ATM cells is maintained. As shown in FIG. 5, when the decoded NOC value is '000', the two ATM cells input to the order controller 21 are connected to the first buffer 23-1 and the second buffer 23 -2, respectively. In order to sequentially store the three ATM cells input to the order controller 21 when the decoded NOC value is '010', the third buffer 23-3, 4 buffer 23-4 and the first buffer 23-1, respectively.

It is important to note that when all the ATM cells are output through the output ports 01 to 04 in the buffer 23, the value of NOC calculated in the counter 22 is set to 0, 1 buffer 23-1.

As shown in FIG. 3, when the order of the ATM cells is adjusted using the order controller 21, the order of the input and output ATM cells can be maintained equal to each other. That is, in the first processing time t1, the first ATM cell 1, the second ATM cell 2, and the third ATM cell 3 are connected to the first buffer 23-1, the second buffer 23-2, 3 buffer 23-3 and the counter 22 calculates the number of ATM cells and applies the value of NOC to the decoder 24 as '3', and the decoder 24 decodes the decoded NOC When the fourth ATM cell 4 and the fifth ATM cell 5 are applied through the switching unit 20 at the second processing time t2, The control unit 21 sequentially stores the fourth and fifth ATM cells 4 and 5 in the fourth buffer 23-4 and the first buffer 23-1. At this time, when the fourth ATM cell 4 is input to the fourth buffer 23-4, the counter 22 is cleared. When the fifth ATM cell 5 is input to the first buffer 23-1, The sixth ATM cell 6, the seventh ATM cell 7 and the eighth ATM cell 8 are connected to the second buffer 23-2 and the third buffer 23-2 at the processing time t3 of the next ATM cell, The buffer 23-3 and the fourth buffer 23-4, respectively.

The order of the ATM cells in the channel group can be guaranteed even when the processing speed of the ATM exchange is increased by performing the operation as described above. When the load of the switching unit 20 is 90 (%), It is possible to obtain the performance when the load of the switching unit 20 is 60 (%) while increasing the voltage of the switching unit 20 by 50 (%).

For example, in an ATM exchange, one cell may be input per 2.7 (μs) at an interface of 155 (Mbit / s). When the input load is 90 (%), nine cells do. However, if the processing speed of the ATM exchanger is increased by 50 (%) more than the input speed of the ATM cell, the processing time of one ATM cell is 2.7 / 1.5 and the maximum of 15 cells can be processed. Therefore, it can be seen that the actual load of the switching unit 20 is reduced to 9/15, that is, 60 (%), so that the probability of loss of the ATM cell due to the overload of the switching unit 20 can be reduced. Meanwhile, the above operation can be performed by assigning a new output port address to the ATM cell input to the order controller 21 using a general exchange. In the ATM cell input to the sequence controller 21, When assigning the address value, the value of the NOC is added and the corresponding value is switched. That is, the output port address values can be given as 1 and 2 to the two ATM cells shown in FIG. 5a, and the output port address values as 3, 4, and 1 to the three ATM cells shown in FIG. .

As described above, according to the present invention, even when the processing speed of the ATM exchange is increased by the present invention, it is checked how many ATM cells of the channel group are processed in the counter unit, and the number of processed ATM cells is decoded in the decoder, The order of the ATM cells in the channel group can be maintained by adjusting the positions of the cells.

Claims (1)

And a switching unit (20) for switching the ATM cells applied through the plurality of input ports (I1 to I4) according to the formed channel group and forming a channel group in the ATM cell order guaranteeing circuit of the channel group in the ATM switch An order controller 21 for adjusting and outputting the order of switched ATM cells applied from the switching unit 20 according to the value of the decoded NOC; A counter unit 22 for calculating the number of ATM cells applied from the sequence control unit 21 and outputting a value of NOC; A plurality of buffers 23 for temporarily storing the regulated ATM cells applied from the order controller 21 and outputting them to the output ports 01 to 04; And a decoder (24) for decoding the value of the NOC applied from the counter (22) and outputting the value of the decoded NOC to the order controller (21) ATM cell order guarantee circuit.