GB2306076A - ATM network switch - Google Patents

Abstract

An ATM network switch comprises a plurality of slot controllers, each having at least one external data link 3, 4 thereto, cell receiving means for receiving ATM cells from the data link and cell transmitting means for transmitting ATM cells outwardly on the data link, each slot controller being connected to a switch fabric comprising means for switching a cell input from one slot controller to a selected one of the other slot controllers for transmission on the external data link connected thereto, wherein each slot controller comprises cell buffering means 23 associated with the cell receiving means and/or the cell transmitting means, the cell buffering means comprising a FIFO 24 for each VC established on the switch, means 22 for determining the VCI for each new cell entering the buffering means and for storing the cell in the appropriate FIFO, and control means for outputting the cells sequentially from each FIFO in turn, the control means comprising an output arbitration FIFO 25, means for sequentially storing in the arbitration FIFO pointers indicating those VC FIFOs containing cells, and output means for reading the pointers and for causing a cell to be output from a respective VC FIFO according to the pointer read.

Description

ATM NETWORK SWITCH Field of the Invention This invention relates to an asynchronous transfer mode (ATM) network switch, and in particular to a switch having means for buffering the flow of ATM cells therethrough.

Background to the Invention In ATM data transmission, cells of data conventionally comprising 53 bytes (48 carrying data and the remainder defining the cell header, the address and re- lated information) pass over the network on a virtual connection at an agreed rate related to the available bandwidth and the level of service paid for. The agreed rate will relate not only to the steady average flow, but will also limit the peak flow rates.

Over an extensive network, cells on a connection can become bunched together, different cells having different delays imposed upon them at different stages, so that the cell flow on a VC then does not conform with the agreed rates.

To prevent rates being exceeded to the detriment of other VCs in the network, the network will include, for example at the boundary between different networks, means for policing the flow, typically including a "leaky bucket" device which will assess the peak and average flow rates of cells on a VC and either downgrade the cells' priority or discard cells. An example of such a device is disclosed in our UK Patent Application No 9505358.3.

At various stages in the network, buffering of cells is desirable or necessary to cnsure that cell rates do not exceed the capability of the network components concerned. In general, known buffering schemes do not take account of the variation in rates in different VCs, so that if one VC is predominant in the input, it will be equally predominant in the output from the buffer. It is desirable for the buffering scheme to operate in such a way as to even out the output across the various different VCs.

Summary of the Invention According to the invention, there is provided an ATM network switch comprising a plurality of slot controllers, each having at least one external data link thereto, cell receiving means for receiving ATM cells from the data link and cell transmitting means for transmitting ATM cells outwardly on the data link, each slot controller being connected to a switch fabric comprising means for switching a cell input from one slot controller to a selected one of the other slot controllers for transmission on the external data link connected thereto, wherein each slot controller comprises cell buffering means associated with the cell receiving means and/or the cell transmitting means, the cell buffering means comprising a FIFO for each VC established on the switch, means for determining the VCI for each new cell entering the buffering means and for storing the cell in the appropriate FIFO, and control means for outputting the cells sequentially from each FIFO in turn, the control means comprising an output arbitration FIFO, means for se- quentially storing in the arbitration FIFO pointers indicating those VC FIFOs containing cells, and output means for reading the pointers and for causing a cell to be output from a respective VC FIFO according to the pointer read.

In a preferred embodiment, the control means comprises means for deter- mining for each cell the priority level assigned thereto, and a separate arbitration FIFO for each priority level, and wherein the means for storing the pointers is arranged to enter each pointer in the arbitration FIFO assigned to the respective priority level and the output means is arranged to read the pointers from the highest available level of priority.

More preferably, timing means associated with each arbitration FIFO below the highest level are provided for causing the output means to read a pointer from the lower level arbitration FIFO after a predetermined interval, regardless of the state of the higher level arbitration FIFO.

The buffer means is suitably configured dynamically in Random Access Memory (RAM), so that the VC FIFOs are set up as new VCs are set up.

The cell buffering means is suitably used to buffer the flow of cells entering the slot controller, but it can also be used on the output from the slot controller when no traffic shaping is required, for example for CBR Constant Bit Rate) traf- fic. Alternatively, the buffering means can be used in conjunction with traffic shaping, for example as disclosed and claimed in our earlier application No 9509483.5, with shaping being determined for an individual connection, with the pointer for the cell being written to a shaping FIFO instead of to the arbitration FIFO. The arbitration process would then consider the shaping FIFO effectively as a different level of priority, for example just below level 0, the highest priority level.

Brief Description of the Drawings In the drawings, which illustrate diagrammatically aspects of ATM network switches according to alternative exemplary embodiments of the invention: Figure 1 is a representation of an ATM switch in accordance with the invention; Figure 2 is a more detailed representation of one of the slot controllers of the switch shown in Figure 1; Figure 3 is a more detailed representation of a cell ingress side buffering system within the slot controller shown in Figure 2; and Figure 4 is a representation corresponding to that of Figure 3, but showing the buffering system for the egress side of the switch.

Detailed Description of the Illustrated Embodiments Referring first to Figure 1, the ATM network switch consists of a plurality of slot controllers 2; in the simple arrangement illustrated eight slot controllers are shown, but a typical switch might have 16 slot controllers. Each slot controller 2 has external input/output links 3. The switch has a pair of switch fabrics 1 of a dynamic crosspoint type and each having input and output connections 4 and 5 re- spectively to each of the slot controllers 2. The two switch fabrics may be operated in such a manner as to double the bandwidth of the switch or to provide an imme- diate alternative path should any particular path through one switch fabric fail.

This type of arrangement is described in more detail in our earlier application GB9507454.8. The structure of the slot controllers is, for example, of the general type described and claimed in our earlier application GB9505358.3, and ATM cells arriving on an input link 3 may be processed in the general manner described in that application.

Figure 2 shows the structure of a slot controller 2 in more detail. For simplicity of illustration, the connections to only one of the switch fabrics are shown.

The slot controller 2 comprises an output cell processor 21, whose structure will not be described further since it has no bearing on the present invention. The output cell processor 21 is connected to the external link 3 and to the output connection 5 from the switch fabric 1. It will be appreciated that the output cell processor principally handles functions such as the writing to the cell headers of the new VPI/VCI information, and output to the external data link 3. Data input on the external data link 3 is received by the input cell processor 22, which passes the cells to, and receives cells from, the buffering system 23, described hereinafter in more detail with reference to Figure 3.The cells are passed in sequence from the buffering system 23 via the input cell processor to the switching fabric 1 (Figure 1) on the input connection 4, to be switched to the appropriate destination slot controller.

Referring now to Figure 3, the buffering system 23 on the ingress side of the slot controller comprises a plurality of FIFOs 24, for example up to 64K FIFOs, configured dynamically in RAM according to the establishment of VCs through the switch. For convenience of illustration, only four of the FIFOs are shown in the Figure. Each of the FIFOs 24 is configured dynamically according to the number of cells to be stored at any time on a particular VC. Since it is possible to con- figure VCs to use a particular switch fabric in a dual switch fabric switch, each VC will be configured to one or other of the switch fabrics.

A second set of FIFOs, the arbitration FIFOs 25, is also provided. These may also be configured in a separate part of the same RAM, or in a separate RAM, if desired. The arbitration FIFOs are divided into two groups of four 25a and 25b, with one group for use with each of the two switch fabrics used in the switch as disclosed in our earlier UK Patent Application No 9507454.8. In Figure 3, each group consists of four arbitration FIFOs 25, one for each of the four classes or priority levels of ATM traffic typically provided for. It will be understood, however, that more or fewer arbitration FIFOs may be provided in each group according to the priority requirements of the network, and that, where the switch only has a single switch fabric, only one group of arbitration FIFOs may be required.

A further set of four FIFOs 26 is provided to handle the OAM (Operations And Maintenance) cells, which the input cell processor identifies from the cell headers and separates out from the data cells for handling by an OAM processor (not shown). Four FIFOs 26 are shown, to handle the four different traffic classes present in the illustrated embodiment. Again, more or fewer traffic classes will change the number of FIFOs required.

In use, the input cell processor 22 of the slot controller receives an incoming cell and determines its VCI and priority level from the cell header information (it will be appreciated that the cell processor also performs other functions to process the cell, but these are not described here as they do not affect the operation of the present invention). The processor 22 then checks the switch fabric (SF) paths through the two SFs for the particular VC. If both are broken, the cell is discarded at that point. If at least one of the paths is available, the processor 22 routes the cell to the "bottom" or input end of the appropriate VC FIFO 24, and at the same time increments a stored cell count for the individual VC FIFO.If the stored count was previously 0, a pointer is written to the "bottom" or input end of the appropriate arbitration FIFO 25, according to the cell priority and switch fabric used.

For output, the arbitration FIFOs are considered according to the priority level. Subject to a timing system described hereinafter, the level 0 or highest prior- ity FIFO is always considered first, and only when there is nothing at this priority level will the lower priority levels be considered, the lower levels being considered in the same way so that only when all higher priority levels are empty will the level 3 FIFO be considered. Taking the case where the priority level 0 FIFO is not empty, a pointer is read from the "top" or output end of the FIFO. This pointer indicates the next VC FIFO to send a cell, and a signal is sent to that FIFO to output the next ATM cell to the processor 22 for onward routing via the switch fabric.At the same time, the cell count for that particular VC is decremented in the cell processor 22, and, if the count is not 0, the pointer is re-entered into the "bottom" of the FIFO. Thus, there is only one pointer entry for any of the VCs in any of the arbitration FIFOs at any given time, and no pointer entry if the VC FIFO is empty. The cells are thus output from the VC FIFOs in turn, subject to the cell priority level, providing a "fair" allocation of the output bandwidth amongst the various VCs.

If the desired SF path is broken when the cell is to be sent, but the alternative path is available, the cell is not sent, and the pointer is entered instead at the bottom of the arbitration or output FIFO 25 for the alternative SF.

Entries in the output FIFOs 25 consist not only of the pointer to the VC FIFO, but also the output port number. The switch fabric preference and the priority bit are stored in the VC FIFO, so that these are available if the pointer has been transferred to the alternative SF output FIFO 25.

With the system described, it is possible that lower priority cells would wait an excessively long time in the VC FIFOs if there were a higher loading of higher priority cells. To overcome this potential difficulty, a timer may be associated with each of the arbitration FIFOs at priority levels 1, 2 and 3, arranged to output a time-out signal after a predetermined time period from the last output of a pointer from the respective arbitration FIFO 25. On receipt of the time-out signal, the priority given to the higher levels is temporarily over-ridden, permitting a pointer from the lower level FIFO 25 to be output, the respective timer then being reset.

It is possible with the system described to encounter "head-of-line" blocking, where one or more ports are full up (blocked), and so cells cannot be sent to the SF. To overcome this problem, yet another FIFO may be provided for the blocked outputs. The appropriate pointers are moved from the output FIFO 25 to the blocked output FIFO, which is given top priority for outputting cells from the VC FIFOs. Since it is possible then for several pointers to be present in the blocked output FIFO, a situation can arise where continued blockage of some ports would prevent cells being sent to other previously-blocked ports which subsequently become available.To overcome this problem, the pointers in this FIFO do not remain fixed, but are considered once per cell time, and if the pointer at the top of the FIFO relates to a VC for which the port is still blocked, so that the cell cannot be sent, the pointer is re-entered at the bottom of the FIFO so that the next pointer is considered in turn at the next cell time. There will need to be one blocked output FIFO for each output FIFO 25.

Figure 4 shows the alternative arrangement of output FIFOs on the egress side of the switch. The general arrangement of components is the same as for the ingress side illustrated in Figure 3, but for each class of traffic and each external data link on the slot controller, a separate output FIFO 40 is provided. In addition, traffic shaping FIFOs 41 are also provided, containing pointers whose address in the FIFO corresponds to the time at which the relevant cell, stored in the VC FIFO, is to be sent. Thus, the system is equivalent to that described in our earlier UK Patent Application No 9508225.1, but it is the pointer to the VC FIFO ad- dress where the cell is stored, rather than the cell itself which is stored in the traffic shaping FIFO at the onward transmission time. According to the type of VC, the pointer is written either to the appropriate traffic shaping FIFO 41 or to the appropriate output FIFO 40.

In the case of the per link output FIFOs 40, the link FIFOs of the same priority are considered sequentially, with each successive pointer for the particular priority level being read from the next link FIFO in the series.

Claims (5)

1. An ATM network switch comprising a plurality of slot controllers, each having at least one external data link thereto, cell receiving means for receiving ATM cells from the data link and cell transmitting means for transmitting ATM cells outwardly on the data link, each slot controller being connected to a switch fabric comprising means for switching a cell input from one slot controller to a selected one of the other slot controllers for transmission on the external data link connected thereto, wherein each slot controller comprises cell buffering means associated with the cell receiving means and/or the cell transmitting means, the cell buffering means comprising a FIFO for each VC established on the switch, means for determining the VCI for each new cell entering the buffering means and for storing the cell in the appropriate FIFO, and control means for outputting the cells sequentially from each FIFO in turn, the control means comprising an output arbitration FIFO, means for sequentially storing in the arbitration FIFO pointers indicating those VC FIFOs containing cells, and output means for reading the pointers and for causing a cell to be output from a respective VC FIFO according to the pointer read.

2. An ATM network switch according to Claim 1, wherein the control means comprises means for determining for each cell the priority level assigned thereto, and a separate arbitration FIFO for each priority level, and wherein the means for storing the pointers is arranged to enter each pointer in the arbitration FIFO assigned to the respective priority level and the output means is arranged to read the pointers from the highest available level of priority.

3. An ATM network switch according to Claim 2, wherein timing means associated with each arbitration FIFO below the highest level are provided for causing the output means to read a pointer from the lower level arbitration FIFO after a predetermined interval, regardless of the state of the higher level arbi- tration FIFO.

4. A switch according to Claim 1, 2 or 3, wherein each VC FIFO is configured dynamically in Random Access Memory (RAM) as a new VC is set up.

5. An ATM network switch, substantially as described with reference to the drawings.