KR970002817B1 - Link sharing control unit by vp in atm network - Google Patents

Abstract

The link sharing control device by a virtual path in an ATM(Asynchronous Transfer Mode) network comprises: a link matching part(210) checking a corresponding virtual path whenever a cell reaches a switch; an address storing part(220) for storing an address value of the cell; a common memory(240); an address state controller(230) for controlling an address state of the common memory(240); a link control part(260) for reading the corresponding cell to transmit the read cell to an output link group and for updating the address state controller(230); a controller(250) for controlling the link matching part(210), the common memory(240), the address storing part(220) and the link control part(260).

Description

Link sharing control device by virtual path in ATM network

1 is a basic conceptual diagram of link sharing control according to the present invention.

2 is a block diagram of a link sharing control device according to the present invention;

* Explanation of symbols for main parts of the drawings

210: link matching device 220: address storage unit

230: address status controller 240: common memory

250: control unit 260: link control device

221: address buffer 222: controller

The present invention relates to an apparatus for controlling link sharing by a virtual path in an ATM network to improve cell efficiency while satisfying a cell loss rate in an ATM network based on a virtual path (VP).

In general, since the ATM network transmits all user information in a unified format called a cell, it can provide a variety of services and has the advantage of facilitating the introduction of new services. In addition, it is possible to transmit services from low speed to high speed through simple protocol and high speed switching, and improve network efficiency by performing statistical multiplexing.

In addition, in the ATM network, in order to simplify control of resource management, a concept of a virtual path (hereinafter referred to as VP) has been proposed. This virtual path method simplifies network resource management by reducing processing functions and processing load in intermediate nodes. If a VP is established between end-to-end nodes, all virtual channels (hereinafter referred to as VCs) within that VP can be multiplexed and routed on the same predefined virtual link. Thus, intermediate nodes do not require call setup or routing procedures for individual VCs. This simply reduces the call processing procedure through the network. VP technology also increases network reliability through dynamic network reconfiguration.

However, one of the output links of the ATM network has too many cells to transmit, causing cell loss. On some other output links, there are no cells to transmit, so the link can be idle, and each VP is in the link. In the present invention, the quality of service (hereinafter, referred to as QoS) of each VP may be affected by other VPs because they are logically allocated rather than physically divided.

In addition, the use of VP can reduce the number of VC multiplexed on one link, and even if the control of each VP is well controlled, the network efficiency cannot be sufficiently improved if the control of the physical link is not performed well. There was this.

Therefore, the present invention devised to solve the problems of the prior art, the link is connected to the same switch of the next node among the output links of the switch so that the output link without the cell to be transmitted can be used to transmit the cells of the other link. Link sharing is defined as a link group, and a link is shared by a virtual path in an ATM network so that a link can be shared within the same link group so that a cell of another link can be transmitted when there is no cell to be transmitted on one link. The object is to provide a control device.

In order to achieve the above object, the present invention provides a link matching device for examining a corresponding VP every time a cell arrives at a switch from an input link group, an address storage unit connected to the link matching device and storing an address value of the cell; A common memory for storing the cells arriving at the link matching device at an address position by the address storage unit, an address state controller connected to the link matching device to control an address state of the common memory, and an address of the address storage unit; A link control device which reads the corresponding cell in the common memory according to the value, transmits it to the output link group, and updates the address state controller, and a control unit which controls the link matching device, the common memory, the address storage unit and the link control device. Characterized in that.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 illustrates a basic conceptual diagram of link sharing control according to the present invention.

As shown in the figure, in the present invention, in order to control sharing of links, links that can be shared with each other should be grouped into a group. That is, a link group is defined as a set of links in which the output link of one switch is connected to the same switch of the next node. Therefore, links can only be shared within the same link group.

In the overall cell transmission flow, cells coming through an input link are stored in the VP's First-In First-Out (FIFO) queue. However, it is assumed that the switch operates on a VP basis and each VP satisfies an independent subtraction. In each slot, each output link transmits one cell at a constant rate according to the bands of VPs included in its link. Each output link checks whether there is a cell to transmit in every slot, and if there is no cell to transmit, transmits a cell belonging to another link of the same link group.

That is, suppose output link 1,2,3 belongs to the same link group, VP number 1,2,3 are virtual paths belonging to output link 1, and VP number 4,5,6 is output link 2 For example, assume that VP numbers 7,8, and 9 belong to output link 3. If there is no cell to transmit in the buffer of all VPs (VP Nos. 4, 5 and 6) belonging to link 2 in any arbitrary slot, select the longest buffer in the other link (1, 3) of link group 1 Transmit the cell in that buffer to link # 2. This sharing of links allows for more efficient use of network resources.

2 is a block diagram of a structure of a link sharing control apparatus according to the present invention. As shown in the figure, the present invention provides a link matching device 210 that checks a corresponding VP every time a cell arrives at a switch from a link group, and is connected to the link matching device 210 to store an address value of the cell. An address storage unit 220, a common memory 240 connected to the link matching device 210 to store a cell, and a link memory 210 connected to the link matching device 210 to control an address state of the common memory 240. The link control device 260 reads the corresponding cell in the common memory 240 by the address state controller 230 and the address storage unit 220, transmits the corresponding cell to the output link group, and updates the address state controller 230. And a control unit 250 for controlling the link matching device 210, the common memory 240, the address storage unit 220, and the link control unit 60, wherein the address storage unit 220 includes a plurality of addresses. For virtual paths (VP1 to VPn) of A plurality of address buffers 221 and a plurality of controllers 222 for controlling the respective address buffers 221 are provided.

The link sharing control apparatus of the present invention configured as described above configures a buffer as a random access common memory to facilitate QoS control of each VP. The cell entering the switch is stored in the common memory 240. The common memory 240 is not a FIFO queue but a structure of random write / random read (RW / RR), and has an idle address for cell storage. Action is required.

The address state controller 230 controls the state of each address of the common memory 240 to indicate whether the corresponding address is busy or idle. Therefore, each time a cell arrives at the switch, the cell is examined at which VP at link matching device 210. Then, the link matching device 210 finds an idle address of the common memory 240 through the investigation of the address state controller 230. If there is no idle address, the common memory 240 is full and a buffer overflow occurs and the cell is lost. If the link matching device 210 obtains an idle address, the cell is stored in the common memory 240 of the address, and the address value is stored in the address buffer 221 of the corresponding VP. The corresponding bit of the address state controller 230 is updated to a busy state. Here, the size of each address buffer 221 is determined in the VP setting step according to the QoS requirement of the VP and the allocated band.

The procedure for transmitting a cell in the common memory 240 to an output link group is as follows. In order to achieve fairness of each VP, a cell read operation of each VP is performed according to the band allocated in the VP setup step. Fairness can be maintained by transmitting VP cells in a kind of round-robin manner. In addition to using round robin, timer logic is used to implement traffic shaping. In addition, the controller 222 that controls the address buffer 221 has a timer logic that is incremented by one by its timer clock, the period of the timer clock is determined by the VP band. If the timer value is greater than 0 and the buffer is not empty, the controller 222 sends a transmission request signal including the timer value to the controller 250. Then, in each link slot, the controller 250 grants a transmission right to the cell of the VP having the highest timer value.

If there are no cells in all VP buffers belonging to one output link, then the transmission right is given to the longest among VPs belonging to other links in the same link group. When the controller 222 receives the transmission right signal from the controller 250, the controller 222 sends the cell address to the link controller 260 and resets the timer value to zero. Then, the link control device 260 reads and transmits the corresponding cell in the common memory 240, and updates the address status bit of the address state controller 230 to an idle state (updata).

In addition, when transmitting a cell belonging to another link in the same link group because there is no cell to transmit on one link, it is important to keep the cell sequence, so the delay margin reaching the switch buffer of the next node should be considered. . Therefore, the delay margin is considered by preventing the cells of the same VP from being transmitted continuously on different links in the same slot. That is, when a cell on another link is selected and transmitted, the cell that is not transmitted in the slot is selected and the cell having the largest queue is transmitted.

As described above, according to the present invention, the VP concept is introduced to simplify network operation, improve network reliability, and to improve buffer efficiency with a common memory structure, and to temporarily prevent congestion using traffic shaping technology. It can absorb and maximize the utilization efficiency of entire network resources through link sharing between link groups.

Claims (5)

Link matching device 210 that checks the virtual path (hereinafter referred to as VP) whenever a cell arrives at the switch from an input link group, and an address connected to the link matching device 210 to store the address value of the cell. The storage unit 220 and the cell that arrive at the link matching device 2100 are connected to the common memory 240 and the link matching device 210 which are stored at an address position by the address storage unit 220. The address state controller 230 controlling the address state of the common memory 240 and the corresponding cell in the common memory 240 are read and transmitted to the output link group according to the address value of the address storage unit 220. The link control device 260 for updating the state controller 230, the control unit 250 for controlling the link matching device 210, the common memory 240, the address storage unit 220, and the link control device 260. Having In ATM networks as Gong link shared control apparatus according to the virtual path. The address storage unit 220 of claim 1, wherein the address storage unit 220 includes a plurality of address buffers 22l having a first-in first-out (FIFO) queue structure corresponding to a plurality of VPs (VP1 to VPn). Link sharing control device according to the most path in the ATM network, characterized in that it comprises a plurality of controllers (222) for controlling each address buffer (221). 3. The controller 222 of claim 2, wherein the controller 222 has a timer value equal to or greater than zero and the address buffer 221 is empty by a timer logic in which the timer value is increased by one according to the timer clock whose period is determined by the VP band. Otherwise, the link sharing control device according to the most path in the ATM network, characterized in that configured to send a cell transmission request signal including a timer value to the control unit (250). The random memory of claim 1, wherein the common memory 240 is configured as a random access common memory (RW / RR) to facilitate Quality of Service (QoS) control of each VP. Link sharing control device by the most path in the ATM network, characterized in that the structure of). The ATM of claim 1, wherein the controller 250 is configured to give a transmission right to a cell of a VP having the highest timer value for each link when receiving the cell transmission request signal from the controller 22. Link sharing control device by path in network.