GB2337407A - Data switch - Google Patents

Abstract

Multiple similar elements in a data switch, for example input or output ports 20a,b,c,d, are operated synchronously (even for essentially asynchronous data) at staggered timings. The staggering of the timings allows the number of control signals acquired to be reduced, as the elements can be identified to some extent from the time at which they are active. In a similar manner, signalling information such as buffer occupancy may be communicated using the timing of signalling to identify different elements.

Description

2337407 Data Switch The present invention relates to data switches,

particularly for switching data packets or cells, and in a preferred embodiment relates to an ATM switch.

In a data switch such as an ATM switch, there are typically a plurality of input/output interfaces (herein termed "slots") which receive ATM cells from external ports, pre-process the cells and feed the cells to a central switch fabric. The switch fabric routes cells from an input to an output, and the input/output interfaces accept returned cells from the switch fabric, post-process the cells, and feed them to the output ports.

Particularly where a large number of inputs and outputs are provided, the switch fabric itself may comprise a plurality of switching elements, each switching element typically receiving inputs from each input port and feeding at least one output port.

In order to transfer data correctly through the switch, it is necessary for both the source and destination of a data packet, or the input and output port, to be uniquely identified to the switch fabric. In addition to data to be switched, it may be necessary for each switching element to communicate other control information, for example an indication of buffer occupancy or availability to accept data, with each input/ output interface.

Since the number of switching elements may be generally proportional to the number of inputs or outputs, it can be seen that the number of communication channels increases approximately in proportion to the square of the number of inputs or outputs. To give a practical example, in a switch having provision for 16 inputs and outputs in which the switch fabric comprises 16 switching elements, each of which is required to comrnunicate with each inputloutput interface, there are 256 possible permutations, and separate channels may be required for data packets and control information. Moreover, it may be necessary for at least some of the switching elements to communicate with others. Thus it can be seen that the number of communication channels 2 required can rapidly become very large as the size of the switch increases.

Another consideration is that a data switch is usually required to process data packets at a high throughput rate, which makes it desirable for communication to occur along different channels effectively concurrently. Furthermore, each channel, particularly those which transfer data to be switched through the cell, should ideally be wide parallel channels (for example at least 8 bits, preferably 16 or more) to improve data transfer rates, rather than serial channels. These requirements suggest the use of individual dedicated parallel data transfer channels for each possible communication path; however, such an arrangement may require more physical connections than can conveniently be accomodated, particularly where a modular assembly is preferred.

Another problem with providing multiple communication channels is that, particularly in a switch for switching data which is inherently asynchronous or unpredictable, a single component (for example an input interface or a switching element) may simultaneously receive data transfer requests from multiple communication channels, and servicing all of these may be problematic; complex arbitration may be required, or each component may require extra hardware to cope with such cases, this hardware being redundant for much of the time in operation.

A further consideration is that each input or output may require processing capability, for example to perform cell header translation or look-up, as well as other functions required to route cells through the switch, so the (often complex) hardware required must be replicated for each input or output.

All of these problems can increase the cost and complexity of a data switch dramatically as the number of input/output interfaces and throughput requirements increase. In addition, testing such a switch can be complex and time-consuming, and reliability may be adversely affected.

The inventor has proposed an elegant solution which can be employed in a number of ways 3 within a data switch to alleviate some or all of the above drawbacks. At least in preferred embodiments, hardware complexity may be reduced and testing may be facilitated without compromising switch performance; indeed, switch performance may be enhanced.

In a first method aspect the invention provides a method of transferring data to or from at least one of a plurality of similar elements in a data switch or processing data associated with said at least one element, the method comprising: supplying at least one synchronisation signal defining a reference timing; assigning a respective time window to each of said similar elements with respect to the reference timing, the time window differing between the similar elements; and transferring data to or from said at least one element or processing data during the time window assigned to said at least one element.

In this specification, unless otherwise stated, references to transferring data are intended to encompass simple signalling, that is the transfer of a single bit of information, for example by the sending of a single control pulse, in addition to transfer of substantial packets of data. The data may comprise data to be routed by the data switch, or control information generated within the switch, or both.

In this way, the elements may be distinguished, at least partially (it is to be noted that the time windows need not be unique; certain elements may share a time window, with further means being provided to distinguish between the elements), based on the timing at which data is transferred or a signal is sent, thereby reducing the need for signalling control signals. Alternatively or additionally, processing or other hardware resources may be shared between the elements. Moreover, because differing time windows are assigned to different elements, conflict between elements may be reduced. This synchronous architecture can provide advantages even in an environment where the data, for example ATM cells, is inherently unpredictable.

In a first apparatus aspect, the invention provides a data switch having a plurality of similar 1 4 elements therein, the data switch further including:

means for supplying at least one synchronisation signal defining a reference timing; means for assigning a respective time window to each of said similar elements with respect to the reference timing, the time window differing between the similar elements; and means for transferring data to or from at least one of said similar elements or processing data during the time window assigned to said at least one element.

The time windows may be assigned by supplying to each element an element synchronisation signal delayed by a predetermined amount with respect to a reference synchronisation signal defining the reference timing. This has the advantage that the time window can be automatically assigned simply by supplying a single signal, and this can be implemented in hardware. In particular, where the elements are located at different physical locations within a data switch, different synchronisation signals can be provided at different locations so that time windows are automatically assigned; this enables elements to be interchanged readily with minimal re configuration necessary.

In a related but independent second apparatus aspect, the invention provides a data switch having a plurality of sockets (which term is intended to encompass any connector or mounting point irrespective of physical configuration) for receiving a respective plurality of similar elements and means for supplying at least one synchronisation signal to each socket, the timings of the synchronisation signals differing between at least two of the sockets, whereby similar elements mounted in said at least two sockets can be distinguished based on the timing of said at least one synchronisation signal supplied to the socket.

Alternatively, the time windows may be assigned by configuring each element to operate at a different timing with respect to a common synchronisation signal; this may have the advantage that elements may be more flexibly configured, for example to enable optimisation of a data switch for different numbers of inputs and outputs or data packet sizes. Configuration may be by means of physical setting of control inputs (hard configuration) or by programming (soft configuration) or by a combination of hardware and software configuration.

Most preferably, the method is applied to transferring data packets of a known, preferably fixed, preferably relatively short length. Particularly preferred applications include transfer of ATM cells (optionally packaged, i.e. including an additional header), or signalling information in a predetermined frame format; in such cases, the time windows can be selected to be appropriate to the time required to transfer data between points in the switch.

In one application of the invention, the similar elements may comprise input/output interfaces (which term is intended to encompass interfaces providing input or output, preferably both, between a switch fabric and an external connection). In such a case, the invention may provide an efficient arrangement for effecting transfer or processing of data packets to be routed through the switch.

In one embodiment of this particular application, the invention may provide, in a second, independent, method aspect, a method of transferring data between one of a plurality of input/output interfaces and a switch fabric coupled to receive data from a plurality of said input/output interfaces, the method comprising: providing at least one synchronisation signal to the switch fabric and the input/output interfaces and transferring data or making data available from each individual input/output interface at a respective predetermined timing with respect to the synchronisation signal, the predetermined timing differing between the input/output interfaces.

The invention also provides a corresponding third apparatus aspect in which the invention provides a data switch comprising: a switch fabric; a plurality of input/output interfaces; means for supplying at least one synchronisation signal to the switch fabric and the 6 input/output interfaces; wherein the input/output interfaces are each arranged to make data available for transfer or to transfer data to the switch fabric at a respective predetermined timing with respect to the synchronisation signal, the timing differing between inputloutput interfaces.

In this embodiment, the switch fabric may be arranged to distinguish between input/output interfaces, for example to determine the input/output interface from which data originated based on the timing at which data is transferred or made available. This may be used to facilitate signalling between interfaces and the switch fabric, or within the switch fabric, or both. In particular, communication between switching elements of the switch fabric may be simplified; to identify a particular input or output, it is not necessary for one switching element to communicate a complete identifier of the input or output port concerned, since the active time window allows the input or output port to be determined. This may be particularly advantageous in a master/slave arrangement in which a data packet is handled by more than one switching element, for example as described in our concurrently filed application bearing the reference PMEK-120138, the disclosure of which is incorporated herein by reference.

Preferably, each inputloutput interface is allocated an active time period in sequence. Preferably, the switch fabric is provided with a clock signal and a synchronisation signal whereby input/output interfaces can be identified based on the number of elapsed clock cycles between the synchronisation signal and a control signal provided by the input/output interface.

Preferably each element or input/output interface is supplied with a synchronisation signal at a predetermined offset with respect to a reference synchronisation signal, preferably an integral number of clock cycles, the switch preferably comprising means (for example a delay chain) for deriving a plurality of synchronisation signals from a master synchronisation signal. The signals supplied to each element preferably differ between physical locations within the switch. In this way, it may not be necessary to configure the input/output interfaces, but the physical location of the input/output interface in the switch may determine the identity of the interface; another 7 advantage is that interface cards may be readily interchanged.

Each interface may handle a plurality of physical ports; in such a case, it is preferable for the interface to provide information identifying the physical port; this may be achieved by further signal connections, by flu-ther variation of the timing at which data is transferred, or most preferably by including identification bits in a header appended to data cells. In the case of an interface having an input function, the header is preferably added by the interface to incoming data cells.

The method may include processing data from each successive input/output interface sequentially, preferably using at least one common processing element. In this way, processing resources on the switch fabric may be shared between input/output interfaces or the total processing activity made more regular, which may in some cases result in more uniform power requirements, or a saving in hardware.

In a second embodiment of this application, which may be provided independently or in conjuction with the first embodiment, the invention may provide in a third method aspect a method of processing, in a data switch, data from one of a plurality of input/output interfaces in a processing element, preferably associated with a switch fabric coupled to receive data from a plurality of said input/output interfaces, the method comprising: providing at least one synchronisation signal, preferably to at least the switch fabric and processing data from each individual input/output interface at a respective predetermined timing with respect to the synchronisation signal, the predetem-iined timing differing between the input/output interfaces.

The processing element may be an integral part of the switch fabric, or may be a distinct component. Preferably the processing element performs a similar processing function for a plurality of input/output interfaces.

8 In a preferred arrangement, which may be provided independently in a fourth method aspect, the method includes receiving a first data packet via a first input, processing at least a portion of the data packet with a processing element, receiving a second data packet data via a second input and processing at least a portion of the second data packet with said processing element. Preferably said portion of each data packet comprises at least a portion of a header associated with each packet.

A related fourth apparatus aspect provides a data switch comprising: a plurality of input/output interfaces; means for providing at least one synchronisation signal; means for processing, preferably in a switch fabric coupled to receive data from a plurality of said input/output interfaces, data from each individual input/output interface at a respective predetermined timing with respect to the synchronisation signal, the predetermined timing differing between the input/output interfaces.

In a development, which may be provided independently, processing comprises mapping a logical destination of a data packet to a physical destination. An advantage of providing logical to physical mapping is that the system can readily be re-configured in the event of failure of a physical port to direct data traffic to another port (which may be externally routable to the same destination). A particular advantage of having this logical to physical translation performed by a common element is that a common look-up table can be employed, and any update to the common look-up table wiiI be effective for all inputloutput interfaces served by the processing element without delay.

In an independent fifth method aspect, the invention provides a method of routing data packets though a data switch having at least one input port, and a plurality of output ports, the method comprising:

associating a respective logical identifier with each of said output ports; receiving a data packet including routing information; 9 processing the routing information to determine at least one destination output port to which the packet should be routed and associating a logical identifier of said at least one destination output port with the data packet; routing the data packet to said at least one destination output port based on the logical 5 identifier.

With this aspect, it is simply necessary to alter the association between a single logical identifier and the corresponding output port in order to re-direct all packets destined for that output port to another port. This may be much faster than re-configuring the processing of routing information 10 included in the incoming data packets.

The invention also provides, in a fifth apparatus aspect, a data switch comprising: at least one input port; a plurality of output ports; means for assigning respective logical addresses to output ports of the switch; means for receiving a data packet containing routing information from said at least one input and associating with the packet a logical address corresponding to a destination output port based on the routing information; and means for routing the packet to the destination output port based on the logical address.

In a preferred application, said routing information includes a path identifer, for example a virtual path identifier and/or a virtual channel identifier, and preferably packets bearing more than one of said path identifiers may be destined for a single output port.

Preferably, in response to a predetermined condition (such as failure of an output port), a logical address is re-assigned to a different output port.

Reverting to the first aspect, the data to be transferred may be data for signalling a measure of buffer occupancy of switching elements within the switch elements of a switch fabric and preferably combined into a composite data stream. In a prefered implementation, the switch elements are connected in serial fashion to output a serial data stream, the time window assigned to each switch element being based on the position in the serial connection.

In a sixth method aspect in which the invention provides a method of providing a measure of buffer occupancy of a plurality of switch elements in a data switch, the method comprising: providing at least one synchronisation signal; outputting from each switch element data pertaining to a measure of buffer occupancy of the switch element; and combining the output data from each switch element to generate a composite output serial data stream containing data pertaining to a measure of buffer occupancy of each switch element, the data from each switch element being output at a respective predetermined time with respect to the synchronisation signal.

The invention also provides, in a corresponding sixth apparatus aspect, a data switch having a plurality of switch elements and including means for providing a measure of buffer occupancy of said plurality of switch elements, the data switch comprising: means for providing at least one synchronisation signal; means for outputting from each switch element data pertaining to a measure of buffer occupancy of the switch element; and means for combining the output data from each switch element togenerate a composite output serial data stream containing data pertaining to a measure of buffer occupancy of each switch element, the data from each switch element being output at a respective predetermined time with respect to the synchronisation signal.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which:

Fig. 1 is a simplified schematic diagram of an ATM switch in which data is transferred 11 between slot controllers and a switch fabric in accordance with a first embodiment of the invention; Fig. 2 is a timing diagram for explaining the operation of the embodiment of Fig. 1; Fig. 3 is a schematic diagram showing the configuration of the switch fabric of the first embodiment in more detail; Fig. 4a is a simplified schematic diagram of an ATM switch in which data is processed in accordance with a second embodiment of the invention; Fig. 4b is a schematic diagram of flow of a data packet in the embodiment of Fig. 4a; Fig. 5 is a schematic diagram of apparatus for performing logical to physical mapping of output port addresses; Fig. 6 is a simplified schematic diagram of an ATM switch in which an indication of buffer occupancy is output by switching elements of a switch fabric in accordance with a third embodiment of the invention; Fig. 7 is a timing diagram for explaining the operation of the third embodiment; In the following description, for ease of understanding of the invention, simplified switch architecture will be described. It will be appreciated that a fimctional switch includes other elements; however, since the details of these may be conventional and are not germane to the invention, they will not be described in detail. Reference may be made to our co-pending applications filed concurrently herewith bearing references PDG/W20137, 20138,20139,2024 6 and 20247, the disclosures of which are incorporated herein by reference, where advantageous implementations of certain features of a data switch are disclosed. Reference may also be made to the ATM forum LTNI 3.0 specification, the content of which is incorporated herein by reference.

Referring to Figure 1, an ATM switch includes a switch fabric 10 coupled to slot controllers 20a,20b,20c,20d. In this embodiment, four slot controllers are provided, but more or fewer may be provided; a typical switch may have sixteen slot controllers. The slot controllers are input/output interfaces which include physical input and output ports and cell processing 12 apparatus including apparatus for performing routing and policing and the like functions. The details of the implementation of these functions are not germane, and may be entirely conventional, or may, advantageously, be as described in our above referenced applications.

A clock signal, for example generated from a SONfEIz crystal controlled oscillator, is supplied to each slot controller and to the switch fabric. In addition, the clock signal is supplied to a synchronisation pulse generator 22, which generates an output signal SlotO,Master which is high for one clock cycle every 4 cycles; this may be implemented readily using a counter. This signal is supplied to SlotO controller 20a and also to the switch fabric 10 to provide a master synchronisation signal. The master synchronisation signal is fed to a chain of delays 24a,24b,24c (which may be implemented by D-type latches), each of which delay the input by one clock cycle, to produce respective output signals Slotl, Slot2, Slot3 which are supplied to the respective Slot controllers. As an alternative, a shift register may be employed to produce appropriately staggered synchronisation pulses.

Each slot controller has an output to signal that data is available for transfer, and the outputs of each slot controller are connected to an associated Data Available input of the switch fabric. As an alternative to the arrangement shown in Fig. 1, the Data Available outputs of the slot controllers could be connected to a common input. In such a case the individual signals can be distinguished within the switch fabric by logic which sets an active slot counter to SlotO on receipt of the Master signal, and then increments the active slot counter every subsequent clock cycle.

In this, preferred, arrangement, each slot controller has a dedicated data path to the switch fabric, 25 preferably at least 8 bits, more preferably 16 or more bits wide (not shown in Fig. 1); this is advantageous for high throughput, as it enables the switch fabric to effect simultaneous data transfer for a plurality of slot controllers, and the Data Available signal may be asserted by each slot controller sequentially. This arrangement is particularly preferred where the time taken to transfer the data is several clock cycles.

13 The method of operation will now be explained, with reference to the timing diagram depicted in Fig. 2 and the more detailed diagram of the switch fabric shown in Fig. 3. As can be seen from Fig. 2, the input (SlotO... 3) to each slot controller will be high for a clock cycle, during which time the relevant slot controller is the "active" slot controller. In the case shown in Fig.

2, the Data AvailableO signal has been pulsed high during the active phase for SlotO and the Data Availablel signal has been pulsed high during the active phase for Slotl, indicating that both slots 0 and 1 have data to be transfered. Here, the Data Available signal has been pulsed high for half a clock cycle on the falling edge of the Clock signal, but this need not be the case, particularly when the active phase of each slot is of a diffierent length (for example 2 Clock cycles or longer).

In this embodiment, the switch fabric comprises master and slave switching elements, as can be seen in more detail in Fig. 3. Specifically, a master switching element 11 Oa receives Data Available inputs DAO... DA3 from all four input ports and receives 8 bit wide data paths LDataO... LData3 (these may additionally include parity or other error checking bits, and may be wider or narrower)from each input. In a similar manner, a slave switching element 1 10b receives Data Available inputs DAO... DA3 from all four input ports and receives 8 bit wide data paths HDataO... HData3 from each input. Thus, together, the master and slave switching elements 11 Oa, 11 Ob receive a 16 bit wide data path and in this embodiment are arranged to transfer a data packet received on any of the four inputs to one of two outputs Output 0, Output 1. The other two outputs for slots 2 and 3 are dealt with in a similar manner by another pair of switching elements, not shown. The advantage of this arrangement is that a wider data path can be accomodated than can conveniently be handled by a single switching element. Referring back to Fig. 2, in this case the data to be transferred from both Input 0 and Input 1 is destined for Output 0 and this can be determined by the master switching element by reading the data present on the LData input lines at the time the DataAvailable input is asserted; the first byte is a header byte indicating the desired destination.

To transfer a data packet from each input to the designated output, it must be determined for which output the data is intended (which can be achieved by reading the header byte). If this 14 corresponds to one (or both, in the case of multi-cast cells) of the outputs (here Output 0, Output 1) served by this pair of switching elements 1 10ab, data is read into a buffer in the switching elements assigned to that combination of input and output, if space is available in the buffer. The data in the buffers is then available for output according to a predetermined algorithm, the details of which are not germane. To avoid potential lack of synchronisation between the master and the slave, whether or not data is destined for the master/slave pair and can be accepted is determined by the master switching element and must be signalled to the slave.

In this embodiment, determination whether or not to accept data from an input simply comprises 10 identifying the designated output by reading the byte available at the time the Data Available signal is asserted and checking the appropriate internal buffer availability signal and can be achieved by simple hardware within a single clock cycle. In other embodiments, this may take several cycles and it may be necessary to clockseveral data bytes into intermediate registers if a more complex determination procedure is implemented; whatever arrangement is used, a substantially fixed offset from receipt of the Data Available signal to the result of determination can be provided for all inputs.

The results of the determination for each input and output combination are multiplexed onto two signals, GoO for Output 0 and Go 1 for Output 1 and supplied to the slave. Thus, referring to Fig.

2, in the case described, having determined that the data is intended for Output 0 and that buffer capacity is available, the GoO signal is pulsed one cycle after the Data AvailableO input and again one cycle after the Data Available 1 input. It can be seen that the Go 1 signal pulsed high during the SlotO active period; this implies that in a previous cycle, Data Available 3 was asserted, and data was destined for Output 1.

The defined timing of the "Go" signals enables the determination made by the master switching element 11 Oa to be followed by the slave switching element 11 Ob as both are operating in synchrony, without requiring individual buffer occupancy signals to be exchanged. On activation of the relevant Go signal, both the master and slave load the appropriate data packet into the is appropriate bufFer. Thus, by making use of staggered timing in this way, the number of control signals required between the master and slave switching elements can be reduced; where a large number of inputs are present, this can be a significant advantage.

Referring back to Fig. 1, the switch fabric 10 also supplies an Output Ready signal to each slot controller. If this signal is asserted by the switch fabric during the active phase of a slot controller, this signifies that data is ready to transfer to the slot controller, which can initiate the data transfer. In the example shown in Fig. 2, the switch fabric is signalling that data is ready for transfer to Slots 0 1 and 3.

It will be appreciated that there are many alternative ways in which the invention may be implemented to provide data transfer between slot controllers and a switch fabric whilst preserving the inventive principle that data transfer timing differing between slots is used. For example, the invention may be employed to facilitate the identification of a slot controller, either between the switch fabric and the slot controller, or within the switch fabric, or to enable processing to be pipelined, or testing to be simplified. For example, with large numbers of slot controllers, more than one may be active during a particular phase, with further signals being used to distinguish between active slot controllers.

A slot controller may control more than one physical port, in which case it will usually be necessary to identify the physical port as well as the slot controller. This may conveniently be achieved by appending a header to incoming data packets including one or more bits identifying the physical source and/or destination port. The precise manner in which such a header is added is not critical, but details of an advantageous implementation may be found in our concurrently filed application which bears the reference PMUC/20137, the disclosure of which is incorporated herein by reference. However, it may not be necessary for the switch fabric to interpret this information; this may be done in the destination slot controller.

In the above embodiment, the data to be transferred will typically comprise data packets to be 16 routed though the switch, advantageously ATM cells, preferably with an appended internal header to facilitate routing through the switch.

In a preferred implementation in which ATM cells of 53 bytes with an internal header of 7 bytes are transferred, transfer over a 16-bit wide data path at one word per clock cycle requires 30 clock cycles. A particularly advantageous arrangement in such a case results where 16 slot controllers are catered for and each active phase lasts two clock cycles; the total time required to service all slot controllers is 32 clock cycles. This enables a cell to be transferred completely from a slot controller while the switch fabric is checking whether other slot controllers have cells to transfer, leaving two spare clock cycles for refresh or other operations before transfer of the next packet. More generally, advantages result when the time required to transfer a packet of data is equal to, or slightly less than, the time required to cycle through the active slots, or (in the case of long data packets and relatively few slots) a multiple thereof, as there will then be only a short delay between the tern-fination of one transfer and the commencement of another. Preferably, the switch is arranged to perform other operations, for example Dynamic RAM refresh, in spare cycles between transfers.

In the above embodiment, because the initiation of data transfer from each input is staggered, occuring in a predictable order, it is possible (though not necessary) to share certain hardware elements between inputs. For example, the hardware elements required to initiate data transfer from an input will only be active around the time of the active phase of that input, so may potentially be re-used for one or more other inputs. More generally, similar operations must be performed on multiple data streams, and it will be appreciated that the extent to which hardware can be re-used will depend on the time taken for the operation. For example a single element may service an input in a clock cycle and be ready for re-use for the subsequent input, in which case only a single element may be required. If it requires more time for an operation to be performed, the hardware element may be available for every other input, in which case only two elements may be required, operating alternately. As the time required for an operation increases, the number of elements required increases up to the point where a dedicated element for each input 17 is preferred. It must be appreciated that the saving in hardware required must be offset by any additional hardware required to multiplex the hardware to the appropriate input. Nevertheless, the invention can facilitate the "pipelining" of operations which must be performed on multiple inputs, leading to an overall reduction in hardware.

Referring to Fig. 4a, a second embodiment of the invention incorporating a common processing element will now be explained.

Data from each input of a switch element 2 10 is supplied to a 4-1 multiplexer 212 having a single output which supplies data from one of the inputs to a processor 214. The output of the processor 214 is supplied to a 1-4 demultiplexer 216 which directs data output from the processor to one of four outputs. As indicated by the dotted lines, data can also pass from the inputs of the multiplexer 212 directly to the outputs of the demultiplexer 216, by-passing the multiplexer, processor and demultiplexer. The by-pass route indicated schematically by the dotted lines may pass through an appropriate delay (not shown in the figure) to ensure that data which by-passes the processor arrives at the output of the demultiplexer 216, for passing to buffer array 218 at the correct timing with respect to processed data. The processed data output from the demultiplexer and the original data are re-combined in order and passed to buffer array 218 from which data can be output according to a chosen output algorithm to the appropriate output.

The passage of a data packet will now be explained with reference to Fig. 4b. A data packet 220 input from input Data 0 may include n bytes of which a header portion 220a m must be processed by processor 214 and the remainder 220b simply passed to the buffer array 218. While the portion 220a containg m bytes requiring processing is present at input Data 0 to multiplexer 212, the multiplexer is set to direct the input from Data 0 to the processor 214 (the lower branch of the path in Fig. 4a); this may be achieved by simple timing circuitry which cycles the multiplexer between inputs in sequence. The m bytes of data are passed through the processor 214 to result in a portion of processed data 220a', which is output in sequence to demultiplexer 216. At the time the data is output from the processor 214 (which may be almost instantaneosuly after input, 18 or several clock cycles later), the demultiplexer 216 is arranged to direct the received data to the first input DO of the buffer array 218. Meanwhile, the remaining n-m bytes in the remainder 220b of the data packet 220 are routed to the output of the demultiplexer (corresponding to the upper dotted path in Fig. 4a, the upper branch of the path in Fig. 4b) to rejoin the processed header 220a' to form a modified packet 220'. As shown in Fig. 4b, the remainder 220b of the packet 220 may pass through a delay 222 to ensure synchronisation (for ease of understanding, delays have not been shown in Fig. 4a, but may be inherent in the dotted paths shown). In the case of data packets from other inputs, the portion to be processed from each input is routed in turn through the common processor 214 and the remainder portions are routed via separate by-pass routes, each including a delay if required, directly to the corresponding buffer array input. Thus, in the embodiment of Fig. 4a, there are four by- pass routes and four delays, one from DataO to DO, one from Datal to D 1, one from Data2 to D2 and one from Data3 to D3, but only a single route via the processor 214.

As an example of an application of the above described embodiment, a data packet to be passed through the switching element may include one or more bytes of header which it is desirable to process in the switching element, the (usually larger) remainder being data to be passed unprocessed. Thus, processing will usually be required at the start of transferring the packet, but not during the bulk of packet transfer. As an example, in the case where the first byte contains a logical identifier of the output destination of the packet, it is necessary to map tilis to a physical output port. This mapping must be carried out identically for each input and will usually require reference to a look-up table, which may be stored in the processor 214. Only a single byte may need to be processed.

In such a case, the multiplexer 212 is arranged to direct the first byte(or word) of each data packet to the processor 214, the remainder of each packet passing via the dotted path to the output of the demultiplexer 216. The processor 214 translates each byte by reference to a look-up table, and the demultiplexer inserts the processed byte in the data packet in place of the original byte, prior to storage in the appropriate buffer 218. In this way, a common look-up table and processor can 19 be employed, leading to a saving in hardware and the additional benefit that only a single look-up table need be updated in the event of a change in logical to physical mapping. As mentioned above, in order to insert the processed byte at the correct place in the data packet, any delay introduced by the processor must be compensated for by an equivalent delay in the "direct" data path; thisdelay (corresponding to element 222 in Fig. 4b) may readily be achieved by providing one or more registers. Alternatively, the data may be buffered further or the output of the processor written directly into an appropriate point in the buffer 218, out of sequence with the rest of the packet.

Referring to Fig. 5, an implementation of a suitable cell-header translation apparatus will be described in more detail.

Data inputs, here four 8-bit wide inputs are supplied to a multiplexer 212% which in this embodiment has an additional input for receiving a Control Address. The output of the multiplexer, is connected directly to the Address inputs of a RAM 214'. At the time the data on one of the four inputs corresponds to a logical address to be translated (this is controlled by timing circuitry [not shown], which switches the data to the common path at the beginning of a data packet; this can be detected by the timing of assertion of the Data Available signal) the logical address will be supplied to the RAM as address information. Thus, in this implementation, the relatively simple processing required (translation of one value, a logical address, to another, a physical address) is implemented by a memory and requires only as long as the time taken to address the desired location.

The data stored in the RAM at that address is output as the processed Data Out, the output data identifying the physical port corresponding to the input logical address.

To store an appropriate lookup table mapping a logical address to a physical address, the following procedure is adopted (for example under the control of a system controller for the switch), at any convenient time when data is not being processed, for example on inital configuration:1) The multiplexer is switched to supply the Control- Address to the RAM 2) The logical address to be mapped is supplied as the Control-Address 3) The corresponding physical address is supplied as the Control-Output 4) The Control-Write is asserted to write the data into the RAM.

The process is repeated for all logical addresses to be mapped or modified.

It will, of course, be appreciated that the above description referred to a relatively small number of inputs (four) and outputs (two), relatively simple processing, and a fixed (1 byte) data path width purely for ease of understanding; the invention can be applied to larger switches with processing of multiple larger data words, or to simpler switches.

The cell-header translation of the last-described embodiment may be employed in conjunction with any details of the first embodiment, or independently.

Whilst the embodiment of Fig. 5 provides relatively simple processing, it will be appreciated that a complex algorithm may be performed on the data to be processed.

A flirther application of the invention will now be described which provides a convenient means of signalling buffer occupancy back to the slot controllers from the switch fabric, for example to enable a decision concerning the order in which to effect data transfer to be made by the slot controllers.

Referring to Fig. 6, a switch fabric has 16 inputs DataO... Datal 5 and 16 outputs OutO... Out 15 and comprises 8 switching elements 310a 310h. Each switching element receives all 16 inputs DataO... DatalS, and provides 2 outputs. The precise details of operation of the switching elements are not critical and may be based on conventional arrangements. An advantageous arrangement is described in our concurrently filed application bearing reference PDG/IK/20138. Each switching element includes logic for determining whether data should be input, one or more 21 buffers for storing input cells, and logic for controlling output of cells; for clarity, these elements are not shown. The switch fabric is arranged to identify the source and destination slot controllers; this may be implemented in a similar manner to that described above in relation to Fig. 1, but this is not critical, and conventional arrangements may be employed.

The application of the invention in this embodiment is in the transfer of signalling data from the switching elements, specifically an indication of the level of buffer occupancy. Since there are sixteen inputs and sixteen outputs, there are 256 combinations, and since it may in some case be desirable to provide indication of multiple levels of buffer occupancy rather than simply full or not full, there is a significant amount of data to be gathered from the switching elements and output, which cannot conveniently be achieved by dedicated signal lines for each condition.

In this embodiment, where there are 16 inputs and outputs, each switching element receives, in addition to data, a 16-bit wide signalling word BufInO... 15, each bit corresponding to an input slot, a clock signal, and an appropriately delayed synchronisation signal. The first switching element 3 1 Oa receives the Master synchronisation signal, and each subsequent switching element 310b... 310h receives a synchronisation signal Syncl... Sync7 delayed by 4 clock cycles with respect to the previous synchronisation signal. As shown in this figure, delay can be effected by delay blocks 320a... 320h comprising D-type flip flops providing a delay chain and connected to receive the Master synchronisation signal and the Clock signal; for clarity, the delay chain is shown detached from the switching elements. Where the first embodiment is employed to distinguish slots based on timing, the delay chain used to provide slot identification signals may be advantageously employed to produce the synchronisation signals; where 16 slot signals are provided at 2 clock cycle intervals, the synchronisation signals are taken from each alternative slot signal. Alternatively, the synchronisation signals may be generated within the switching elements from the master and clock signals. Independent timing, and, if desired, clock frequencies may be employed for this embodiment and the previous embodiment even when applied to the same switch fabric.

22 The signalling inputs BufInO.. 15 to the first switching element 3 1 Oa are connected to logic 0, and the signalling inputs of subsequent switching elements are connected to corresponding outputs BufOutO... 15 of the previous element. The outputs from the eight element 3 1 Oh are output to the slot controllers.

When the appropriate synchronisation signal becomes active, the switching element outputs over four clock cycles, in sequence, 2 bits of information pertaining to the buffer occupancy for the first output and then 2 bits of information pertaining to the buffer occupancy for the second output; for example the following combinations may be used:

11 bit 2' bit Condition 0 0 Empty 0 1 1/4 full 1 0 3/4 full 1 1 FULL At other times, the input signal is simply copied to the output. This is performed simultaneously for all 16 inputs for the switching element, to result in a 16 bit wide output word, each bit corresponding to an input.

Referring to Fig. 7, it can be seen that, on activation of the Master synchronisation signal, the first switching element 32a outputs data for outputs 0 and then 1. That is, during the two time periods labelled OutO, I, and OutO,H the first and second bits of information relating to the buffer occupancy for output buffer 0, provided by switching element 3 1 Oa, are outputfor each input.

That is, on signal line BufOutO (referring back to Fig. 6) two bits of data indicating the fullness of the buffer for receiving data from Input 0 for Output 0 will be output. Simultaneously, on signal line BufOut I, two bits of data indicating the fullness of the buffer for receiving data from Input 1 for Output 0 will be output, and similarly for the other signal lines. Thus, after 2 clock cycles, information will be output enabling the capacity of Output 0 to receive data from each of 23 the 16 inputs to be determined. In the following two clock cycles, labelled Outi,L and Outi,H, the corresponding information for Output 1 is output, again provided by switching element 3 1 Oa. Then, on receipt of the Sync 1 signal by the second switching element 3 1 Ob, the corresponding data for outputs 3 and 4 is output. The information passes through the chain to result in an output word 16 bits wide which, over the course of 32 clock cycles, provides buffer occupancy information for each input and each output, without requiring an excessive number of control signals or complicated interface hardware in the switching elements. In total, 512 bits of information are output (16 inputs 16 outputs 2bits per combination) The bit combinations given above are purely exemplary, and other combinations giving an indication of bufler level may be employed ranging from a simple 1 -bit full or empty inidication to a full count of the number of packets stored or the number of spaces available. Most preferably, however, 2 bits are employed, to enable some distinction between partially full buffers to be made, without requiring a complex algorithm to determine the order in which data is transferred.

The precise mechanism for outputting the data is not critical. In one variant, the input can be copied directly, with a four bit shift register storing the buffer occupancy for each signal line being triggered to output its data over 4 clock cycles at the appropriate time. More preferably, each element includes a 4 bit shift register, the registers being effectively connected in series. On receipt of the Master synchronisation signal, the shift register in each switching element is preloaded with the information bits representing the state of the buffers. The shift register at the bottom of the chain has its input connected to null data, for example logic 0 (or 1), and the others have their inputs connected to the output of the preceding shift register. Thus, following receipt of the Master synchronisation signal, the composite shift register formed by the series connection of the individual shift registers contains a word signalling buffer occupancy of each element, and this is then clocked out in serial fashion over subsequent clock cycles. In the embodiment described, as the null data reaches the top of the shift register and is about to be clocked out, the Master synchronisation signal re-loads the shift register with new data, so the null data never 24 emerges.

Thus, it is generally most preferable for the size of the shift register and the time between Master synchronisation pulses to be such that the shift register is continually outputting useful data; this generally means that the number of bits to be output, multiplied by the number of clock cycles required to output a bit (usually 1) equals the number of clock cycles between synchronisation signals.

Each feature disclosed above may be provided independently or in combination with other 10 features, unless otherwise stated. In particular, the invention may be employed in several distinct applications within a single switch.

Claims (1)

1. Claims:

   A method of transferring data to or from at least one of a plurality of similar elements in a data switch or -processing data associated with said at least one element, the method comprising: supplying at least one synchronisation signal defining a reference timing; assigning a respective time window to each of said similar elements with respect to the reference timing, the time window differing between the similar elements; and transferring data to or from said at least one element or processing data during the time 10 window assigned to said at least one element.

   2. A method according to Claim 1, wherein time windows are assigned by supplying to each element an element synchronisation signal delayed by a predetermined amount with respect to a master synchronisation signal defining the reference tin-fing.

   3. A method according to Claim 1 or Claim 2, wherein the elements are located at a plurality of locations within a switch and wherein mutually different synchronisation signals are supplied to mutually different locations, whereby time windows are assigned to elements based on the location of each element within the switch.

   4. A method according to any of Claims 1 to 3, wherein said elements comprise input/output interfaces.

   5. A method of transferring data between one of a plurality of input/output interfaces and a switch fabric coupled to receive data from a plurality of said input/output interfaces, the method comprising: providing at least one synchronisation signal to the switch fabric and the input/output interfaces and transferring data or making data available from each individual input/output interface at 26 a respective predetermined timing with respect to the synchronisation signal, the predetermined timing differing between the input/output interfaces.

   6. A method according to Claim 4 or 5, further comprising distinguishing input/output 5 interfaces based on the timing at which data is transferred or made available.

   7. A method according to Claim 4, 5 or 6, further comprising processing data from successive input/output interfaces in sequence.

   A method of processing, in a data switch, data from one of a plurality of input/output interfaces in a processing element, the method comprising:

   providing at least one synchronisation signal; and processing data from each individual input/output interface at a respective predetermined timing with respect to the synchronisation signal, the predetermined timing differing between the 15 input/output interfaces.

   9. A method according to Claim 8, wherein the processing element is associated with a switch fabric coupled to receive data from a plurality of said input/output interfaces, the processing element serving to process data sequentially from a plurality of input/output interfaces.

   10. A method according to any preceding claim wherein the data comprises data packets to be routed through the switch.

   A method according to Claim 10, wherein the data packets comprise ATM cells.

   12. A method according to Claim 11, wherein a header is appended to the ATM cells containing information identifying a physical port on the input/output interface or information for routing the data packet through the switch..

   27 13. A method according to any of Claims 1 to 3, wherein said elements comprise switch elements of a switch fabric.

   14. A method according to Claim 13 wherein data pertaining to buffer occupancy of the 5 switch elements is output by each switch element.

   15. A method according to Claim 14, wherein the output data is combined into a composite data stream.

   16. A method according to Claim 15, wherein the switch elements are connected in serial fashion to output a serial data stream, the time window assigned to each switch element being based on the position in the serial connection.

   17. A method of providing a measure of buffer occupancy of a plurality of switch elements in a data switch, the method comprising:

   providing at least one synchronisation signal; outputting from each switch element data pertaining to a measure of buffer occupancy of the switch element; and combining the output data from each switch element to generate a composite output serial data stream containing data pertaining to a measure of buffer occupancy of each switch element, the data from each switch element being output at a respective predetermined time with respect to the synchronisation signal.

   18. A method according to Claim 16 or 17, wherein the switch elements are connected in daisy-chain fashion, at least one switch element having an input for receiving a data stream from one or more other switch elements, means for combining the input data stream with data generated by said at least one switch element, and an output for outputting the data stream resulting from said combining.

   28 19. A data switch having a plurality of similar elements therein, the data switch further including: means for supplying at least one synchronisation signal defining a reference timing; means for assigning a respective time window to each of said similar elements with respect to the reference timing, the time window differing between the similar elements; and means for transferring data to or from at least one of said similar elements or processing data during the time window assigned to said at least one element.

   20. A data switch having a plurality of sockets for receiving a respective plurality of similar elements and means for supplying at least one synchronisation signal to each socket, the timings of the synchronisation signals differing between at least two of the sockets, whereby similar elements mounted in said at least two sockets can be distinguished based on the timing of said at least one synchronisation signal supplied to each socket.

   21. A data switch according to Claim 19 or Claim 20, wherein said elements comprise input/output interfaces.

   22. A data switch according to Claim 19 or 20, wherein said elements comprise switch elements of a switch fabric.

   23. A data switch having a plurality of switch elements and including means for providing a measure of buffer occupancy of said plurality of switch elements, the data switch comprising: means for providing at least one synchronisation signal; means for outputting from each switch element data pertaining to a measure of buffer occupancy of the switch element; and means for combining the output data from each switch element to generate a composite output serial data stream containing data pertaining to a measure of buffer occupancy of each switch element, the data from each switch element being output at a respective predetermined time with respect to the synchronisation signal.

   29 24. A data switch according to any of Claims 19 to 23, further comprising means for providing a desired synchronisation signal to each element.

   25. A data switch comprising: a plurality of input/output interfaces; a switch fabric coupled to receive data from a plurality of said input/output interfaces; means for providing at least one synchronisation signal; means for transferring dataor making data available for transfer from each individual input/output interface at a respective predetermined timing with respect to the synchronisation signal, the predetermined timing differing between the inputloutput interfaces.

   26. A data switch according to Claim 25 having a plurality of physical slots for receiving a plurality of input/output interfaces, each slot being configured differently so that the timing of data transfer from each inputfoutput interface is dependent on the slot in which the input/output interface is connected whereby slots can be distinguished without further configuration of the input/output interfaces.

   27. A data switch comprising: a plurality of input/output interfaces; means for providing at least one synchronisation signal; means for processing data from each individual input/output interface at a respective predetermined timing with respect to the synchronisation signal, the predetermined timing differing between the input/output interfaces.

   28. A data switch according to Claim 27, wherein processing comprises mapping a logical destination of a data packet to a physical destination.

   29. A data switch comprising: at least one input port; a plurality of output ports; means for assigning respective logical addresses to output ports of the switch; means for receiving a data packet containing routing information from said at least one input and associating with the packet a logical address corresponding to a destination output port based on the routing information; and means for routing the packet to the destination output port based on the logical address.

   30. A method of routing data packets though a data switch having at least one input port and a plurality of output ports, the method comprising:

   associating a respective logical identifier with each of said output ports; receiving a data packet including routing information; processing the routing information to determine at least one destination output port to which the packet should be routed and associating a logical identifier of said at least one destination output port with the data packet; routing the data packet to said at least one destination output port based on the logical identifier.

   31. A data switch substantially as any one herein described or as illustrated in any of the accompanying drawings.

   32. A method of operating a data switch substantially as any one herein described, with reference to the accompanying drawings.