JP2001053800A - Cross bus switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a cross bus switch in which a working rate is improved. SOLUTION: In a cross bus switch which performs exchange of data transfer paths by bus switches 311 to 334 provided at each node of a plurality of input busses 21 to 24 and a plurality of output busses 51 to 54 which cross with one another, the switch is equipped with an input switching means 6 for distributing data stored in input buffers 11 to 14 to the plurality of input busses 21 to 24, an output switching means 7 for outputting data transferred from the plurality of output busses 51 to 54 to output buffers 41 to 44, and a control means 10 for controlling the operation of the input switching means 6 and the output switching means 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to ATM, Ethe
The present invention is applied to data communication in a communication switch or a parallel computer using rnet (registered trademark) or the like, and exchanges a data transfer path between a plurality of communication terminals in a communication switch and between a plurality of processors in a parallel computer. Related to crossbar switch.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a configuration of a crossbar switch based on the prior art. Crossbar switch is AT
It is installed inside a communication exchange such as M or Ethernet, and exchanges communication paths. The crossbar switch is installed inside the parallel computer, and exchanges a data transfer path when data is transferred between the parallelized processors.

Here, the operation of the conventional crossbar switch will be described with reference to FIG. The crossbar switch is
Generally, it is for selectively connecting n inputs and n outputs. FIG. 4 shows the configuration of the crossbar switch when n = 4.
The description will be made based on FIG.

The crossbar switch shown in FIG. 4 has four input buffers 11 to 14, four input buses 21 to 24,
Output buses 51 to 54 and four output buffers 41 to 4
4, and each input bus 21-24 and each output bus 51-54
Bus switches 311 to 311 installed at the intersections with
14, 321-324, 331-334, 341-34
4.

With this crossbar switch, data input from a certain port can be transferred to any one of port A, port B, port C, and port D, some specific ports, or all ports. It is possible. Hereinafter, as an example, the operation of the crossbar switch when data input from port A is output to another port will be described.

(1) When data input from port A is transferred only to port B, it can be realized by connecting bus switch 312 and disconnecting bus switch 311, bus switch 313, and bus switch 314.

(2) When transferring data input from the port A to the ports C and D, the bus switch 31
3, the bus switch 314 is connected, and the bus switch 31
1, can be realized by disconnecting the bus switch 312.

(3) When transferring data input from port A to all ports, bus switches 311 and 31
2, 313 and 314 can all be connected.

As described above, in the crossbar switch, by connecting / disconnecting each of the bus switches 311 to 314,
The input side and the output side can be selectively connected. That is, an exchange function can be realized. Note that these controls are performed by the crossbar switch controller 10, but information for connecting / disconnecting the crossbar switch is usually included in data input to each port.

[0010] The capability of the crossbar switch is represented by a data transfer amount. That is, the number of input / output ports is n
Assuming that the bus width of each of the input buses 21 to 24 and the output buses 51 to 54 is N bits and the operating frequency of the crossbar switch is M hertz, the capacity of the crossbar switch is as follows: the capacity of the crossbar switch = n × N × M (bit / Sec).

[0011]

In the above-described conventional crossbar switch, the bus widths of the input buses 21 to 24 and the output buses 51 to 54 are fixed to N bits. For this reason, when the load (data transfer amount) balance differs for each input port, a part of the capacity of the crossbar switch is not used, and the operation rate decreases.

For example, when a large amount of data is input only to the ports A, B, and C and there is almost no data input to the port D, the capacity of the entire crossbar switch = 4 × N × M (bit /
Seconds) The used capacity = 3 × N × M (bits / second). Therefore, the operating rate of the crossbar switch = the used capacity / the capacity of the entire crossbar switch = 3 × N × M / 4 × N × M = 3/4, and the operating rate decreases.

An object of the present invention is to provide a crossbar switch having an improved operation rate.

[0014]

In order to solve the above-mentioned problems and achieve the object, a crossbar switch according to the present invention is configured as follows.

(1) A crossbar switch according to the present invention is a crossbar switch in which a data transfer path is exchanged by a bus switch provided at each intersection of a plurality of input buses and a plurality of output buses which cross each other. The input bus and the output bus used for data transfer are dynamically allocated according to conditions.

(2) The crossbar switch of the present invention is a crossbar switch in which a data transfer path is exchanged by a bus switch provided at each intersection of a plurality of input buses and a plurality of output buses which cross each other, and is stored in an input buffer. Input switching means for distributing the received data to the plurality of input buses, output switching means for outputting data transferred from the plurality of output buses to a corresponding output buffer, and the input switching means and the output switching means. And control means for controlling the operation.

(3) The crossbar switch according to the present invention is the switch according to the above (2), and the input switching means has the same number of input bus buffers as the input buses for each of the input buffers. The output switching means includes the same number of output bus buffers as the output buses for each of the output buffers.

(4) The crossbar switch according to the present invention is the switch according to the above (3), and the input bus buffer and the output bus buffer have a plurality of cells for sequentially storing data.

[0019]

FIG. 1 is a diagram showing a system configuration of a crossbar switch according to an embodiment of the present invention. In FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals.
In general, a crossbar switch has n input buses and n output buses. In this embodiment, a case where n = 4 will be described.

The crossbar switch shown in FIG. 1 has four input buffers 11 to 14, four input buses 21 to 24, and four output buses 51 to 54, similarly to the conventional crossbar switch shown in FIG. , Four output buffers 41 to 44, and bus switches 311 to 314, 321 to 3 provided at the intersections of the input buses 21 to 24 and the output buses 51 to 54.
24, 331 to 334, and 341 to 344.

Further, in the crossbar switch according to the present embodiment, the input switch 6 is connected between the four input buffers 11 to 14 and the four input buses 21 to 24 by the four output buses 51 to 54 and 4. An output switch 7 is added between each of the output buffers 41 to 44. These controls are executed by the crossbar switch controller 10.

FIG. 2 is a diagram showing the configuration of the input switch 6. The input switch 6 shown in FIG. 2 includes, for each of the input buffers 11 to 14, the same number of bus buffers 81 to 814, 821 to 824, 83 as the number of input buses 21 to 24.
1 to 834, 841 to 844 are provided.

The input buffer 11 has a FIFO (Firsts)
t In First Out) type buffer,
A cell that stores data input to the head of the input buffer 11 (that is, data to be read first) is a cell 1
The cell storing the data input in the eleventh and second (that is, the data read out in the second) is referred to as a cell 112, and similarly the cell 113, the cell 114, and so on.

For example, the bus buffers 811 to 814 have a function of distributing data from the input buffer 11 to the input buses 21 to 24. The bus buffer 811 is the input bus 2
1, the bus buffer 812 is connected to the input bus 22, the bus buffer 813 is connected to the input bus 23, and the bus buffer 814 is connected to the input bus 24. Which input buses 21 to 24 can transfer data from the input buffer 11 is controlled by the crossbar switch controller 10.

Therefore, the relationship between the transfer of the data input to the input buffer 11 and the connection state of the bus buffers 811 to 814 is as follows.

(1) If the bus buffer 811 is connected and the other buffers 812 to 814 are disconnected,
Data is transferred to the output side only through the input bus 21. That is, the data of the cell 111 is transferred to the input bus 21 every time in synchronization with the operating frequency of the crossbar switch.

(2) If the bus buffers 811 and 812 are in the connected state and the bus buffers 813 and 814 are in the disconnected state, the data is transferred to the output side in parallel using the input bus 21 and the input bus 22. . That is, in synchronization with the operating frequency of the crossbar switch, the data of the cell 111 is transferred to the input bus 21 and the data of the cell 112 is transferred to the input bus 22 every time.
, Respectively.

(3) Bus buffers 811, 812, 81
3 is in the connected state and the bus buffer 814 is in the disconnected state, the data is transferred to the output side in parallel using the input buses 21, 22, 23. That is, in synchronization with the operating frequency of the crossbar switch, the data of the cell 111 is transferred to the input bus 21 and the data of the cell 112 is transferred to the input bus 22 every time.
To the input bus 23.

(4) All bus buffers 811 to 814
Are connected, data is transferred to the output side in parallel using all the input buses 21 to 24. That is,
In synchronization with the operating frequency of the crossbar switch,
11 to the input bus 21, data of the cell 112 to the input bus 22, and data of the cell 113 to the input bus 23
And the data in the cell 114 are transferred to the input bus 24, respectively.

FIG. 3 is a diagram showing the configuration of the output switch 7. The output switch 7 shown in FIG. 3 has the same number of bus buffers 1211 to 1214 and 1221 as the number of output buses 51 to 54 for each of the output buffers 41 to 44.
~ 1224,1231-1234,1241-1244
Is provided. The bus buffer 1211 is connected to the output bus 5
1, the bus buffer 1212 is connected to the output bus 52, the bus buffer 1213 is connected to the output bus 53, and the bus buffer 121
4 are connected to the output bus 54, respectively.

The output buffer 41 has a FIFO (Fi
This is a rst in first out (buffer out) type buffer, and stores cells that store data output first to the output buffer 41 (that is, data that is output first to the port A) in the cell 411 and data that is output second (that is, The cell storing the data output second to port A) is cell 412, and similarly, cell 413, cell 414, and so on.
...

For example, bus buffers 1211 to 1214
Can transmit the data transferred from the output buses 51 to 54 to the output buffer 41 or can not transmit the data. This is executed in conjunction with the input switch 6, but under the control of the crossbar switch controller 10.

Therefore, the relationship between the data sent on the output buses 51 to 54 and the connection state of the bus buffers 1211 to 1214 is as follows.

(1) When the bus buffer 1211 is in the connected state and the other bus buffers 1212 to 1214 are in the disconnected state, the data sent via only the output bus 51 is transferred to the output buffer 41. That is, the data transferred on the output bus 51 is stored in the cell 411.

(2) If the bus buffers 1211 and 1212 are connected and the bus buffers 1213 and 1214 are disconnected, the output bus 51 and the output bus 52 are used.
The data sent in parallel is transferred to the output buffer 41. That is, the data transferred on the output bus 51 is stored in the cell 411, and the data transferred on the output bus 52 is stored in the cell 412.

(3) Bus buffers 1211, 1212
If the bus buffer 1214 is disconnected and the bus buffer 1214 is disconnected, the data transmitted in parallel is transferred to the output buffer 41 using the output buses 51, 52 and 53. That is, the data transferred on the output bus 51 is stored in the cell 411, and the data transferred on the output bus 52 is stored in the cell 4.
12, the data transferred on the output bus 53 is stored in the cell 413
Is stored in

(4) All bus buffers 1211-12
14 is in the connected state, the data sent in parallel is output from the output buffer 41 using all the output buses 51-54.
Transferred to That is, the data transferred on the output bus 51 is to the cell 411, the data transferred on the output bus 52 is to the cell 412, the data transferred on the output bus 53 is to the cell 413, and the data transferred on the output bus 54 is Cell 4
14 is stored.

The crossbar switch according to the present embodiment is
The bus width, that is, the number of the input buses 21 to 24 and the number of the output buses 51 to 54 is increased or decreased according to the input load from the port A to the port D, so that the maximum transfer capacity can be used.

Hereinafter, as a first case, consider a case where there is only data transfer from port A to port A and there is no input from ports B, C and D. In this case, the bus switches 311 and 322 of the crossbar switches
333 and 344 are connected, and the other bus switches are disconnected.

The bus buffer 8 inside the input switch 6
11 to 814 are connected, and the other bus buffers are disconnected. Further, the bus buffers 1211 to 1214 inside the output switch 7 are connected, and the other bus buffers are disconnected.

Thus, data successively input from the port A is output from the input bus 21 to the output bus 51, the input bus 22 to the output bus 52, the input bus 23 to the output bus 53, and the input bus 24 to the output bus 54. The data is transferred in parallel using four buses and output to port A.

In this case, the operation rate of the crossbar switch is 25% because the conventional method uses only one of the four buses, whereas the operation rate of the crossbar switch according to the present embodiment is four. 100% because all buses are used.

Next, as a second case, consider a case where data is transferred from port A to port A, from port B to port B, and there is no input from ports C and D. In this case, the bus switch 31 of the crossbar switch
1, 322, 333, and 344 are connected, and the other bus switches are disconnected.

The bus buffer 8 inside the input switch 6
11 and 812 and the bus buffers 833 and 834 are connected, and the other bus buffers are disconnected. Further, bus buffers 1211, 121 inside the output switch 7
2 and the bus buffers 1233 and 1234 are connected, and the other bus buffers are disconnected.

As a result, data successively input from the port A are transferred in parallel using the two buses, the input bus 21, the output bus 51, and the input bus 22, and the output bus 52, and output to the port A. Is done. At the same time, data successively input from the port B is input to the input bus 23.
Output bus 53 and input bus 24 to output bus 54
The data is transferred in parallel using the system bus and output to port B.

In this case, the operation rate of the crossbar switch is 50% because the conventional system uses only two of the four buses, whereas the system of the present embodiment has four systems. 100% because all buses are used.

Next, as a third case, consider a case where data is transferred from port A to port A, from port B to port B, from port C to port C, and from port D to port D. In this case, the bus switch 311, the bus switch 322, the bus switch 333, and the bus switch 344 of the crossbar switch are connected, and the other bus switches are disconnected.

The bus buffer 8 inside the input switch 6
11, 822, 833 and 844 are connected, and the other bus buffers are disconnected. Further, the output switch 7
Internal bus buffers 1211, 1222, 1233, 1
244 is connected, and the other bus buffers are disconnected.

Thus, data successively input from the port A is output from the input bus 21 to the port A using the output bus 51. Data sequentially input from the port B is output from the input bus 22 to the port B using the output bus 52. Data sequentially input from the port C is output from the input bus 23 to the port C using the output bus 53. Further, data sequentially input from the port D is output to the port D using the input bus 24 and the output bus 54.

In this case, the operation rate of the crossbar switch is the same as that of the conventional system, and all four buses are used.
0%.

As described above, in the crossbar switch according to the present embodiment, the operation rate of the crossbar switch is always 100%.
%, And can be fully utilized.

It should be noted that the present invention is not limited to the above-described embodiment, but can be implemented with appropriate modifications without departing from the scope of the invention.

[0053]

According to the crossbar switch of the present invention, each input bus and each output bus are used for data transfer according to the load condition of the input port so as not to be in a state where data transfer is not performed, that is, in an idle state. Since the input bus and the output bus are dynamically allocated, the capacity of the crossbar switch can be maximized and the operation rate can be improved.

According to the crossbar switch of the present invention, data is distributed to a plurality of input buses, and data transferred from a plurality of output buses is output to a corresponding output buffer.
The ability of the crossbar switch can be maximized and the operation rate can be improved.

According to the crossbar switch of the present invention, all input buses and output buses can be used, so that the operation rate is always 100%.

According to the crossbar switch of the present invention, the data of each cell can be sequentially transferred to the corresponding input bus in synchronization with the operating frequency, and the data from the output bus is sequentially stored in the corresponding cell. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a system configuration of a crossbar switch according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an input switch according to the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of an output switch according to the embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a crossbar switch according to a conventional example.

[Explanation of symbols]

 10 Crossbar Switch Controller 11-14 Input Buffer 111-118 Cell 121-128 Cell 131-138 Cell 141-148 Cell 21-24 Input Bus 311-314 Bus Switch 321-324 Bus Switch 331-334 bus switch 341-344 bus switch 41-44 output buffer 411-418 cell 421-428 cell 431-438 cell 441-448 cell 51-54 output bus 6 input switch 7 .. Output switchers 811-814 Bus buffers 821-824 Bus buffers 831-834 Bus buffers 841-844 Bus buffers 1211-1214 Bus buffers 1221-1224 Bus buffers 1231-1234 Bus buffers 1241-124 ... bus buffer

Claims (4)

[Claims] 1. A crossbar switch in which a data transfer path is exchanged by a bus switch provided at each intersection of a plurality of input buses and a plurality of output buses that intersect each other, wherein data transfer is performed in accordance with a load condition of an input port. A crossbar switch, wherein the input bus and the output bus to be used are dynamically allocated. 2. A crossbar switch in which a data transfer path is exchanged by a bus switch provided at each intersection of a plurality of input buses and a plurality of output buses intersecting with each other, wherein data stored in an input buffer is input to the plurality of input buses. An input switching unit that distributes data to a bus, an output switching unit that outputs data transferred from the plurality of output buses to a corresponding output buffer, a control unit that controls operations of the input switching unit and the output switching unit, A crossbar switch comprising: 3. The input switching means comprises the same number of input bus buffers as the number of input buses for each of the input buffers, and the output switching means comprises the same number of output buses as the number of output buses for each of the output buffers. The crossbar switch according to claim 2, further comprising a bus buffer. 4. The crossbar switch according to claim 3, wherein said input bus buffer and said output bus buffer have a plurality of cells for sequentially storing data.