JP2579508B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor device formed on a substrate made of GaAs and having a resonant tunneling barrier structure having a high barrier height, and a conduction electron band in a barrier layer and its periphery. In order to provide a resonant tunneling barrier structure having a large difference between the bottoms of the layers, each layer is composed of an InGaAs graded layer, an AlAs barrier layer, an InGaAs well layer, an AlAs barrier layer, and an InGaAs graded layer formed on a GaAs substrate. Is selected so that misfit dislocations due to lattice mismatch do not occur, and each of the InGaAs graded layers is graded such that the energy at the bottom of the conduction band gradually decreases toward the AlAs barrier layer. And a resonant tunneling barrier structure.

[Industrial applications]

The present invention relates to a semiconductor device formed on a GaAs substrate and having a resonant tunneling barrier structure having a high barrier height.

[Conventional technology]

Conventionally, resonant tunneling barrier structures formed on a GaAs substrate include, for example, AlGaAs / GaAs / AlGaAs, AlAs
/ GaAs / AlAs and AlAs / In _x Ga _1-x As / AlAs are known.

These are all applied to a semiconductor device requiring a resonant tunneling barrier structure, for example, a resonant tunneling bipolar transistor, a resonant tunneling hot electron transistor, and the like.

[Problems to be solved by the invention]

In the above-described resonance tunneling barrier structure, the peripheral portion of the barrier layer is formed of a GaAs layer. In that case, the difference at the bottom of the conduction electron band between the GaAs layer and the AlAs layer or the AlGaAs layer is only about 0.3 eV at most, so that the contribution of the thermally stimulated current beyond the barrier layer cannot be ignored, Therefore, the differential negative resistance characteristic at room temperature, especially the peak / valley current ratio is small, and currently remains at about 3.5 (if necessary, WDGoodhue et.al., “Larg
e room-temperature effects from resonant tun
neling through AlAs barriers ": Appl.Phys.Lett. 49
(1986), 1086).

The present invention seeks to provide a resonant tunneling barrier structure in which the difference between the bottom of the conduction electron band at the barrier layer and the periphery thereof is large.

[Means for solving the problem]

According to the experiments of the present inventors, a resonant tunneling well of In _x Al _1-x As / In _y Ga _1-y As / In _x Al _1-x As (y = 0.53) grown on an InP substrate Then, the barrier layer In
The periphery of the _y Ga _1-y As (y = 0.53) layer is an In _x Al _1-x As layer,
When x ≧ 0.52, the In _x Al _1-x As (x ≧ 0.52) layer and In _y G
At the interface with the a _1-y As (y = 0.53) layer, the difference in the bottom of the conduction electron band is as large as 0.53 [eV] or more, and therefore, the differential negative resistance at room temperature is good. In addition, the resonant tunneling barrier structure of In _0.52 Al _0.48 As / In _0.53 Ga _0.47 As / In _0.52 Al _0.48 As has a peak / valley current ratio of 5.5, and the resonant tunneling barrier of AlAs / In _0.53 Ga _0.47 As / AlAs The peak / valley current ratio reaches as high as 14 in the barrier structure.

By the way, the resonant tunneling barrier structures showing good characteristics as described above are all formed on the InP substrate, but at present, the best quality and the abundance can be provided in the compound semiconductor substrate. Since the substrate is a GaAs substrate, it is very desirable to form a resonant tunneling barrier structure having good characteristics as described above on the GaAs substrate.

However, since InGaAs and GaAs have a lattice mismatch, the problem must be solved. In this case, it is immediately recalled in connection with the recent technology that a graded layer is interposed between the resonant tunneling barrier structure and the GaAs substrate, but various conditions are required to implement the graded layer. is required.

On the lattice mismatch of In _z Ga _1-z As / GaAs (if necessary,
`` JWMatthews and AEBlackeslee, J.Chyst.Growth
27, referring to 118 (1974) _{"), z Δa / ah c 0.53} 3.18 [%] 40 [Å] 0.4 2.87 [%] 60 [Å] 0.3 2.15 [%] 90 [Å] 0.2 1.43 [%] 160 [ Å] 0.1 0.717 [%] 400 [Å] 00 [%] ∞ a: Lattice constant Δa: Lattice shift Δa / a = [a _InAs −a _GaAs ] / a _GaAs · z _hc : Critical thickness σ: Poisson ratio As described above, in the semiconductor device according to the present invention, an InGaAs graded layer (for example, n-type In _z Ga ₁ -z) formed on a GaAs substrate (for example, n ⁺ -type Gaas substrate 1).
As graded layer 3), AlAs barrier layer (eg, AlAs barrier layer 4), InGaAs well layer (eg, In _y Ga _1-y As well layer 5), AlAs barrier layer (eg, AlAs barrier layer 6), and InGaAs.
A graded layer (for example, an n-type In _z Ga _{1 -z} As graded layer 7) is formed, and the thickness of each layer is selected so that misfit dislocation due to lattice mismatch does not occur.
GaAs graded layer (n-type In _z Ga _1-z As graded layer 3
And the n-type In _z Ga _{1 -z} As graded layer 7) is directed toward the AlAs barrier layer (the AlAs barrier layer 4 and the AlAs barrier layer 6) by the energy of the bottom of the conduction electron band (for example, the bottom E _{c of the} conduction electron band). Is provided with a resonant tunneling barrier structure that is graded so as to gradually decrease.

[Action]

By taking the above measures, there is provided a resonant tunneling barrier structure in which the difference between the barrier layer and the bottom of the conduction band around the barrier layer is large, so that the heat stimulation current and the like across the barrier is greatly reduced. And as a result,
Good differential negative resistance characteristics are obtained, and the peak / valley current ratio is improved.

〔Example〕

FIG. 1 is a cutaway side view of an essential part of one embodiment of the present invention. Here, a diode structure is illustrated.

In the figure, 1 is an n ⁺ type GaAs substrate, 2 is an n ⁺ type GaAs layer, 3
Is an n-type In _z Ga _1-z As graded layer, 4 is an AlAs layer, 5 is In
_y Ga _1-y As well layer, 6 is an AlAs barrier layer, 7 is n-type In _z Ga
_{A 1-z} As graded layer, 8 is an n ⁺ type GaAs layer, 9 is a surface side electrode, and 10 is a substrate side electrode.

The main data in each part is as follows.

(A) About substrate 1 Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Impurity: Si (b) About GaAs layer 2 Thickness: 3000 [Å] Impurity concentration: 2 × 10 ¹⁸ [cm ⁻³ ] Impurity: Si (C) Graded layer 3 Thickness: 90 [Å] Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] Impurity: Si z value: 0.0 → 0.3 (substrate side → barrier layer side) On the near side, a non-doped region having a thickness of, for example, about 15 [Å] is provided.

(D) Thickness of barrier layer 4: 25 [Å] (e) Thickness of well layer 5: 44 [Å] y value: 0.3 (f) Thickness of barrier layer 6: 25 [Å] (g) Gray About dead layer 7 Thickness: 90 [Å] Impurity concentration: 1 × 10 ¹⁸ [cm ⁻³ ] Impurity: Si z value: 3.0 → 0.0 (barrier side → substrate layer side) The thickness is closer to the well layer 5 side. For example, it has a non-doped region of about 15 [Å].

(H) About GaAs layer 8 Thickness: 3000 [Å] Impurity concentration: 5 × 10 ¹⁸ [cm ^-3 ] Impurity: Si (i) Surface-side electrode 9 Material: AuGe / Au Thickness: 200 [Å] / 3000 [Å] (j) Substrate-side electrode 10 Material: AuGe / Au Thickness: 200 [Å] / 3000 [Å] The formation of each semiconductor layer can be realized very easily by applying the MBE method.

FIG. 2 shows an energy band diagram relating to the semiconductor device shown in FIG. 1, and the same symbols as those used in FIG. 1 indicate the same parts or have the same meanings.

In the figure, 3A denotes a non-doped region forming a part of the graded layer 3, and 7A denotes a non-doping region forming a part of the graded layer 7.

The barrier height at the interface between the barrier layer 4 and the well layer 5 or the interface between the well layer 5 and the barrier layer 6 in this embodiment was about 1.2 eV.

As illustrated and described, resonant tunneling barrier structures can be readily applied to quantum effect devices such as those described above, and such semiconductor devices can be used, for example, in high electron mobility transistors (high electron mobility transistors).
transistor: HEMT), heterojunction bipolar transistor (HBT),
Alternatively, it can be understood that it is easy to coexist with a semiconductor laser or the like on the same substrate.

〔The invention's effect〕

In the semiconductor device according to the present invention, the InGaAs graded layer, the AlAs barrier layer, the InGaAs well layer, the AlAs barrier layer, and the InGaAs graded layer are formed, and the thickness of each layer is such that misfit dislocation due to lattice mismatch is caused. A resonant tunneling barrier structure is formed on the GaAs substrate that is selected to such an extent that it does not occur and is graded such that the energy at the bottom of the conduction band gradually decreases toward the AlAs barrier layer. ing.

By adopting the above configuration, a resonant tunneling barrier structure having a large difference between the bottom of the conduction electron band in the barrier layer and the periphery thereof is provided, and therefore, a heat stimulation current or the like exceeding the barrier is greatly reduced. And as a result,
Good differential negative resistance characteristics are obtained, and the peak / valley current ratio is improved.

[Brief description of the drawings]

FIG. 1 shows a cutaway side view of a main part of an embodiment of the present invention, and FIG. 2 shows an energy band diagram of the embodiment shown in FIG. In the figure, 1 is an n ⁺ -type GaAs substrate, 2 is an n ⁺ -type GaAs layer, 3 is an n-type In _z Ga _{1 -z} As graded layer, 4 is an AlAs barrier layer, 5
Is an In _y Ga _1-y As well layer, 6 is an AlAs barrier layer, and 7 is n-type In.
_{A z} Ga _1-z As graded layer, 8 is an n ⁺ -type GaAs layer, 9 is a surface side electrode, and 10 is a substrate side electrode.

Claims (1)

(57) [Claims] An InGaAs graded layer, an AlAs barrier layer, an InGaAs well layer, an AlAs barrier layer and an InGaAs graded layer formed on a GaAs substrate.
The thickness of each layer is selected so that misfit dislocations due to lattice mismatch do not occur, and each InGaAs graded layer has an energy at the bottom of the conduction band toward the AlAs barrier layer. A semiconductor device comprising a resonant tunneling barrier structure graded so as to gradually decrease.