JPH0661245A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce contact resistance between a collector electrode and a collector contact layer without high-temperature heat treatment by providing a superlattice layer which is formed by alternately laminating a well layer which allows higher electronic affinity than a first compound semiconductor layer and a barrier layer which allows lower electronic affinity than a second compound semiconductor layer. CONSTITUTION:For the application to HBT, Al0.3Ga0.7As is used for an emitter, GaAs is used for base/collector and a superlattice formed by alternately forming an Inlays thin film and a GaAs thin film is used between a collector contact layer 2 and a collector layer 4. Namely, the collector contact layer 2, the superlattice layer 3, the collector layer 4, the base layer 5, the emitter layer 6 and the emitter contact layer 7 are crystal-grown on a substrate 1 composed of semi-insulating GaAs, etc., by MBE method. Then, emitter mesa etching and base mesa etching are performed by using photoresist. Thus, stable element characteristics are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, it can be applied to a bipolar transistor such as HBT (heterojunction bipolar transistor) or hot electric transistor (HET). The present invention relates to a semiconductor device in which the contact resistance of a collector contact layer can be lowered to realize high speed operation of an element.

In recent years, the HBT operates at high speed and has a high current driving capability, and therefore, it is expected to be applied to a microwave device and a driver for optical communication.

[0003]

2. Description of the Related Art FIG. 7 is a sectional view showing the structure of a conventional HBT. In FIG. 7, 31 is a substrate of semi-insulating GaAs or the like, and 32 to 36 are n ⁺ -Ga sequentially formed on the substrate 31.
Collector contact layer such as As, collector layer such as n-GaAs, base layer such as p ⁺ -GaAs, n ⁺ -GaAs
And an emitter contact layer such as n ⁺ -InGaAs. 37 is the emitter contact layer 36
An emitter electrode made of WSi or the like is formed thereon, 38 is a base electrode made of Cr / Au or the like formed on the base layer 34, and 39 is AuG formed on the collector contact layer 32.
It is a collector electrode of e / Au or the like.

In the conventional HBT, as shown in FIG. 7, the emitter layer 35, the base layer 34, and the collector layer 33 are each divided into regions of uniform composition. Generally, the emitter layer 35 portion has a bandgap from the base layer 34. Is used to reduce the injection of holes from the base layer 34 to the emitter layer 35 and increase the injection of electrons from the emitter layer 35 to the base layer 34 to obtain a current gain.

By the way, there is a bipolar transistor which can increase the hole injection speed by increasing the hole speed in the base by increasing the electron injection efficiency by using the superlattice as the base and conversely blocking the hole injection. Proposed. For example, Japanese Patent Laid-Open No. 60-10775 reports a bipolar transistor using a superlattice as a base. This is a structure in which a semiconductor having a wide band gap and a semiconductor having a narrow gap are alternately stacked. The wide-gap semiconductor is selectively doped with p-type impurities, and the narrow-gap semiconductor is not doped with impurities. For this reason, the holes fall to the narrow gap side and can travel at high speed in the layer free from impurity scattering, so that the base resistance can be reduced and high-speed operation of the device can be expected.

Further, Japanese Patent Application Laid-Open No. 62-268159 reports a bipolar transistor using a superlattice characterized in that the conduction band Ec difference between two kinds of semiconductors is larger than the Eg difference in the base. In this structure, the holes in the superlattice fall into the quantum well, and the barrier of the emitter seen from the quantum well increases, so that the current gain can be obtained without using a wide-gap semiconductor for the emitter.

Further, in JP-A-64-9656,
A bipolar transistor having a base with strain and a superlattice has been reported. In the strained superlattice here,
Since the mobility of the hole is increased several times in the portion where the compressive stress is applied, the base resistance of the HBT can be reduced. Further, in JP-A-61-150373, a bipolar transistor capable of obtaining a low threshold value by narrowing the band gap by doping the base with a single crystal, a mixed crystal, a superlattice having a small band gap, or by doping impurities. Has been reported. Each of these patents is characterized by using a superlattice as a base.

If the base concentration is increased to lower the base resistance, the impurities in the base will easily diffuse to the emitter side. Thus, if the impurities in the base diffuse to the emitter side, carrier recombination occurs and the current gain decreases, which is not preferable, and therefore it is important to suppress this. Further, if the base resistance is lowered, the contribution of the contact resistance to the base becomes relatively large, so that it is also important to lower the resistance.

Further, when performing mesa etching of HBT, it is not preferable because the ohmic electrode cannot be formed unless the base / emitter interface is exposed with good controllability. Therefore, a technique for exposing the base / emitter interface with good controllability is required. is there. Then, as a means for lowering the base resistance, in addition to increasing the base concentration, a method using a superlattice as a base has been proposed.

However, if a superlattice is used for the entire base in order to lower the base resistance, the structure of the base becomes complicated, and the controllability of crystal growth becomes poor. As a method of solving the problem that the controllability of crystal growth is deteriorated when a superlattice is used for the entire base, the present inventor has previously filed an application. The invention is to insert a layer to reduce the contact resistivity and use this superlattice layer as an etching stopper.

Next, a conventional HBT manufacturing method will be described with reference to FIG. First, the collector contact layer 32, the collector layer 33, the base layer 34, and the emitter layer 35 are formed on the substrate 31.
And emitter contact layer 36 are sequentially grown, and the emitter and base are mesa-etched in stages, and then the emitter contact layer 36, the base layer 34, and the collector contact layer.
By forming the emitter electrode 37, the base electrode 38, and the collector electrode 39 on the 32, respectively, the HBT as shown in FIG.
Can be obtained.

[0012]

In the conventional semiconductor device described above, the resistance of the emitter contact portion can be reduced by adjusting the material of the emitter contact. That is, an n-type semiconductor is usually used for the emitter contact layer and the collector contact layer.
When forming T, InGaA is used for the emitter contact.
By using s, the contact resistance between the emitter electrode and the emitter contact can be reduced, and G
Since the growth is performed while changing the composition from aAs to InGaAs and nothing is grown on InGaAs, the strain does not increase so much, and therefore, there is an advantage that good crystal growth can be performed. On the other hand, if crystal growth is performed using InGaAs for the collector contact in the same manner as described above in order to reduce the resistance of the collector contact and the collector electrode, the lattice constant is significantly different from that of GaAs, so that strain or the like occurs and good crystal growth occurs. There is a problem that the resistance of the collector contact and the collector electrode cannot be reduced as a result.

Therefore, conventionally, the collector electrode has a Ga
The contact resistance between the collector contact layer and the collector electrode is lowered by alloying the electrode and the semiconductor by subjecting the As-based alloy electrode to a high temperature heat treatment at about 450 ° C. However, this method has a problem that it is difficult to obtain stable element characteristics such as a change in element characteristics because the high temperature heat treatment of 450 ° C. is performed.

Therefore, according to the present invention, the contact resistance between the collector electrode and the collector contact layer can be reduced without performing high-temperature heat treatment, stable element characteristics can be obtained, and the degree of process freedom can be increased. An object is to provide a semiconductor device.

[0015]

In order to achieve the above object, a semiconductor device according to the present invention includes a first compound semiconductor layer of one conductivity type and a first compound semiconductor layer between the electrode in Schottky contact with the first compound semiconductor layer. A well layer composed of a second compound semiconductor layer having an electron affinity higher than that of the first compound semiconductor layer and a barrier layer having an electron affinity lower than that of the second compound semiconductor layer and a thickness allowing carriers to be tunneled are alternately laminated. The superlattice layer is provided.

In the present invention, some of the semiconductors of the alternating layers have a smaller bandgap, a lower conduction band, or a higher valence band than the emitter, base and collector. It is preferable to configure
In this case, electrons can be efficiently tunneled. In the present invention, the superlattice layer may be formed between the collector contact or the collector layer and the collector electrode, or may be formed between the base layer and the base electrode, It may be formed between the emitter or the emitter contact layer and the emitter electrode. In these cases, the contact resistance of each contact portion can be reduced as compared with the case where the superlattice layer is not formed.

In the present invention, the difference in the conduction band or valence band of the composition of the first semiconductor layer of the superlattice layer changes in order,
It is preferable that the film thickness is changed accordingly, and in this case, good crystal growth can be performed.

[0018]

As described above, the inventors of the present invention can form a superlattice layer on a part of the base layer and reduce the contact resistance between the base layer and the base electrode through the superlattice layer. Focusing attention, this method is also used for the collector contact portion, a superlattice layer is formed on the collector contact layer, and a part of the collector layer is etched to form a collector electrode on the exposed superlattice layer. When the collector contact layer and the collector electrode are contacted with each other through the superlattice layer, the resistance between the collector contact layer and the collector electrode is remarkably reduced as compared with the case of directly forming each without the superlattice layer. It was possible (however, 45
Only when there is no heat treatment at 0 ° C). Hereinafter, a specific description will be given with reference to the drawings.

FIG. 1 illustrates the principle of the present invention. Figure 1
In (a), GaAs is formed on the first semiconductor layer such as GaAs.
Layer and InGaAs layer thin film alternately stacked GaAs
Layer / InGaAs layer is formed, and a second semiconductor layer such as AlGaAs or GaAs is further formed on the superlattice layer to form a GaAs first semiconductor layer and a Ga layer.
It shows a state where the As / InGaAs superlattice layer and the GaAs second semiconductor layer are in contact with each other. Note that, although the first semiconductor layer and the second semiconductor layer may be made of the same material as described above, they may not be made of the same material. The superlattice layer has a laminated structure of a plurality of thin (several tens of liters) semiconductor layers having different compositions. Usually, if the band gap is different, the lattice constant is different, and if it is not made thin, the crystal will be broken. Considering the film forming property and the tunnel effect of electrons, the thickness of the semiconductor thin film layer forming the superlattice layer is preferably 10 Å or more and 100 Å or less.

By the way, in the case where a metal film is formed on a semiconductor layer without a superlattice layer as in the conventional case, the structure shown in FIG.
As shown in, a Schottky junction is formed between the metal and the semiconductor, and electrons cannot penetrate into the semiconductor layer. Therefore, the contact resistance between the semiconductor layer and the metal film cannot be reduced by simply forming the metal film on the semiconductor layer.

On the other hand, when the semiconductor layer and the semiconductor layer are formed via the superlattice layer as shown in FIG. 1A, the barrier layer of the thin superlattice layer is formed as shown in FIG. 1B. The electrons tunnel and can easily penetrate into the semiconductor layer. The barrier portion of the superlattice is made of a semiconductor having a uniform composition and an equal thickness, such as GaAs. It is preferable that the well (valley) portion has a bottom of the conduction band deeper than that of the barrier portion, becomes shallower in order as it goes to the adjacent well, and the thickness becomes thicker. Although the superlattice may be formed with a constant composition as in the portion A of FIG. 1A, in consideration of forming the film without strain, the above-mentioned composition (conduction band or conduction band) may be used. It is desirable that the film thickness be changed in order and the film thickness be changed accordingly.

In the present invention, the first structure shown in FIG.
By using the above semiconductor layer as a collector layer and the superlattice layer and the second semiconductor layer as a collector contact layer and sandwiching the superlattice layer between them, the following operational effects can be obtained. . (A) The electrons injected from the collector side to the collector contact side can be injected into the collector contact side without feeling the hindrance of electron travel due to the existence of the superlattice layer. (B) Even if the collector portion is removed and the superlattice layer and the metal film are brought into contact with each other, an electron barrier cannot be formed, and the electron can efficiently penetrate the superlattice layer by the tunnel effect of electrons.
Therefore, a stable collector ohmic electrode with reduced contact resistance can be easily formed without performing high temperature heat treatment. (C) Since it is not necessary to perform high-temperature heat treatment for forming the collector electrode, the process flexibility can be increased. (D) Since the first semiconductor layer and the semiconductor layer in the superlattice well portion have different properties, etching can be stopped in the well portion. Therefore, the superlattice layer serves as an etching stop layer, and the surface of the collector contact layer can be easily exposed. (E) It can be expected that the superlattice layer will be a strained superlattice, whereby dislocations extending from the substrate can be absorbed and dislocations can be prevented from being transmitted to the upper layer, which further improves the reliability of the device. Can be improved.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure
2 shows a structure of a semiconductor device according to an embodiment of the present invention.
FIG. The illustrated example is a case applied to HBT.
Here, the emitter is Al_0.3Ga_0.7As, base
GaAs is used for the collector and the collector contact layer and
The present invention is applied between the rectifier layers, specifically, InGaAs
This is a superlattice composed of alternating thin and GaAs thin films.
Used for the part. In FIG. 1, 1 is semi-insulating GaAs
Collector contact layer on this substrate 1.
2 (n⁺-GaAs5x10¹⁸cm ^-3, 5000Å), superlattice layer
3 (InGaAs / GaAs, 5x10¹⁸cm^-3, 300 Å)
[Details are the same as those shown in FIGS. 1 (a) and 1 (b).
], Collector layer 4 (n-GaAs, 3x10¹⁶cm^-3, 40
00Å), base layer 5 (p⁺-GaAs4x10¹⁹cm ^-3, 700
Å), emitter layer 6 (N-AlGaAs, 5x10¹⁷c
m^-3, 1500 Å), emitter contact layer 7 (n⁺-Ga
As, 5x 10¹⁸cm^-3, 1000 Å / n⁺-InGaAs, 5x
Ten¹⁹cm^-3, 1000 Å) are grown by the MBE method.
Emitter etching and base mesa etching
Perform etching. For example, when etching the base mesa
For example, use a mixed solution of ammonium hydroxide and hydrogen peroxide.
And, only the GaAs layer of the collector layer 4 is selectively etched.
Be used. Etching is on the collector contact layer 2
It stops at the superlattice layer 3 and the surface of this superlattice layer 3 is exposed.
It At this time, the superlattice layer 3 portion immediately below the collector layer 4 (see the figure
The dots) have a band structure as shown in FIG.
Electron failure from the collector layer 4 to the collector contact layer 2
It is harmless and allows electrons to penetrate through the superlattice layer 3 efficiently.
It can be injected into the emitter contact layer 7. Well
Also, the superlattice layer 3 part whose surface is exposed by etching
The collector electrode 10 made of metal is attached to the
By pushing it, the van as shown in FIG.
A non-alloyed ohmic contact is obtained due to the
You can Therefore, for example, Ti (100 Å) / P
Simultaneous emitter using t (900 Å) / Au (3000 Å)
The electrode 8, the base electrode 9 and the collector electrode 10 can be formed.
You can This simplifies the electrode formation process
In addition, the alloy electrode is not used,
Do not perform high temperature heat treatment to reduce tact resistance
Contact that has a sufficiently reduced contact resistance.
Obtainable.

In the above embodiment, the case where the superlattice layer 3 is formed between the collector electrode 10 and the collector contact layer 2 has been described, but the present invention is not limited to this, and as shown in FIG. Alternatively, the superlattice layer 3 may be formed between the emitter electrode 8 and the emitter layer 6 and between the base electrode 9 and the base layer 5, or as shown in FIG. It may be formed between the layers 11, between the base electrode 9 and the base layer 5, and between the collector electrode 10 and the collector layer 4. In these cases, the contact resistance can be reduced without performing high-temperature heat treatment on all the contact portions of the emitter, base and collector. Note that FIG. 5 shows a case where the present invention is applied to a collector-up structure HBT.

In each of the above embodiments, the superlattice portion has
Although the case where InGaAs is used as the semiconductor with a narrow band gap has been described, the present invention is not limited to this, and a semiconductor with a narrow band gap such as InAs or GaSb, or a mixed crystal thereof may be used. As the superlattice, for example, FIG.
A combination of semiconductors having a band structure as shown in (b) and (c) may be appropriately used. FIG. 6A shows the case where the Ec band is lowered but the Ev band is raised, and FIGS. 6B and 6C show the case where the Ec and Ev cobands are lowered.

In each embodiment, AlGaAs / GaA is used.
Although the case where the HBT is formed by using the s system has been described, the present invention is not limited to this and, for example, InP / InG is used.
aAs, InAlAs / InGaAs system, or Si
The HBT may be formed by using a / SiGe system or the like. Among these, in the Si / SiGe system HBT, a semiconductor such as InAs or Ge may be used as a semiconductor having a narrow band gap in the superlattice portion.

Further, in the above-mentioned embodiments, the HBT is exemplified as the semiconductor device, but the present invention is not limited to this, and the present invention can be applied to a semiconductor device such as a hot electron transistor (HET) or a static induction transistor (PBT). Needless to say, can be applied similarly.

[0028]

According to the present invention, the contact resistance between the collector electrode and the collector contact layer can be reduced without performing high temperature heat treatment, stable device characteristics can be obtained, and the degree of process freedom can be increased. The effect is that it can be raised.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a cross-sectional view showing the structure of a semiconductor device according to the first embodiment of the present invention.

3 is a diagram showing a band structure of a superlattice layer portion between a collector layer and a collector contact layer shown in FIG.

FIG. 4 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view showing the structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 6 is a band diagram showing an example of a combination of superlattice materials applicable to the present invention.

FIG. 7 is a cross-sectional view showing the structure of a conventional heterojunction bipolar transistor.

[Explanation of symbols]

 1 substrate 2 collector contact layer 3 superlattice layer 4 collector layer 5 base layer 6 emitter layer 7 emitter contact layer 8 emitter electrode 9 base electrode 10 collector electrode 11 emitter contact layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/205

Claims (5)

[Claims] 1. A first compound semiconductor layer of one conductivity type and an electrode in Schottky contact with the first compound semiconductor layer,
A second compound semiconductor layer having a larger electron affinity than the first compound semiconductor layer;
And a barrier layer having an electron affinity smaller than that of the second compound semiconductor layer and having a thickness capable of tunneling carriers, are alternately laminated to form a superlattice layer. apparatus. 2. The semiconductor device according to claim 1, wherein the superlattice layer (3) is formed between a collector contact or collector layer (2, 4) and a collector electrode (10). . 3. The superlattice layer (3) is a base layer (5).
The semiconductor device according to claim 1, wherein the semiconductor device is formed between the base electrode and the base electrode. 4. The superlattice layer (3) comprises an emitter or emitter contact layer (6, 11) and an emitter electrode (8).
The semiconductor device according to claim 1, wherein the semiconductor device is formed between them. 5. The composition of the well layer of the superlattice layer (3) is changed so that the energy level of the bottom of the conduction band or the top of the valence electron is changed in order, and the film thickness is changed in order. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.