JPH05114603A - Bipolar semiconductor device - Google Patents

Abstract

PURPOSE:To obtain high speed operation characteristics by employing a superlattice for a base layer, and to eliminate a problem such as deterioration, etc., of a crystallinity generated by reduction in a base resistance and insertion of the superlattice. CONSTITUTION:In a bipolar semiconductor device having an emitter layer 1, a base layer 2 and a collector layer 3, a superlattice 4 in which two or more types of semiconductor layers having different forbidden band width are alternately laminated is inserted into a lateral part of the layer 2. In this case, the superlattice can be so disposed as to be brought into contact with any of the layers 1 and 3, or formed of two superlattices in contact with the layers 1 and 3. Or, a distortion superlattice can be used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar semiconductor device such as a heterojunction bipolar transistor (HBT). Since the HBT can operate at high speed and has a high current driving capability, it is expected to be suitable as a driver for a microwave element or a light emitting element or a light receiving element for optical communication.

[0002]

Prior to the description of the present invention, a conventionally known bipolar semiconductor device will be briefly described.

FIGS. 6A and 6B are explanatory views of a conventional HBT. In this figure, 31 is semi-insulating GaAs
Substrate, 32 is n ⁺ -GaAs collector contact layer, 3
3 is an n-GaAs collector layer, 34 is ap ⁺ -GaAs base layer, 35 is an n-AlGaAs emitter layer, and 36 is n.
⁺ -GaAs / n ⁺ -InGaAs emitter cap layer, 37 is a collector electrode, 38 is a base electrode, 39 is an emitter electrode, and 40 is a hole.

FIG. 6A shows a conventionally known HB.
The structure of T is shown on the semi-insulating GaAs substrate 31 with n ⁺ -GaAs collector contact layer 32 and n-G.
aAs collector layer 33, p ⁺ -GaAs base layer 34,
n-AlGaAs emitter layer 35, n ⁺ -GaAs / n
^{A +} -InGaAs emitter cap layer 36 is grown and etched in an island shape by emitter mesa etching and base mesa etching, and a collector electrode 37 is formed on the collector contact layer 32 and a base electrode 3 is formed on the base layer 34.
8 on the emitter cap layer 36.
Is formed.

In this HBT, the bandgap of n-GaAs forming the emitter layer 35 is larger than the bandgap of p ⁺ -GaAs forming the base layer 34, so holes from the base layer 34 to the emitter layer 35 are formed. Suppress the injection of
A large current gain is obtained by increasing the injection of electrons from the emitter layer 35 to the base layer 34.

In this HBT, if the impurity concentration of the base layer 34 is increased in order to reduce the base resistance, the impurities in the base layer 34 tend to diffuse toward the emitter layer 35 side and destroy the impurity distribution. Suppressing is an important issue.

Further, when the resistance of the base layer 34 is lowered in this way, the contribution of the contact resistance between the base electrode 38 and the base layer 34 becomes relatively large, so that it is also an important problem to lower the contact resistance. Become.

Further, when performing HBT emitter mesa etching, it is necessary to expose the interface between the base layer 34 and the emitter layer 35 with good controllability, but there is a problem with the controllability of the etching.

FIG. 6B is an energy band diagram between the base layer 34 and the base electrode 38. As shown in FIG. 6A, the base electrode is formed on the base layer 34. In the case of forming 38, since a barrier against the hole 40 as illustrated remains between the base layer 34 and the base electrode 38, the contact resistance of the base electrode 38 increases, which adversely affects the high frequency characteristics. ..

In order to solve these problems, a superlattice is used for the base layer to increase the injection efficiency of electrons from the emitter layer to the base layer, and conversely, to inject holes from the base layer to the emitter layer. It has been proposed to block or increase the speed of electrons and holes in the base layer to operate at high speed.

7 (A), (B), 8 (C), (D)
FIG. 6 is an explanatory diagram of a conventional bipolar semiconductor device. Hereinafter, a conventionally proposed bipolar type semiconductor device using a superlattice for a base layer will be described.

First Conventional Example (See FIG. 7A)
In this figure, 41 is an emitter layer, 42 is a base layer,
43 is an InGaAs layer, 44 is an energy band of the InP layer, 45 is an acceptor, and 46 is a hole.

In this semiconductor device, the base layer 42
As a semiconductor layer (InGaAs) 43 having a large band gap
And a superlattice in which semiconductor layers (InP) 44 having a small bandgap are stacked.

The semiconductor layer having a large forbidden band width is selectively doped with p-type impurities, and the semiconductor layer having a small forbidden band width is undoped. In this configuration, hole 4
No. 6 falls into the semiconductor layer 43 having a small forbidden band, and the layer free from impurity scattering can be moved at a high speed in the direction perpendicular to the paper surface. Therefore, the base resistance is reduced and the operation speed can be expected to be increased.

Second conventional example (see FIG. 7B)
2-268159 gazette) In this figure, 47 is an emitter layer, 48 is a base layer,
49 is a collector layer, 50 is a superlattice, 51 is a SiGe layer,
52 is the energy band of the Si layer.

In this semiconductor device, the base layer is
A superlattice 50 made of a semiconductor layer is used in which the discontinuity value of the conduction band or valence band of the first and second semiconductors is larger than the difference between the forbidden band widths of the first and second semiconductors.

In this structure, holes in the superlattice fall into the quantum well, and the barrier of the emitter seen from the quantum well increases, so that holes do not move even if a semiconductor having a wide band gap is not used as the emitter. High current gain can be obtained by suppressing.

Third conventional example (see FIG. 8C)
4-9656 gazette) In this figure, 53 is an emitter layer, 54 is a base layer,
55 is a collector layer.

In this semiconductor device, the emitter layer 5
3 as the base layer 54 sandwiched between the collector layer 55 and the collector layer 55.
n _{0.53 + x} Ga _0.47-x As layer and In _0.53-x Ga _{0z47 + x} As layer
A superlattice in which layers (x = 0.15) are alternately laminated by 200Å and p-type impurities such as Be are doped is used.

In this structure, I having a large lattice constant
A compressive force acts on the n _{0.53 + x} Ga _0.47-x As layer, and the hole mobility becomes four times higher at room temperature than when x = 0.
The base resistance of the HBT can be reduced.

Fourth conventional example (see FIG. 8D)
In this figure, 56 is an emitter layer, 57 is a base layer,
Reference numeral 58 is a collector layer, and 59 is a substrate.

In this semiconductor device, the collector layer 58, the base layer 57, and the emitter layer 56 are formed on the substrate 59. The base layer 57 has a large forbidden band width Si and a small forbidden band width. A superlattice made of Ge single crystal is used, and with this structure, the bandgap of the base layer is narrowed to obtain a low threshold bipolar transistor. In any of the conventional bipolar semiconductor devices described above, the entire base layer is formed of a superlattice.

[0023]

In the conventional bipolar type semiconductor device described above, as a method of lowering the base resistance, the impurity concentration of the base layer, which causes undesired diffusion of impurities or carrier impurity scattering, is used. The base resistance is lowered by using a superlattice in the base layer instead of adopting the method of raising it.
When the superlattice is used for the entire base layer, the crystal growth controllability becomes poor at the time of crystal growth for forming the superlattice, or for forming the emitter layer or the collector layer on the superlattice, It was unavoidable that the crystallinity of those growth layers deteriorated.

According to the present invention, by using the superlattice for the base layer, high-speed operation characteristics are obtained, the base resistance is lowered, and the crystallinity deterioration caused by inserting the superlattice does not occur. The purpose is to do so.

[0025]

In a bipolar semiconductor device including an emitter layer, a base layer and a collector layer according to the present invention, a superlattice in which two or more kinds of semiconductor layers having different forbidden band widths are alternately laminated. Was adopted in a part of the width direction of the base layer.

In this case, one superlattice is inserted so as to be in contact with the emitter layer or the collector layer, or
A structure in which two superlattices are inserted in contact with the emitter layer and the collector layer is adopted.

In this case, the band gap of the semiconductor layer inserted into the base layer to form the superlattice forms a semiconductor layer forming the base layer, or a semiconductor forming an emitter layer or a collector layer in contact with the superlattice. A structure smaller than the forbidden band width is adopted.

Further, a structure is adopted in which the lattice constant of the semiconductor layer inserted into the base layer to form the superlattice is larger than the lattice constant of the base layer or the emitter layer or collector layer in contact with the superlattice. did.

[0029]

1A to 1C are explanatory views of the bipolar semiconductor device of the present invention. In this figure, 1 is an emitter layer, 2 is a base layer, 3 is a collector layer, and 4 is a superlattice.

In the bipolar semiconductor device of the present invention, as schematically shown in FIG. 1A, the emitter layer 1 and the collector layer 3 are formed of a uniform semiconductor material, but the base layer 2 part, eg base layer 2
The superlattice 4 is formed on the side of the emitter layer 1 by inserting one or more thin layers of a semiconductor material having a band gap smaller than that of the semiconductor material of the base layer 2.

FIG. 1B is an energy band diagram of the valence band near the emitter layer 1 and the base layer 2 of the bipolar semiconductor device of the present invention shown in FIG. Of the superlattice 4 as shown in this figure.
The bandgap of the material inserted into the base layer 2 to form the is smaller than the bandgap of the semiconductor material forming the emitter layer 1 and the base layer 2.

The bipolar semiconductor device of the present invention is shown in FIG.
8 is different from the conventional bipolar semiconductor device shown in FIG. 8 in that the entire base layer is not composed of a superlattice.

Like the bipolar type semiconductor device of the present invention, by providing the base layer having the structure shown in FIGS. 1A and 1B, the following operational effects are produced.

(A) When the base electrode 5 is formed on the superlattice 4 of the base layer 2 (the structure is shown in FIG.
Is shown in. ), In the conventional base layer without a superlattice, a barrier against holes remains between the electrode metal and the base layer, and the contact resistance of the base electrode cannot be ignored (see FIG. 6 (B)). , Fig. 1 (C)
As shown in FIG. 2, since the superlattice 4 is interposed between the base layer 2 and the electrode metal 5, the holes 6 in the valence band are tunneled or resonantly tunneled in the superlattice 4 to form the electrode. It is conducted to the metal 5, the contact resistance between them becomes small, and high speed operation becomes possible.

(B) When the superlattice 4 is formed by using a semiconductor material having a different etching resistance from the semiconductor material forming the emitter layer 1 and the base layer 2, for example, when the emitter layer 1 is removed by etching, The lattice can be used as an etching stopper, and the surface of the base layer 2 can be exposed accurately.

(C) Base layer 2 for forming superlattice
As the semiconductor layer to be inserted into the semiconductor layer, a semiconductor material having a lattice constant larger than that of the semiconductor material forming the base layer 2 or the semiconductor material forming the emitter layer or the collector layer in contact with the superlattice layer is used. When a strained superlattice is formed by applying compressive strain in the semiconductor layer forming
Emitter layer 1 that terminates defects such as dislocations generated in the crystal here and grows the influence of defects in base layer 2 thereon
Has the effect of not telling. Further, the strain in this case has a compressive force perpendicular to the superlattice plane, and therefore has an effect of suppressing diffusion of impurities in the base layer to the emitter layer.

[0037]

(First Embodiment) FIG. 2 is an explanatory diagram of a first embodiment in which the present invention is applied to an HBT. In this figure, 1
1 is a semi-insulating GaAs substrate, 12 is an n ⁺ -GaAs collector contact layer, 13 is an n-GaAs collector layer,
14 is a base layer, 14 'is a semiconductor layer made of p ⁺ -GaAs, 15 is an InGaAs / p ⁺ -GaAs superlattice, 1
6 is an n-AlGaAs emitter layer, 17 is n ⁺ -GaA
An emitter cap layer composed of an s layer and an n ⁺ -InGaAs layer, 18 is a collector electrode, 19 is a base electrode, and 20 is an emitter electrode.

In this embodiment, semi-insulating GaA is used.
s thickness of 5000Å impurity concentration 5 × 10 on the substrate 11
¹⁸cm^-3N⁺-Collector contact made of GaAs
Layer 12, thickness 4000Å, impurity concentration 3 × 10¹⁶cm^-3
Collector layer 13 and base layer 14 made of n-GaAs
Thickness that forms a part of Å impurity concentration 4 × 10¹⁹cm ^-3
P⁺-Semiconductor layer 14 'made of GaAs, thickness 10Å
Non-doped InGaAs layer and thickness 10Å impurity concentration
4 x 10¹⁹cm^-3P⁺-It consists of 5 cycles of GaAs layer
Superlattice 15, thickness 1500Å impurity concentration 5 × 10¹⁷cm
^-3N-AlGaAs emitter layer 16, thickness 1
000Å Impurity concentration 5 × 10¹⁸cm^-3N⁺-GaAs
Layer and thickness 1000Å Impurity concentration 5 × 10¹⁹cm^-3N⁺
-The emitter cap layer 17 made of InGaAs
Combined by molecular beam epitaxy method (MBE method)
Crystal growth.

In this case, the superlattice 15 in the base layer 14
The thickness may be as thin as the width of the surface depletion layer of the base, and the period may be small.

A resist film is formed on the multilayer semiconductor crystal structure formed through the above steps, and mesa etching of the emitter is performed using the patterned film as a mask.

FIG. 3 is an explanatory diagram of an etching process using a superlattice as a stopper. In this figure, 14 is a base layer, 15 is a superlattice, 16 is an emitter layer, and 21 is a resist mask.

As shown in the figure, an emitter layer 16 is formed on a superlattice 15 forming a part of the base layer 14, a photoresist film 21 is formed on the emitter layer 16, and after patterning, the resist mask is formed. 21 as a mask
For example, when emitter mesa etching is performed using a mixed solution of ammonium hydroxide and hydrogen peroxide, only the AlGaAs layer forming the emitter layer is selectively etched, and the InGaAs layer forming the superlattice of the base layer 14 is etched. Then, the surface of the base layer is accurately and uniformly exposed.

After the mesa etching of the emitter, the mesa etching of the base is performed by the same steps as described above.

After that, Au is formed on the collector contact layer 12.
Form a layer of Ge (200Å) / Au (3000Å),
Heat treatment is performed at 450 ° C. to obtain a collector electrode 18 that makes ohmic contact with the collector contact layer 12.

On the superlattice 15 of the emitter cap layer 17 and the base layer 14, Cr (100Å) / Au (3
000Å) is formed to obtain an emitter electrode 20 and a base electrode 19 which make ohmic contact with each semiconductor layer.

When this structure is adopted, a tunnel current flows between the superlattice 15 of the base layer 14 and the Cr base electrode 19, and the contact resistance of the base electrode 19 decreases. In the above-mentioned embodiment, InGaAs is used as the superlattice 15.
Although / GaAs was used, in the case of a graded base, InGaAs / AlGaAs may be adopted and the composition thereof may be changed to adjust the band gap.

In addition, a semiconductor having a narrow bandgap is InGaA
However, a single crystal of a semiconductor having a narrow band gap such as InAs or GaSb or a mixed crystal thereof may be used.

The above HBT is AlGaAs / Ga.
Although it is an As system, for example, InP / InGaAs, Al
In a GaAs / InGaAs-based or Si / SiGe-based HBT, as a semiconductor with a narrow superband forbidden band,
A semiconductor such as InAs or Ge can be used.

FIG. 4 is an energy band diagram of the first embodiment in which the present invention is applied to an HBT. In this figure, 1
3 is a collector layer, 14 is a base layer, 15 is a superlattice, 16
Is an emitter layer.

In this embodiment, the emitter layer 16 has A
l _0.3 Ga _0.7 As, GaAs is used for the base layer 14 and the collector layer 13, and InGaAs is used as a semiconductor with a narrow band gap for forming a superlattice.

FIGS. 5A and 5B are explanatory views of another embodiment in which the present invention is applied to an HBT. In this figure, 2
2, 26 are emitter layers, 23 and 27 are base layers, 24,
28 and 29 are superlattices, and 25 and 30 are collector layers.

(Second Embodiment) FIG. 5A shows the base layer 2
3 shows a schematic structure of the bipolar semiconductor device of the second embodiment, in which the superlattice 24 inserted in 3 is in contact with the collector layer 25.

Contrary to this, the bipolar semiconductor device of the first embodiment is an emitter-up type HBT having the emitter layer on the upper side. However, as shown in FIG. The present invention can also be applied to a collector-up type HBT having 25 on the upper side. In this case, as shown in the figure, the base layer 23 is formed on the emitter layer 22.
Of the superlattice 24 on the side in contact with the collector layer 25.
It is the one.

(Third Embodiment) FIG. 5B shows the base layer 2
7 shows a schematic structure of a bipolar type semiconductor device in which the superlattice inserted in 7 is two: a superlattice 29 in contact with the collector layer 30 and a superlattice 28 in contact with the emitter layer.

This bipolar type semiconductor device is a collector-up HBT similar to the second embodiment, and has a superlattice 2 structure.
8 and 29 have the effect of increasing the mobility of carriers, suppressing the undesired diffusion of impurities from the base layer 27 to the emitter layer 26 and the collector layer 30, and minimizing the deterioration of crystallinity. it can.

[0056]

According to the present invention, the superlattice is etched by inserting the superlattice into a part of the base layer of the bipolar semiconductor device in the width direction, for example, a part of the base layer in contact with the emitter layer or the collector layer. Since the emitter layer and the collector layer can be etched as stoppers, there is an advantage that the manufacturing process can be easily controlled.
Since the tunnel current flows through the superlattice, the contact resistance between the base electrode and the base layer can be reduced, which greatly contributes to speeding up the operation.

Further, when a material having a larger lattice constant than the base layer or the semiconductor layers constituting the emitter layer and the collector layer in contact with the superlattice is selected as the semiconductor material layer constituting the superlattice, one having a larger lattice constant is selected. Compressive strain is generated in the semiconductor material layer, and this compressive strain suppresses diffusion of impurities in the base layer to the emitter layer, so that the impurity distribution can be fixed and the reliability of the bipolar semiconductor device is improved. You can

[Brief description of drawings]

1A to 1C are explanatory views of a bipolar semiconductor device of the present invention.

FIG. 2 is an explanatory diagram of a first embodiment in which the present invention is applied to HBT.

FIG. 3 is an explanatory diagram of an etching process using a superlattice as a stopper.

FIG. 4 is an energy band diagram of a first embodiment in which the present invention is applied to HBT.

5A and 5B are explanatory views of another embodiment in which the present invention is applied to an HBT.

6A and 6B are explanatory diagrams of a conventional HBT.

7A and 7B are explanatory views (1) of a conventional bipolar semiconductor device.

8C and 8D are explanatory views (2) of the conventional bipolar semiconductor device.

[Explanation of symbols]

 1 Emitter layer 2 Base layer 3 Collector layer 4 Superlattice

Claims (5)

[Claims] 1. In a bipolar semiconductor device comprising an emitter layer, a base layer and a collector layer, a superlattice in which two or more kinds of semiconductor layers having different forbidden band widths are alternately laminated is formed on a part of the width direction of the base layer. A bipolar semiconductor device characterized by being inserted. 2. The bipolar semiconductor device according to claim 1, wherein the superlattice inserted in the base layer is in contact with the emitter layer or the collector layer. 3. The bipolar semiconductor device according to claim 1, wherein the superlattice inserted in the base layer is a superlattice in contact with the emitter layer and a superlattice in contact with the collector layer. 4. A semiconductor layer in which a band gap of a semiconductor layer inserted into a base layer to form a superlattice forms a base layer, or a semiconductor layer forming an emitter layer or a collector layer in contact with the superlattice. 4. The bipolar semiconductor device according to claim 1, wherein the bipolar band width is smaller than the band gap. 5. A lattice constant of a semiconductor layer inserted into a base layer to form a superlattice is larger than a lattice constant of a base layer or an emitter layer or a collector layer in contact with the superlattice. Claims 1 to 4
The bipolar semiconductor device according to any one of 1.