JP2005260255A - Compound semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor device having a novel configuration, without degradation in characteristics and reliability due to heat generated when used, and being capable of withstanding the use with high power, and to provide a method for manufacturing the same. <P>SOLUTION: In the compound semiconductor device, including a contact structure 106 consisting of a plurality of layers provided on a semiconductor multilayer 120 and an electrode 109 provided on the contact structure 106, a layer 106c on the side closest to the electrode 109 among the plurality of layers of the contact structure 106 is made of In<SB>x</SB>Ga<SB>1-x</SB>As (0.9≤X≤1); and the heat generated in the semiconductor multilayer 120 is dissipated to the outside via the contact structure 106 and the electrode 109. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a compound semiconductor device that can be suitably used for a power element that requires heat dissipation, such as a heterojunction bipolar transistor (HBT) element, and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, as a compound semiconductor device that requires heat dissipation, a compound semiconductor device is known in which a compound semiconductor layer is provided on a semiconductor substrate to form a semiconductor element, and a bump is formed on an electrode provided thereon. The compound semiconductor device is mounted by connecting the bump and the electrode formed on the mounting substrate with the upper surface of the bump facing the mounting substrate. This mounting method is called a flip-chip method, and high-density mounting is possible. Therefore, this mounting method is considered to be an effective method for mounting LSIs that have a remarkable tendency to increase the number of input terminals and miniaturization.

  When this flip-chip method is used for a power transistor, the bump is used not only as an electrode but also as a heat dissipation path for releasing heat generated in the element. In particular, a heterojunction bipolar transistor (HBT) element tends to have a high heat generation density when operated at a high current density. Therefore, in order for this HBT element to operate properly, it is necessary to efficiently release the heat generated inside the element, and the above-described flip chip method is considered to be particularly effective.

  Techniques using these bumps are disclosed in, for example, Hasegawa et al., Shingaku Technical Journal, Vol. 93, No. 416, “Bump Heat Sink Technology” (1994), and Sato, US Pat. No. 5,373,185. Is disclosed.

  The configuration of a conventional compound semiconductor device will be described below with reference to FIG. The compound semiconductor device 300 in this figure has a semiconductor multilayer 320 on a semi-insulating substrate 301 made of GaAs and a contact structure 306 formed thereon, and an emitter electrode 309 formed on the upper surface of the contact structure 306. Bumps 313 are joined to each other via a plating conductive metal (Ti / Au) layer 312.

The semiconductor multilayer 320 includes a sub-collector layer 302 (thickness: 500 nm) made of n ⁺ GaAs (impurity concentration: 5.0E + 18 / cm ³ ) and n-GaAs (impurity concentration: 2.0E + 16) on a semi-insulating substrate 301. / Cm ³ ) collector layer 303 (thickness: 700 nm), p ⁺ GaAs (impurity concentration: 2.0E + 19 / cm ³ ) base layer 304 (thickness: 80 nm), n-AlGaAs (impurity concentration) : A heterojunction bipolar transistor (HBT) having a structure in which an emitter layer 305 (thickness: 120 nm) made of 5.0E + 17 / cm ³ ) is stacked in this order. The collector electrode 311 (AuGe / Ni / Au), the base electrode 310 (Ti / Pt / Au), and the emitter electrode 309 (Ti / Pt / Au) are provided on the subcollector layer 302, the base layer 304, and the emitter layer 305, respectively. Each is electrically connected.

The contact structure 306 is provided for making contact between the emitter layer 305 and the emitter electrode 309 (Ti / Pt / Au) without performing an alloy process, and is made of n ⁺ GaAs provided on the emitter layer 305 side. First contact layer 306a (impurity concentration: 5.0E + 18 / cm ³ , thickness: 50 nm), second contact layer 306c (impurity concentration:> 1.0E + 19 / cm) made of n ⁺ InGaAs provided on the emitter electrode 309 side ³ and a thickness of 50 nm) and a graded layer 306b made of n ⁺ InGaAs (impurity concentration:> 1.0E + 19 / cm ³ , thickness: 50 nm) between the first and second contact layers 306a and 306c. Have.

In the configuration of FIG. 9, In _x Ga _1-x As (x = 0.5) is often used as a material for forming the second contact layer 306c. InGaAs can be doped with a high concentration of impurities and can form an ohmic electrode having a low contact resistance without performing an alloy process. Usually, in order to obtain lattice matching and conduction band matching between the second contact layer 306c made of In _0.5 Ga _0.5 As and the first contact layer 306a made of GaAs, the mixed crystal ratio of In is changed from 0 to 0.5. The graded layer 306b is formed between the first contact layer and the second contact layer. In order to obtain a good electrical contact, an In mixed crystal ratio of about 0.5 is sufficient. Generally, when the In mixed crystal ratio is 0.5 or more, the problem of mismatch of lattice constants increases. . Therefore, conventionally, In _x Ga _1-x As having x of 0.5 or more has not been used as a material for the graded layer 306b or the second contact layer 306c.
Recently, In _x Ga ₁ that is lattice-matched to an InP substrate from the viewpoint of having excellent carrier running characteristics as a semiconductor material for obtaining an ultrahigh-speed HBT together with a conventionally used GaAs-based material. _{The -x} As (x = 0.53) -based material has attracted attention.

Hereinafter, the configuration of a conventional InP-based HBT using an In _x Ga _1-x As (x = 0.53) material will be described with reference to FIG. In the HBT 700 of this figure, a semiconductor multilayer 720 is formed on a semi-insulating substrate 701 made of InP.

The semiconductor multilayer 720 includes a sub-collector layer 702 (thickness: 500 nm) made of n ⁺ In _0.53 Ga _0.47 As (impurity concentration: 1.0E + 19 / cm ³ ), n-In _0.53 Ga _0.47 on a semi-insulating substrate 701. Collector layer 703 (thickness: 500 nm) made of As (impurity concentration: 1.0E + 16 / cm ³ ), base layer 704 made of p ⁺ In _0.53 Ga _0.47 As (impurity concentration: 1.0E + 19 / cm ³ ) The HBT has a structure in which an emitter layer 705 (thickness: 100 nm) made of n-InP (impurity concentration: 5.0E + 17 / cm ³ ) is laminated in this order.

A part of the subcollector layer 702 and a part of the base layer 704 are exposed by mesa etching, and a collector electrode 711 is exposed on the exposed part of the subcollector layer 702 and a base electrode is exposed on the exposed part of the base layer 704. 710 are each formed as an ohmic electrode. On the emitter layer 705, an emitter electrode 709 is formed as an ohmic electrode via an emitter contact layer 706 (thickness: 100 nm) made of n ⁺ In _0.53 Ga _0.47 As (impurity concentration: 1.0E + 19 / cm ³ ). .

  In the above-described conventional compound semiconductor device with bumps, particularly power elements such as power transistors, the temperature of the element itself is increased due to heat generation during use, and the characteristics and reliability of the element itself are lowered. There is a problem that the characteristics and reliability of the elements mounted in the periphery are deteriorated, and sufficient performance as a power element cannot be exhibited.

Further, in the compound semiconductor device using the In _x Ga _1-x As (x = 0.53) material, the electron running characteristics are improved as compared with the case where the GaAs material is used, but the heat dissipation characteristics are deteriorated. There was a problem. In particular, when an ultrafast and high-power HBT is formed on an InP-based substrate, due to the poor heat dissipation characteristics, device characteristics deteriorate and reliability decreases due to self-heating during use. There is a problem that the adverse effect on the elements mounted in the periphery is remarkable.

  An object of the present invention is to provide a compound semiconductor device having a novel structure that can solve the above-described problems and can withstand use at high power, and a method for manufacturing the compound semiconductor device.

The compound semiconductor device of the present invention includes a semiconductor multilayer formed on a substrate, an In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer, and an In _x Ga _1-x formed on the semiconductor multilayer. It has a superlattice structure in which As (0 ≦ x ≦ 0.1) layers are alternately stacked, and the layer closest to the electrode is an In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer A contact structure comprising: an electrode formed on the contact structure; and a bump formed on the electrode. Heat generated in the semiconductor multilayer is transmitted through the contact structure, the electrode, and the bump. It is characterized by diffusing outside.

A superlattice structure in which the In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer and the In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer are alternately stacked is In _x As the number of molecular layers in the Ga _1-x As (0.9 ≦ x ≦ 1) layer decreases, the number of molecular layers in the In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer increases. It may be characterized by that.

  The superlattice structure may be characterized in that InAs layers and GaAs layers are alternately stacked.

The compound semiconductor device of the present invention includes a semiconductor multilayer formed on a substrate, a contact structure formed on the semiconductor multilayer, an electrode formed on the contact structure, and a bump formed on the electrode. In the compound semiconductor device having the above structure, the contact structure is provided on the semiconductor multilayer side from a layer made of at least In _x Ga _1-x As (0 <x ≦ 0.1) and on the semiconductor multilayer. A layer made of In _x Ga _1-x As (0.1 ≦ x ≦ 0.9) in which the composition ratio x changes from 0.1 to 0.9 as it goes to the electrode, and the layer closest to the electrode A graded layer composed of a layer made of In _x Ga _1-x As (0.9 ≦ x ≦ 1) in contact with the In _x Ga _1-x As (0.1 ≦ x ≦ 0.9) layer. And heat generated in the semiconductor multilayer And diffusing outside through the electrodes and the bumps.

In the contact structure, the thickness of the layer made of In _x Ga _1-x As (0.1 ≦ x ≦ 0.9) in which the composition ratio x is changed from 0.1 to 0.9 is the graded It may be characterized by being 50% or less of the total thickness of the layer.

  The semiconductor multilayer may constitute a heterojunction bipolar transistor including a collector and base layer made of GaAs and an emitter layer made of AlGaAs or InGaP.

The compound semiconductor device of the present invention includes a semiconductor multilayer formed on an InP substrate, an In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer, and an In _x Ga _1-1 formed on the semiconductor multilayer. _It has a superlattice structure in which _x As (0 ≦ x ≦ 0.1) layers are alternately stacked, and the layer closest to the electrode is In _x Ga _1-x As (0.9 ≦ x ≦ 1) A contact structure comprising layers, an electrode formed on the contact structure, and a bump formed on the electrode, and heat generated in the semiconductor multilayer is transmitted through the contact structure, the electrode and the bump. It is characterized by being dissipated outside.

The compound semiconductor device of the present invention is formed on an InP substrate, the InP substrate, an In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer, and an In _x Ga _1-x As (0 ≦ x ≦). 0.1) a layer having a superlattice structure in which layers are alternately stacked, and a semiconductor multilayer formed on the layer having the superlattice structure, and heat generated in the semiconductor multilayer is It is characterized by being diffused to the outside through a layer having a lattice structure and the InP substrate.

The compound semiconductor device of the present invention is formed on an InP substrate and on the InP substrate, and includes an In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer and an In _x Ga _1-x As (0 ≦ x). ≦ 0.1) a layer having a superlattice structure in which layers are alternately stacked, a semiconductor multilayer formed on the layer having the superlattice structure, and an In _x Ga ₁ layer formed on the semiconductor multilayer. _-x as has (0.9 ≦ x ≦ 1) layer and the _{in x Ga 1-x as (} 0 ≦ x ≦ 0.1) layer and are alternately stacked superlattice structure, the side closest to the electrode A contact structure comprising a layer of In _x Ga _1-x As (0.9 ≦ x ≦ 1), an electrode formed on the contact structure, and a bump formed on the electrode, The heat generated in the semiconductor multilayer is dissipated to the outside through the layer having the superlattice structure and the InP substrate. The contact structure, characterized in that to dissipate to the outside through the electrodes and the bumps.

  The layer having the superlattice structure may be a subcollector layer, and the semiconductor multilayer may be composed of at least a collector layer, a base layer, and an emitter layer constituting a heterojunction bipolar transistor.

  The semiconductor multilayer may constitute a heterojunction bipolar transistor including a collector layer made of InGaAs or InP, a base layer made of InGaAs, and an emitter layer made of InP or InAlAs.

  The bump may be directed toward the mounting substrate, and the bump may be connected to an electrode formed on the mounting substrate.

  As described above in detail, according to the present invention, the thermal resistance is 30% or less as compared with the conventional contact structure shown in FIG. 9, and a contact structure lattice-matched with the substrate is obtained, which is excellent in heat dissipation. A compound semiconductor device and a manufacturing method thereof are provided. Since heat generated inside the element can be efficiently dissipated from the electrode side to the outside through the contact structure, the operation characteristics and reliability of the element are not deteriorated by the heat. Therefore, it is possible to provide a compound semiconductor device used at high power such as a power transistor having excellent operating characteristics and reliability. According to another aspect of the present invention, the contact layer whose thermal resistance is 50% or less than that of the conventional contact layer shown in FIG. 10 and the thermal resistance of 60% as compared with the conventional subcollector layer shown in FIG. % Of the subcollector layer is obtained, and a compound semiconductor device excellent in heat dissipation is provided. The heat generated inside the element can be efficiently dissipated from the electrode side to the outside through the contact layer, or can be efficiently dissipated from the InP substrate side to the outside through the subcollector layer. The operating characteristics and reliability are not degraded. Therefore, it is possible to provide a compound semiconductor device used at high power such as a power transistor having excellent operating characteristics and reliability.

  First, the present inventors have found that the deterioration of element characteristics and reliability of a conventional compound semiconductor device when used at high power, as well as the deterioration of the operation characteristics and reliability mounted in the periphery, are caused by the heat dissipation of the compound semiconductor device. Considering that the characteristics are poor, the inventors have studied to improve the heat dissipation characteristics of the semiconductor device. As a result, the following became clear.

In the conventional compound semiconductor device with bumps shown in FIG. 9, heat is mainly generated between the n-GaAs collector layer 303 and the p ⁺ GaAs base layer 304. This heat is generated by the first contact layer 306a and the graded layer. Heat is dissipated through 306b and the second contact layer 306c. As described above, these films have a very thin film thickness of about 50 nm, and at first, it was considered that there was almost no influence on heat dissipation.

The inventors of the present invention have examined the thermal conductivity of the materials constituting these layers as a precaution, and the result is as shown in Table 1 (this table is shown in FIG. 4). . From FIG. 4, in the In _X Ga _1-X As system, GaAs has the best heat conduction, and the heat conduction deteriorates as the amount of Ga replaced with In increases, but the amount of In is 0.9 or more. It turns out that heat conduction is improved again. Considering this, the second contact layer 306c in FIG. 9 is In _0.5 Ga _0.5 As, and thus has the lowest thermal conductivity, and the graded layer 306b extends from the second contact layer 306c side to the first contact layer 306a side. It is predicted that the thermal conductivity will improve as the value approaches.

As described above, the combined thickness of both the second contact layer 306c and the graded layer 306b is about 100 nm at most, and since it is very thin, it has a thermal resistance that hinders heat dissipation of the semiconductor element. However, as shown in the following examples and effects, it has become clear that the heat dissipation characteristics of the semiconductor device are greatly improved by using a new structure for these films.

In the conventional compound semiconductor device shown in FIG. 10, heat is mainly generated between the n-In _0.53 Ga _0.47 As collector layer 703 and the p ⁺ In _0.53 Ga _0.47 As base layer 704. This heat is emitted from the emitter. Heat is radiated from the emitter electrode 709 side through the contact layer 706 or radiated from the InP substrate 701 side through the subcollector layer 702. Similarly, the emitter contact layer 706 and the sub-collector layer 702 were not considered to have a thermal resistance that would inhibit the heat dissipation of the semiconductor element, but as shown in the following examples and effects. In addition, it has been clarified that the use of a new structure for these films significantly improves the heat dissipation characteristics of the semiconductor element.

Examples of the present invention will be described below.
(Example 1)
FIG. 1 is a diagram showing the configuration of the compound semiconductor device 100 of this example. The compound semiconductor device 100 has a semiconductor multilayer 120 on a semi-green substrate 101 made of GaAs and a contact structure 106 formed thereon, and is made of Ti / Pt / Au formed on the upper surface of the contact structure 106. A bump 113 is bonded on the electrode 109 to be formed via a plating conductive metal (Ti / Au) layer 112.

The semiconductor multilayer 120 includes a subcollector layer 102 (thickness: 500 nm) made of n ⁺ GaAs (impurity concentration: 5.0E + 18 / cm ³ ) and n-GaAs (impurity concentration: 2.0E + 16) on a semi-insulating substrate 101. / Cm ³ ) collector layer 103 (thickness: 700 nm), p ⁺ GaAs (impurity concentration: 2.0E + 19 / cm ³ ) base layer 104 (thickness: 80 nm), n-AlGaAs (impurity concentration: 5) 0.0E + 17 / cm ³ ) and an emitter layer 105 (thickness: 120 nm) stacked in this order to form an AlGaAs / GaAs heterojunction bipolar transistor.

The contact structure 106 is provided to make contact between the emitter layer 105 and the emitter electrode 109 without performing an alloying process, and n ⁺ GaAs (impurity concentration: 5.0E + 18 / cm ³⁾ provided on the emitter layer 105 side. ) Made of a first contact layer 106a (thickness: 50 nm), and a second contact layer 106c (thickness: 50 nm) made of n ⁺ InAs (impurity concentration:> 1.0E + 19 / cm ³ ) provided on the emitter electrode 109 side. ) And a graded layer 106b between the first and second contact layers 106a and 106c. The graded layer 106b has a superlattice structure made of GaAs and InAs.

  Details of the structure of the contact structure 106 will be described with reference to FIG. FIG. 3 is a diagram showing the structure and energy band of the contact structure 106. The horizontal axis indicates the position in the thickness direction of the contact structure 106, and the vertical axis indicates the energy level of the conduction band of each semiconductor layer. The graded layer 106b has a superlattice structure in which molecular layers of GaAs and molecular layers of InAs are alternately stacked, and from the GaAs first contact layer 106a side toward the InAs second contact layer 106c. (From right to left in the figure), the thickness of the InAs molecular layer increases and the thickness of the GaAs molecular layer decreases. In the configuration of FIG. 3, GaAs (106a) / InAs1 molecular layer / GaAs9 molecular layer / InAs2 molecular layer / GaAs8 molecular layer /... / GaAs3 molecular layer / InAs8 molecular layer / GaAs2 molecular layer / InAs9 molecular layer / GaAs1 molecule Layer / InAs (106c). With this superlattice structure, a graded layer 106b having high thermal conductivity as well as lattice matching and conduction band matching between the first contact layer 106a made of GaAs and the second contact layer 106c made of InAs is obtained. .

  The thickness and the number of layers of each molecular layer in the superlattice structure are not limited to the above examples, and any structure may be used as long as lattice matching and conduction band matching can be obtained and high thermal conductivity can be obtained. For example, a superlattice structure having two to eighteen molecular layers alternately can be used. The change in the number of molecular layers may not be regular as described above, but may be irregular as long as lattice matching is achieved.

  The compound semiconductor device 100 of the present embodiment is manufactured by a method generally described below.

  First, the subcollector layer 102, the collector layer 103, the base layer 104, the emitter layer 105, and the contact structure 106 (the first contact layer 106a, the graded layer 106b, and the second contact layer 106c) are formed on the semi-insulating GaAs substrate 101. Epitaxial growth is sequentially performed by MBE or MOCVD.

  Thereafter, the semiconductor multilayer 120 on the semi-insulating GaAs substrate 101 is etched into a desired shape by appropriately combining photolithography and etching methods to form the collector electrode 111, the base electrode 110, and the emitter electrode 109. The etching process and these electrode formation processes may be combined as appropriate as shown below.

  In this example, Ti / Pt / Au was used for the emitter electrode material and the base electrode material, and AuGe / Ni / Au was used for the collector electrode material. Here, the alloying temperature of AuGe / Ni / Au is about 390 ° C. Since Ti / Pt / Au does not require an alloying process, the collector electrode is formed by the alloying process first, and the base electrode and the emitter electrode are formed later. This order of formation is very important. Conventionally, in order to simplify the process, the emitter and base electrodes were first formed, and then the collector electrode was alloyed. By reversing, about 10% improvement in heat dissipation characteristics was observed. This is considered to be because the influence of the alloying process can suppress the badness of the emitter electrode.

  In the above embodiment, Ti / Pt / Au is used as the base electrode, but Pt / Ti / Pt / Au may be used. At that time, Pt / Ti / Pt / Au is alloyed at 400 ° C. or higher. . In that case, after forming the base electrode 110 and alloying it, it is desirable to form the collector electrode 111 and perform alloying treatment. After the Pt / Ti / Pt / Au alloying process requiring treatment at a higher temperature is performed first, AuGe / Ni / Au is deposited and alloyed to form the collector electrode 111, thereby forming the first electrode. It can suppress that the material of the electrode formed previously by the alloying process of 2 is influenced. Therefore, in this case, Ti / Pt / Au may be deposited as the emitter electrode after alloying the base electrode and the collector electrode.

  In addition, when Ti / Pt / Au is formed after forming a high melting point material such as tungsten nitride or tungsten silicide as the emitter electrode, the emitter electrode is not easily affected by the alloying process. It may be before the conversion process.

  In this embodiment, it is not always necessary to form the contact structure 106 immediately above the semiconductor multilayer 120, and a so-called ballast resistor layer may be formed between the contact structure 106 and the semiconductor multilayer 120. The ballast resistor layer can be formed using, for example, AlGaAs doped at a low concentration.

  Next, in order to form the bump 113 immediately above the emitter electrode 109, an SiNx film is formed on the entire surface of the semiconductor substrate 101 on which the semiconductor multilayer 120, the contact structure 106, and the electrodes 109, 110, and 111 are formed by a plasma CVD method. Then, patterning and etching for opening the SiNx film are performed only on the emitter electrode portion. Then, a conductive metal layer for plating (Ti / Au) is formed on the entire substrate so as to cover the exposed electrodes, a photoresist layer is formed by patterning the bumps, and bumps are formed by gold plating along the photoresist pattern. Then, the compound semiconductor device 100 is manufactured by removing the photoresist layer.

In the above embodiment, after the contact structure is formed, the collector electrode, the base electrode, and the emic electrode are formed in an appropriate order depending on the configuration, but the emitter layer is formed, and the collector electrode is formed there (alloying process). After that, a contact structure may be formed.
The HBT of this example has a high thermal conductivity of the contact structure 106 and has a heat resistance of 30% or less and excellent heat dissipation characteristics compared to a conventional contact structure using In _0.5 Ga _0.5 As. The heat generated in the semiconductor multi-layer 120) can be efficiently released to the emitter electrode 109 side to prevent deterioration of the operating characteristics and reliability of the compound semiconductor device.
(Example 2)
FIG. 2 shows a compound semiconductor device 200 of this example. The compound semiconductor device 200 is different from the compound semiconductor device 100 of the first embodiment in the configuration of the emitter layer 205 and the contact structure 206. The emitter layer 205 of the compound semiconductor layer 200 can be used in the configuration of the first embodiment, and the emitter layer 105 of the compound semiconductor device 100 of the first embodiment can be applied to the configuration of this embodiment.

  Details will be described below with a focus on the contact structure which is a feature of the present embodiment.

The compound semiconductor device 200 has a semiconductor multilayer 220 on a semi-insulating substrate 201 made of GaAs and a contact structure 206 formed on the semiconductor multilayer 220, and a conductive layer for plating on an electrode 209 formed on the upper surface of the contact structure 206. Bumps 213 are joined via metal (Ti / Au) layer 212. The semiconductor multilayer 220 is formed on a semi-insulating substrate 201, a subcollector layer 202 (thickness: 500 nm) made of n ⁺ GaAs (impurity concentration: 5.0E + 18 / cm ³ ), and n-GaAs (impurity concentration: 2.0E + 16). / Cm ³ ) collector layer 203 (thickness: 700 nm), p ⁺ GaAs (impurity concentration: 2.0E + 19 / cm ³ ) base layer 204 (thickness: 80 nm), n-InGaP (impurity concentration) InGaP / GaAs hetero-coupled bipolar transistor with a structure in which an emitter layer 205 (film thickness: 120 nm) composed of: 5.0E + 17 / cm ³ ) is stacked in this order.

In the compound semiconductor device 200, n-InGaP (impurity concentration: 5.0E + 17 / cm ³ ) is used for the emitter layer 205, and the contact structure 206 has the structure shown in FIG.

  FIG. 5A shows the structure of the contact structure 206 and its energy band. The horizontal axis indicates the position in the thickness direction of the contact structure, and the vertical axis indicates the energy level of the conduction band of each semiconductor layer.

The contact structure 206 includes a first contact layer 206a (thickness: 50 nm) made of GaAs, a graded layer 206b (thickness: 50 nm), and a second contact layer 206c (thickness: 50 nm) made of In _0.9 Ga _0.1 As. Have. The graded layer 206b has an In _0.1 Ga _0.9 As layer having a thickness of 15 nm on the first contact layer 206a side and an In _0.9 Ga _0.1 As layer having a thickness of 15 nm on the second contact layer 206c side. It has an In _x Ga _1-x As (0.1 <x <0.9) layer (thickness: 20 nm) whose composition changes continuously. With this configuration, the thickness of the In _x Ga _1-x As (0.1 <x <0.9) layer having low thermal conductivity can be reduced. As a result, the graded layer 206b realizes a contact structure 206 having a high thermal conductivity as a whole while performing lattice matching and conduction band matching between the first contact layer 206a and the second contact layer 206c.

Further, as shown in FIG. 5B, the graded layer 206b is also made of In _0.9 Ga _0.1 As on the second contact layer 206c ′ side even in the configuration using the layer made of InAs as the second contact layer 206c ′. Since it has a layer, lattice matching and conduction band matching with the second contact layer 206c ′ can be achieved.

The graded layer 206b of this embodiment includes at least an In _x Ga _1-x As (0 <x ≦ 0.1) layer on the first contact layer side and at least an In _x Ga _1-x As on the second contact layer side. The thickness of the In _x Ga _1-x As (0.1 <x <0.9) layer having (0.9 ≦ x <1) layers and having low thermal conductivity formed between them is It has a structure thinner than the thickness of the conventional graded layer 306b shown in FIG. The thickness of the In _X Ga _1-X As (0.1 <x <0.9) layer is desirably about 50% or less of the total thickness of the graded layer 206b, and considering the lattice matching as well, It was found that about 30% or more and about 40% are the most preferable.

The compound semiconductor device 200 can be manufactured by the same method as the compound semiconductor device 100 of the first embodiment. In the case where at least one of the base electrode 210 and the collector electrode 211 is formed using an alloy material, the emitter electrode may be formed after these electrodes are formed, as in the first embodiment. The graded layer 206b can be formed by depositing while changing the composition ratio of Ga and In continuously or stepwise.
The HBT of this example has a high thermal conductivity of the contact structure 206, and has a heat resistance of 30% or less and excellent heat dissipation characteristics as compared with the conventional contact structure using In _0.5 Ga _0.5 As. The heat generated in the semiconductor multilayer 220) can be efficiently released to the emitter electrode 209 side, thereby preventing deterioration of the operating characteristics and reliability of the compound semiconductor device.

FIG. 5A shows an example in which the energy level Ec changes linearly in the conduction band of the In _X Ga _1-X As (0.1 <x <0.9) layer. It may change in a curve. The graded layer 206b may be configured so that the composition gradually changes so that lattice matching and conduction band matching between the first contact layer 206a and the second contact layer 206c can be obtained.

The material of the first contact layer 206a and the second contact layer 206c, may also be used of course In _X Ga _1-X As the (0.9 ≦ x ≦ 1).

Further, instead of the graded layer 206 in the contact structure 206 of the present embodiment, a superlattice structure similar to that of the first embodiment can be used. For example, a superlattice structure in which molecular layers of In _0.1 Ga _0.9 As and In _0.9 Ga _0.1 As are alternately formed can be used as the graded layer. In _X Ga _1-X As (0.9 ≦ x ≦ 1) is used as the material of the second contact layer 206c, and In _X Ga _1-X As (0 ≦ x ≦ 0.1) is used as the material of the first contact layer 206a. Can be used, a superlattice structure in which layers made of the same material as both layers are alternately stacked can also be used.

  The composition of the material composing the graded layer 206b does not need to coincide with the contact layers at the junction boundary between the first and second contact layers, as long as lattice matching and conduction band matching can be obtained.

  Needless to say, the superlattice structure of Example 1 and the graded layer of Example 2 may be combined.

  Furthermore, it is needless to say that the first and second embodiments can be interchanged within the scope of the gist of the present invention.

  In the above embodiments, the AlGaAs / GaAs HBT and the InGaP / GaAs HBT have been described. However, the present invention is not limited to these elements. For example, GaAs may be used as the emitter layer.

The present invention can also be applied to the case where an InP-based HBT is formed using semi-insulating InP instead of a semi-green GaAs substrate .
(Example 3)
FIG. 6 is a diagram showing the configuration of the compound semiconductor device 400 of this example. The compound semiconductor device 400 includes a semiconductor multilayer 420 on an semi-green substrate 401 made of InP and an emitter contact layer 406 formed thereon, and a WN / Ti / formed on the upper surface of the emitter contact layer 406. On the emitter electrode 409 made of Pt / Au, a bump 413 is joined via a conductive metal (Ti / Au) layer 412 for plating.

The semiconductor multilayer 420 includes a subcollector layer 402 (thickness: 500 nm) made of n ⁺ In _0.53 Ga _0.47 As (impurity concentration: 1.0E + 19 / cm ³ ), n-In _0.53 Ga _0.47 on a semi-insulating substrate 401. A collector layer 403 (thickness: 500 nm) made of As (impurity concentration: 1.0E + 16 / cm ³ ) and a base layer 404 made of p ⁺ In _0.53 Ga _0.47 As (impurity concentration: 1.0E + 19 / cm ³ ) The HBT has a structure in which an emitter layer 405 (thickness: 100 nm) made of n-InP (impurity concentration: 1.0E + 17 / cm ³ ) is stacked in this order.

  A part of the sub-collector layer 402 and a part of the base layer 404 are exposed by mesa etching, and a collector electrode 411 is formed on the exposed part of the sub-collector layer 402, and a base electrode is formed on the exposed part of the base layer 404. 410 are formed as ohmic electrodes. On the emitter layer 405, an emitter electrode 409 is formed as an ohmic electrode via an emitter contact layer 406.

Emitter contact layer 406, the contact between the emitter layer 405 and the emitter electrode 409 is provided to take without processing alloyed, n ⁺ InAs (impurity concentration: 2.0E + 19 / cm ³⁾ and n ⁺ GaAs ( (Impurity concentration: 5.0E + 18 / cm ³ ) and a superlattice structure in which 20 molecular layers are stacked 20 times repeatedly. With this superlattice structure, an emitter contact layer 406 having high thermal conductivity as well as lattice matching and conduction band matching between the emitter layer 405 and the emitter electrode 409 can be obtained. Note that the thickness of each molecular layer in the superlattice structure is not limited to the above example, and the repetition of the number of molecular layers may be irregular as well as irregular as described above. It is desirable that the band alignment be obtained. When the emitter contact layer 406 is lattice-matched with the semiconductor multilayer 420 underneath, the semiconductor multilayer and the lattice are formed, for example, when an emitter contact layer is formed by repeating a 10 molecular layer of InAs and a 20 molecular layer of GaAs. Compared to the case where they are not matched, better thermal conductivity can be obtained, and the thermal resistance can be reduced by about 30%.
The HBT of this embodiment has a high thermal conductivity of the emitter contact layer 406 and is lattice-matched to the InP substrate 401. Therefore, the HBT in comparison with the conventional HBT that radiates heat through the emitter contact layer made of In _0.5 Ga _0.5 As is used. Thus, the thermal resistance is reduced to about 50%. For this reason, the heat generated inside the element (semiconductor multilayer 420) can be efficiently released to the emitter electrode 409 side to prevent deterioration of the operating characteristics and reliability of the compound semiconductor device.
Example 4
FIG. 7 is a diagram showing the configuration of the compound semiconductor device 500 of this example. The compound semiconductor device 500 is different from the compound semiconductor device 400 of Example 3 in the configuration of the subcollector layer 502, the emitter layer 505, and the emitter contact layer 506. The emitter layer 505 of the compound semiconductor packaging layer 500 can be used for the configuration of the third embodiment, and the emitter layer 405 of the compound semiconductor device 400 of the third embodiment can be applied to the configuration of this embodiment.

  Details will be described below with a focus on the subcollector layer, which is a feature of this embodiment.

  The compound semiconductor device 500 includes a semiconductor multilayer 520 on an semi-green substrate 501 made of InP and an emitter contact layer 506 formed thereon, and an emitter electrode 509 is formed on the upper surface of the emitter contact layer 506. Yes.

Sub-collector layer 502 constituting the HBT is, n ⁺ InAs (impurity concentration: 1.0E + 19 / cm ³⁾ 47 molecule layer and the n ⁺ GaAs (impurity concentration: 5.0E + 18 / cm ³⁾ of a laminate of 53 molecular layers Is made of a superlattice structure that is repeated 20 times. With this superlattice structure, a subcollector layer 502 having lattice matching with the InP substrate 501 and high thermal conductivity can be obtained. Note that the thickness of each molecular layer in the superlattice structure is not limited to the above example, and the repetition of the number of molecular layers may be irregular as well as irregular as described above, but lattice matching is obtained. It is desirable to have a configuration.

The emitter layer 505 is made of n-In _0.52 Ga _0.48 As (impurity concentration: 1.0E + 17 / cm ³ , thickness: 100 nm), and the emitter contact layer 506 is made of n ⁺ In _0.53 Ga _0.47 As (impurity concentration: 2.0E + 19 / cm ³ , thickness: 100 nm).
The HBT of this embodiment has a high thermal conductivity of the subcollector layer 502 and is lattice-matched to the InP substrate 501, so that it is compared with an HBT that radiates heat through a conventional subcollector layer made of In _0.5 Ga _0.5 As. Thus, the thermal resistance is reduced to about 50%. For this reason, the heat generated inside the element (semiconductor multilayer 520) can be efficiently released to the InP substrate 501 side to prevent deterioration of the operating characteristics and reliability of the compound semiconductor device.
(Example 5)
FIG. 8 is a diagram showing the configuration of the compound semiconductor device 600 of this example. In the compound semiconductor device 600, each of the subcollector layer 602 and the emitter contact layer 606 has a superlattice structure in which InAs layers and GaAs layers are alternately stacked.

  Details will be described below with a focus on the subcollector layer and the emitter contact layer, which are the features of this embodiment.

  The compound semiconductor device 600 has a semiconductor multilayer 620 on a semi-green substrate 601 made of InP and an emitter contact layer 606 formed thereon, and Ti / Pt / formed on the upper surface of the emitter contact layer 606. On the emitter electrode 609 made of Au, a bump 613 is bonded via a plating conductive metal (Ti / Au) layer 612.

Semiconductor multilayer 620, on a semi-insulating substrate 601, n ⁺ InAs (impurity concentration: 1.0E + 19 / cm ³⁾ 47 molecule layer and the n ⁺ GaAs (impurity concentration: 5.0E + 18 / cm ³⁾ 53 molecular layers A subcollector layer 602 having a superlattice structure in which the stacked layers are repeated 30 times, a collector layer 603 (thickness: 500 nm) made of n-In _0.53 Ga _0.47 As (impurity concentration: 1.0E + 16 / cm ³ ), p ⁺ Base layer 604 (thickness: 60 nm) made of In _0.53 Ga _0.47 As (impurity concentration: 1.0E + 19 / cm ³ ), emitter layer 605 made of n-InP (impurity concentration: 1.0E + 17 / cm ³ ) (Thickness: 100 nm) are stacked in this order to form an HBT. The subcollector layer 602 can achieve lattice matching with the InP substrate 601 and have high thermal conductivity by such a superlattice structure.

The emitter contact layer 606 is a superlattice in which molecular layers of n ⁺ InAs (impurity concentration: 1.0E + 19 / cm ³ ) and molecular layers of n ⁺ GaAs (impurity concentration: 5.0E + 18 / cm ³ ) are alternately stacked. The structure is such that the thickness of the InAs molecular layer increases and the thickness of the GaAs molecular layer decreases from the side in contact with the emitter layer 605 toward the emitter contact layer 606. Here, the structure is InAs 20 molecular layer / GaAs 20 molecular layer / InAs 21 molecular layer / GaAs 19 molecular layer /... / GaAs 2 molecular layer / InAs 39 molecular layer / GaAs 1 molecular layer / InAs 40 molecular layer. By this superlattice structure, an emitter contact layer 606 having lattice matching with the emitter layer 305 and high thermal conductivity can be obtained.
Since the HBT of this embodiment uses a superlattice structure in which InAs layers and GaAs layers are alternately stacked for both the emitter contact layer 606 and the subcollector layer 602, the heat generated inside the element is on the emitter electrode 509 side. And about 30% of the thermal resistance compared to the conventional HBT that radiates heat through the emitter contact layer and subcollector layer made of In _0.5 Ga _0.5 As. Reduced to. For this reason, it is possible to efficiently release the heat generated inside the element (semiconductor multilayer 620) and prevent deterioration of the operating characteristics and reliability of the compound semiconductor device. Further, the contact resistance of the emitter electrode 609 could be reduced to 70% of the conventional one by increasing the number of InAs molecular layers constituting the superlattice structure of the emitter contact layer 606 as approaching the emitter electrode 609 side.
After the compound semiconductor device 600 is flip-chip mounted, if a heat-dissipating metal plate is bonded to the back surface of the semi-insulating InP substrate 601 using Au—Sn eutectic or silver paste, the semiconductor multilayer 620 can be more efficiently processed. Can be dissipated from both the emitter contact layer 606 and the subcollector layer 602.

  The present invention is not limited to the HBT, and the compound semiconductor layer and the electrode or the semiconductor multilayer and the electrode are electrically connected through the contact structure, and heat generated in the element is radiated through the contact structure. It can be widely applied to devices that need it.

  The present invention is not limited to a compound semiconductor device with bumps, and can be applied to a configuration in which a metal portion called a thermal shunt is formed on an element. For example, Burhan Bayraktaaroglu et ar, "Very-High-Power-Density CW Operation of GaAs / AlGaAs Microwave Heterojunction Bipolar Transistors" IEEEEDL.Vol.14, No.10, October 1993, pp.493-495. Is disclosed. The heat dissipation of the compound semiconductor can be improved by thermally connecting the metal part for heat dissipation used in the thermal shunt and the compound semiconductor through the electrode structure (contact structure) in the present invention. In this case, the metal part for heat dissipation does not need to function as an electrode, and the electrode structure (contact structure) in the present invention does not need to function as an electrode.

It is a figure which shows the structure of the compound semiconductor device of Example 1 of this invention. It is a figure which shows the structure of the compound semiconductor device of Example 2 of this invention. It is a figure which shows the structure of the contact structure of a compound semiconductor device, and its energy band. It is a graph showing the composition dependency of the thermal conductivity at 300K of In _X Ga _1-X As. It is a figure which shows the structure of the contact structure of a compound semiconductor device, and its energy band. It is a figure which shows the structure of the compound semiconductor device of Example 3 of this invention. It is a figure which shows the structure of the compound semiconductor device of Example 4 of this invention. It is a figure which shows the structure of the compound semiconductor device of Example 5 of this invention. It is a figure which shows the structure of the conventional compound semiconductor device. It is a figure which shows the structure of the conventional compound semiconductor device.

Explanation of symbols

100, 200, 300, 400, 500, 600 Compound semiconductor device 700 Compound semiconductor device 101, 201, 301, 401, 501, 601, 701 Semi-insulating substrate 102, 202, 302, 402, 502, 602, 702 Subcollector Layer 103, 203, 303, 403, 503, 603, 703 Collector layer 104, 204, 304, 404, 504, 604, 704 Base layer 105, 205, 305, 405, 505, 605, 705 Emitter layer 106, 206, 306 Contact structure 406, 506, 606, 706 Emitter contact layer 106a, 206a, 306a First contact layer 106b, 206b, 306b Graded layer 106c, 206c, 206c ′, 306c Second contact layer 109, 209 , 309, 409, 509, 609, 709 Emitter electrode 110, 210, 310, 410, 510, 610, 710 Base electrode 111, 211, 311, 411, 511, 611, 711 Collector electrode 112, 212, 312, 412, 612 conductive metal layer for plating 113, 213, 313, 413, 613, bump 120, 220, 320, 420, 520, 620, 720 semiconductor multilayer

Claims (12)

A semiconductor multilayer formed on a substrate;
An In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer and an In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer are alternately stacked. A contact structure having a superlattice structure, the layer closest to the electrode being an In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer;
An electrode formed on the contact structure;
A bump formed on the electrode;
A compound semiconductor device, wherein heat generated in the semiconductor multilayer is diffused to the outside through the contact structure, the electrode, and the bump. A superlattice structure in which the In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer and the In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer are alternately stacked is In _x As the number of molecular layers in the Ga _1-x As (0.9 ≦ x ≦ 1) layer decreases, the number of molecular layers in the In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer increases. The compound semiconductor device according to claim 1.   The compound semiconductor device according to claim 1, wherein the superlattice structure includes an InAs layer and a GaAs layer that are alternately stacked. In a compound semiconductor device having a semiconductor multilayer formed on a substrate, a contact structure formed on the semiconductor multilayer, an electrode formed on the contact structure, and a bump formed on the electrode,
The contact structure includes a layer made of at least In _x Ga _1-x As (0 <x ≦ 0.1) from the semiconductor multilayer side, and a composition ratio x as it goes from the semiconductor multilayer toward the electrode. A layer made of In _x Ga _1-x As (0.1 ≦ x ≦ 0.9) in which is changed from 0.1 to 0.9, and the In _x Ga _1-x As ( 0.1 ≦ x ≦ 0.9) having a graded layer composed of a layer made of In _x Ga _1-x As (0.9 ≦ x ≦ 1) in contact with the layer,
A compound semiconductor device, wherein heat generated in the semiconductor multilayer is diffused to the outside through the contact structure, the electrode, and the bump. In the contact structure, the thickness of the layer made of In _x Ga _1-x As (0.1 ≦ x ≦ 0.9) in which the composition ratio x is changed from 0.1 to 0.9 is the graded The compound semiconductor device according to claim 4, wherein the thickness is 50% or less of the total thickness of the layer.   6. The compound semiconductor according to claim 1, wherein the semiconductor multilayer constitutes a heterojunction bipolar transistor including a collector and base layer made of GaAs and an emitter layer made of AlGaAs or InGaP. apparatus. A semiconductor multilayer formed on an InP substrate;
An In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer and an In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer are alternately stacked. A contact structure having a superlattice structure, the layer closest to the electrode being an In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer;
An electrode formed on the contact structure;
A bump formed on the electrode;
A compound semiconductor device characterized in that heat generated in the semiconductor multilayer is dissipated to the outside through the contact structure, the electrode and the bump. An InP substrate;
An In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer and an In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer are alternately stacked on the InP substrate. A layer of superlattice structure;
A semiconductor multilayer formed on the layer having the superlattice structure,
A compound semiconductor device characterized in that heat generated in the semiconductor multilayer is dissipated to the outside through the layer having the superlattice structure and the InP substrate. On an InP substrate;
An In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer and an In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer are alternately stacked on the InP substrate. A layer of superlattice structure;
A semiconductor multilayer formed on the layer of the superlattice structure;
An In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer and an In _x Ga _1-x As (0 ≦ x ≦ 0.1) layer are alternately stacked. A contact structure having a superlattice structure, the layer closest to the electrode being an In _x Ga _1-x As (0.9 ≦ x ≦ 1) layer;
An electrode formed on the contact structure;
A bump formed on the electrode;
The heat generated in the semiconductor multilayer is dissipated to the outside through the layer having the superlattice structure and the InP substrate,
A compound semiconductor device, wherein the compound semiconductor device is diffused to the outside through the contact structure, the electrode, and the bump.   10. The layer of the superlattice structure is a subcollector layer, and the semiconductor multilayer is composed of at least a collector layer, a base layer, and an emitter layer constituting a heterojunction bipolar transistor. Compound semiconductor device.   10. The semiconductor multilayer comprises a heterojunction bipolar transistor including a collector layer made of InGaAs or InP, a base layer made of InGaAs, and an emitter layer made of InP or InAlAs. The compound semiconductor device according to any one of the above.   The compound semiconductor device according to claim 1, wherein the bump is directed toward the mounting substrate, and the bump and an electrode formed on the mounting substrate are connected.

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