JP2558466B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2558466B2 JP2558466B2 JP62138384A JP13838487A JP2558466B2 JP 2558466 B2 JP2558466 B2 JP 2558466B2 JP 62138384 A JP62138384 A JP 62138384A JP 13838487 A JP13838487 A JP 13838487A JP 2558466 B2 JP2558466 B2 JP 2558466B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- single crystal
- semiconductor
- semiconductor device
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 239000010408 film Substances 0.000 claims description 48
- 239000013078 crystal Substances 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 15
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 7
- 239000006087 Silane Coupling Agent Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 12
- 230000005669 field effect Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 108091006146 Channels Proteins 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000005046 Chlorosilane Substances 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- KOPOQZFJUQMUML-UHFFFAOYSA-N chlorosilane Chemical compound Cl[SiH3] KOPOQZFJUQMUML-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、IV族もしくはIII−Ｖ族化合物半導体の電
界効果トランジスタ等の半導体装置に関する。TECHNICAL FIELD The present invention relates to a semiconductor device such as a field effect transistor of a group IV or group III-V compound semiconductor.
本発明は、非晶質基板上の半導体単結晶膜をチャネル
領域に用いた電界効果トランジスタで、非晶質基板と半
導体単結晶膜の間にシランカップリング剤から成る表面
周期性を持ったLB膜（ラングミュア・ブロジェット膜）
等の有機薄膜を挿入したものである。The present invention is a field effect transistor using a semiconductor single crystal film on an amorphous substrate as a channel region, and an LB having a surface periodicity made of a silane coupling agent between the amorphous substrate and the semiconductor single crystal film. Membrane (Langmuir-Blodgett membrane)
Etc. is an organic thin film inserted.
従来は非晶質基板上に、電界効果トランジスタを形成
する場合、非晶質基板１上に非晶質もしくは多結晶膜を
形成し、その後レーザ・アニール法やヒータ・アニール
法などにより再結晶化膜10を形成していた（第２図）。
この方法では、完全な単結晶は得られず、多結晶と単結
晶の間の特性をもったものしか得られなかった。Conventionally, when forming a field effect transistor on an amorphous substrate, an amorphous or polycrystalline film is formed on the amorphous substrate 1 and then recrystallized by a laser annealing method or a heater annealing method. The film 10 had been formed (Fig. 2).
By this method, a perfect single crystal could not be obtained, but only one having characteristics between a polycrystal and a single crystal could be obtained.
本発明は、広い単結晶領域を提供し、安定した特性を
有する電界効果トランジスタを可能ならしめるものであ
る。The present invention provides a wide single crystal region and enables a field effect transistor having stable characteristics.
本発明における電界効果トランジスタは、チャネル領
域を設ける半導体膜と非晶質基板との間に、表面周期性
を有するLB膜等の有機薄膜を挿入し、LB膜上の半導体結
晶を単結晶とした。In the field effect transistor of the present invention, an organic thin film such as an LB film having surface periodicity is inserted between a semiconductor film provided with a channel region and an amorphous substrate, and the semiconductor crystal on the LB film is made into a single crystal. .
非晶質基板上に設けられた半導体膜は、単結晶である
ので、通常のSi基盤上に素子を構成するのと同様に扱う
ことができる。またSiO2などの非晶質基板は絶縁性を有
し、寄生容量が小さいために、高速動作を可能とする電
界効果トラジスタを構成できる。Since the semiconductor film provided on the amorphous substrate is a single crystal, it can be handled in the same manner as a device formed on a normal Si substrate. Further, since an amorphous substrate such as SiO 2 has an insulating property and a small parasitic capacitance, a field effect transistor capable of high speed operation can be configured.
以下に図面を用いて本発明を詳述する。 The present invention will be described in detail below with reference to the drawings.
（１）実施例１（第１図） 第１図には本発明による絶縁ゲート型電界効果トラン
ジスタの１例であるSiのMOS型電界効果トランジスタ
（以下MOSFET）の断面構造図を示す。SiO2などの非晶質
基板１の上に、クロロシランなどのシラン・カップリン
グ剤を用いたLB剤２と、さらにその上にＰ型Si単結晶膜
３が設けられている。Ｎ型主電極領域９に挟まれたＰ型
Si単結晶膜の表面をチャネル領域８とし、その上にはゲ
ート絶縁膜４とゲート電極５を設けている。LB膜を構成
するシラン・カップリング剤と、その上に成長させるSi
単結晶膜の面方位の組み合わせは、LB膜の表面周期性と
Si単結晶の格子定数が、ほぼ一致しているか、もしくは
一方が他方の整数倍であることが望ましく、その厚みは
単分子層〜100分子層である。(1) Embodiment 1 (FIG. 1) FIG. 1 shows a cross-sectional structural view of a Si MOS field effect transistor (hereinafter MOSFET) which is an example of an insulated gate field effect transistor according to the present invention. An LB agent 2 using a silane coupling agent such as chlorosilane is provided on an amorphous substrate 1 such as SiO 2, and a P-type Si single crystal film 3 is further provided thereon. P type sandwiched between N type main electrode regions 9
The surface of the Si single crystal film is used as the channel region 8, and the gate insulating film 4 and the gate electrode 5 are provided thereon. Silane coupling agent forming the LB film and Si grown on it
The combination of plane orientations of the single crystal film depends on the surface periodicity of the LB film.
It is desirable that the lattice constants of the Si single crystal are substantially the same or one is an integral multiple of the other, and the thickness thereof is a monomolecular layer to 100 molecular layers.
ここではSiのMOS型について述べてきたが、GeなどのI
V族、GaAsなどのIII−ＶをチャネルとしたMOS型でもよ
く、またSiNやAl2O3などの絶縁物をゲート絶縁膜とした
IV族、III−Ｖ族のMIS型FETであっても構わない。Although I have described the Si MOS type here, I
A MOS type using III-V channel such as V group or GaAs may be used, and an insulator such as SiN or Al 2 O 3 is used as a gate insulating film.
It may be a MIS type FET of group IV or group III-V.
LB族の周期性と半導体の周期性の不整合は、半導体と
して例えばIII−Ｖ族半導体膜でLB膜との不整合を小さ
くし、その後Siをその上に堆積するといった多層構造に
よっても緩和できる。The mismatch between the periodicity of the LB group and the periodicity of the semiconductor can be alleviated by a multilayer structure in which, for example, a III-V group semiconductor film as a semiconductor is used to reduce the mismatch with the LB film and then Si is deposited thereon. .
（２）実施例２（第３図） 第３図は本発明によるショット・ゲート型電界効果ト
ランジスタの１例であるGaAsMES型FETの断面構造図を示
している。実施例１と同様に非晶質基板１上にLB膜２を
設け、さらにその上にＰ型GaAs単結晶膜11を設ける。ｎ
型主電極領域９に挟まれたＰ型GaAs単結晶膜表面をチャ
ネル領域８とし、その上にゲート電極５を設けている。
LB膜とGaAs単結晶膜の組み合わせは、実施例１で述べた
組み合わせとし、厚みも実施例１に従う。(2) Embodiment 2 (FIG. 3) FIG. 3 shows a cross-sectional structural view of a GaAs MES type FET which is an example of the shot gate type field effect transistor according to the present invention. Similar to the first embodiment, the LB film 2 is provided on the amorphous substrate 1, and the P-type GaAs single crystal film 11 is further provided thereon. n
The surface of the P-type GaAs single crystal film sandwiched between the type main electrode regions 9 serves as a channel region 8, and the gate electrode 5 is provided thereon.
The combination of the LB film and the GaAs single crystal film is the combination described in Embodiment 1, and the thickness is also in accordance with Embodiment 1.
ここでは、GaAsについて述べてきたが、InPなどのIII
−Ｖ族のMES型FETであっても構わない。Although I have described GaAs here, I
It may be a V-group MES type FET.
（３）実施例３（第４図） 第４図（ａ）〜（ｅ）により、本発明のMOS型FETの製
造工程例を説明する。第４図（ａ）は、SiO2（石英）基
板１に、ラングミュア・ブロジェット法によりシランカ
ップリング剤を用いたLB膜２を形成する。第４図（ｂ）
はLB膜の上に、CVD法やMBE法などによりＰ型Si単結晶膜
３を成長した状態を示している。第４図（ｃ）は、Si単
結晶膜上にCVD−SiO2膜12をマスクにイオン注入により
ｎ型主電極領域９を設けた状態である。第４図（ｄ）は
CVD−SiO2膜を除去後、ゲート絶縁膜４をCVD法等で全面
に堆積した状態である。第４図（ｅ）はコンタクト開孔
を行い、ソース・ドレイン各電極を形成して完成した状
態を示す。(3) Embodiment 3 (FIG. 4) An example of the manufacturing process of the MOS FET of the present invention will be described with reference to FIGS. In FIG. 4A, an LB film 2 using a silane coupling agent is formed on a SiO 2 (quartz) substrate 1 by the Langmuir-Blodgett method. Fig. 4 (b)
Shows the state in which the P-type Si single crystal film 3 is grown on the LB film by the CVD method or the MBE method. FIG. 4C shows a state in which the n-type main electrode region 9 is provided on the Si single crystal film by ion implantation with the CVD-SiO 2 film 12 as a mask. Figure 4 (d)
After the CVD-SiO 2 film is removed, the gate insulating film 4 is deposited on the entire surface by the CVD method or the like. FIG. 4 (e) shows a state in which contact holes have been formed and source and drain electrodes have been formed and completed.
（４）実施例四（第５図） 第５図（ａ）〜（ｃ）により、本発明のMES型FETの製
造工程例を説明する。第５図（ａ）は、石英基板１上に
LB膜２を設け、さらにその上にMBE法やMOCVD法等によっ
てＰ型GaAs単結晶膜11を成長した状態を示している。第
５図（ｂ）は、CVD−SiO2膜12をマスクにイオン注入に
よりｎ型主電極領域９を設けた状態である。第５図
（ｃ）は、チャネル上のSiO2膜を除去後、ソース６・ド
レイン７各電極，ゲート電極５を形成し完成した状態を
示す。(4) Fourth Embodiment (FIG. 5) An example of a manufacturing process of the MES type FET of the present invention will be described with reference to FIGS. FIG. 5 (a) shows a quartz substrate 1
The LB film 2 is provided, and the P-type GaAs single crystal film 11 is grown on the LB film 2 by the MBE method, the MOCVD method or the like. FIG. 5B shows a state in which the n-type main electrode region 9 is provided by ion implantation using the CVD-SiO 2 film 12 as a mask. FIG. 5C shows a state in which the source 6 and drain 7 electrodes and the gate electrode 5 have been formed and completed after removing the SiO 2 film on the channel.
（５）実施例５（第６図） 第６図（ａ）〜（ｃ）には本発明による３次元ICの製
造工程順断面図を示す。第６図（ａ）は実施例４を施し
たSiMOS型FET上に層間絶縁膜であるCVD−SiO213を堆積
した状態を示している。第６図（ｂ）は、エッチ・バッ
ク法やバイアス・スパッタ法などの平坦化技術を用い
て、堆積したSiO2の表面を平坦化した状態を示してい
る。第６図（ｃ）は平坦化したSiO2上に再び実施例１を
施しSiO2MOS型FETを形成した状態を示している。ここで
は実施例４を２回繰り返した例を示したが、実施例５ま
たは実施例４と５の組み合わせでも良く、繰り返し回数
については何回でも良い。下のFETと上のFETを電気的に
分離する層間絶縁膜については１μｍ以上が好ましく、
SiO2だけではなくAl2O3なども考えられる。(5) Embodiment 5 (FIG. 6) FIGS. 6 (a) to 6 (c) show sectional views in order of the manufacturing steps of the three-dimensional IC according to the present invention. FIG. 6A shows a state in which CVD-SiO 2 13 which is an interlayer insulating film is deposited on the SiMOS type FET subjected to Example 4. FIG. 6B shows a state in which the surface of the deposited SiO 2 is flattened by using a flattening technique such as an etch back method or a bias sputtering method. Figure 6 (c) shows a state of forming a SiO 2 MOS type FET subjected again Example 1 on the SiO 2 was flattened. Although the example in which the fourth embodiment is repeated twice is shown here, the fifth embodiment or a combination of the fourth and fifth embodiments may be used, and the number of repetitions may be any number. About 1 μm or more is preferable for the interlayer insulating film that electrically separates the lower FET and the upper FET,
Not only SiO 2 but also Al 2 O 3 can be considered.
以上のように本発明によれば、非晶質基板上にIV族,I
II−Ｖ族単結晶半導体をチャネル領域とした安定・高速
動作可能な電界効果トランジスタを実現できる。実施例
はｎ型チャネルのエンハンスメント型について説明して
きたが、Ｐ型チャネルにも、デプレッション型にも適用
でき、CMOSも実現できる。上記のように本発明は非晶質
上に高速デバイス,3次元ICを実現するのに有効である。
また、実施例として半導体膜は主に活性領域として利用
する例を述べてきたが、ゲート電極や配線としても利用
できる。またLB膜上は半導体膜に限らずAl等の金属や金
属珪素化合物の結晶化膜にも適用できるものである。As described above, according to the present invention, a group IV, I
It is possible to realize a stable and high-speed field-effect transistor having a II-V group single crystal semiconductor as a channel region. Although the embodiment has been described with respect to the enhancement type of the n-type channel, it can be applied to the P-type channel and the depletion type, and the CMOS can be realized. As described above, the present invention is effective for realizing a high speed device and a three-dimensional IC on an amorphous material.
Further, although the semiconductor film is mainly used as an active region as an example, it may be used as a gate electrode or a wiring. Further, the LB film can be applied not only to a semiconductor film but also to a crystallized film of a metal such as Al or a metal silicon compound.
第１図は本発明によるMOS型FETの断面図，第２図は従来
技術の説明図，第３図は本発明のMES型FETの断面図，第
４図（ａ）〜（ｅ）は本発明のMOS型FETの製造工程順断
面図，第５図（ａ）〜（ｃ）は本発明のMES型FETの製造
工程順断面図，第６図（ａ）〜（ｃ）は本発明の３次元
ICの製造工程順断面図を示したものである。 １……非晶質基板 ２……LB膜 ３……Si単結晶膜 ４……GaAs単結晶膜 ５……ゲート電極 ６……ソース電極 ７……ドレイン領域 ８……チャネル領域 ９……主電極領域1 is a sectional view of a MOS type FET according to the present invention, FIG. 2 is an explanatory view of a conventional technique, FIG. 3 is a sectional view of a MES type FET of the present invention, and FIGS. 5A to 5C are sectional views of the MOS type FET of the invention in the order of manufacturing steps, and FIGS. 5A to 5C are sectional views of the MES type FET of the invention in the order of manufacturing steps. Three-dimensional
3 is a cross-sectional view showing the order of manufacturing steps of an IC. 1 ... Amorphous substrate 2 ... LB film 3 ... Si single crystal film 4 ... GaAs single crystal film 5 ... Gate electrode 6 ... Source electrode 7 ... Drain region 8 ... Channel region 9 ... Main Electrode area
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/00 ３０１ Ｈ０１Ｌ 21/84 27/12 7376−4Ｍ 29/80 Ｂ 29/812 29/28 51/00 (72)発明者 土谷 昭 東京都江東区亀戸６丁目31番１号 セイ コー電子工業株式会社内 (56)参考文献 特開 昭63−126577（ＪＰ，Ａ) 特開 昭63−130165（ＪＰ，Ａ) 特開 昭63−248474（ＪＰ，Ａ)─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 27/00 301 H01L 21/84 27/12 7376-4M 29/80 B 29/812 29/28 51/00 (72) Inventor Akira Tsuchiya 6-31-1 Kameido, Koto-ku, Tokyo Within Seiko Denshi Kogyo Co., Ltd. (56) Reference JP-A-63-126577 (JP, A) JP-A-63-130165 (JP, A) JP-A-63-248474 (JP, A)
Claims (5)
周期性をもつ有機薄膜と、該有機薄膜上に形成した半導
体単結晶膜よりなり、該半導体単結晶膜に主電極領域も
しくは活性領域の少なくとも一部を形成した事を特徴と
する半導体装置。1. An amorphous substrate, an organic thin film having periodicity formed on the amorphous substrate, and a semiconductor single crystal film formed on the organic thin film, wherein the semiconductor single crystal film has a main electrode region. Alternatively, a semiconductor device characterized in that at least a part of an active region is formed.
囲第１項記載の半導体装置。2. The semiconductor device according to claim 1, wherein the organic thin film is an LB film.
の範囲第１項又は第２項記載の半導体装置。3. The semiconductor device according to claim 1, wherein the organic thin film is a monomolecular layer.
主成分とする特許請求の範囲第１項又は第２項又は第３
項記載の半導体装置。4. The organic thin film containing a silane coupling agent as a main component, as claimed in claim 1, claim 2, or claim 3.
The semiconductor device according to the item.
の化合物半導体よりなる単層又は多層膜である特許請求
の範囲第１項記載の半導体装置。5. The semiconductor device according to claim 1, wherein the semiconductor single crystal film is a single layer or a multilayer film made of Si, Ge, GaAs, or other compound semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62138384A JP2558466B2 (en) | 1987-06-02 | 1987-06-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62138384A JP2558466B2 (en) | 1987-06-02 | 1987-06-02 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63302571A JPS63302571A (en) | 1988-12-09 |
| JP2558466B2 true JP2558466B2 (en) | 1996-11-27 |
Family
ID=15220680
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62138384A Expired - Lifetime JP2558466B2 (en) | 1987-06-02 | 1987-06-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2558466B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2828152B2 (en) * | 1991-08-13 | 1998-11-25 | 富士通 株式会社 | Method of forming thin film, multilayer structure film, and method of forming silicon thin film transistor |
| US5480818A (en) * | 1992-02-10 | 1996-01-02 | Fujitsu Limited | Method for forming a film and method for manufacturing a thin film transistor |
-
1987
- 1987-06-02 JP JP62138384A patent/JP2558466B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63302571A (en) | 1988-12-09 |
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