JP2550968B2 - Crystallization method of semiconductor thin film - Google Patents
Crystallization method of semiconductor thin filmInfo
- Publication number
- JP2550968B2 JP2550968B2 JP62029356A JP2935687A JP2550968B2 JP 2550968 B2 JP2550968 B2 JP 2550968B2 JP 62029356 A JP62029356 A JP 62029356A JP 2935687 A JP2935687 A JP 2935687A JP 2550968 B2 JP2550968 B2 JP 2550968B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor thin
- amorphous
- annealing
- photoresist layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、固相成長法を使用した半導体薄膜の結晶化
方法に関する。TECHNICAL FIELD The present invention relates to a method for crystallizing a semiconductor thin film using a solid phase growth method.
本発明は、固相成長法を使用した単結晶薄膜の形成方
法であり、部分的に結晶化した非晶質半導体薄膜の上に
マスク層を選択的に形成し、再度非晶質化した後、改め
て結晶化させることにより、粒径の大きな単結晶薄膜が
られるようにしたものである。〔従来の技術〕 従来、石英のような絶縁性基板上にCVD（化学気相成
長）法により多結晶（ポリ）Si層を形成し、シリコンSi
+のイオン注入を行って非晶質（アモルファス）化した
後、アニールによって固相エピタキシャル成長させて単
結晶Si薄膜を得る方法（固相成長法）が提案されてい
る。The present invention is a method for forming a single crystal thin film using a solid phase growth method, in which a mask layer is selectively formed on a partially crystallized amorphous semiconductor thin film, and then the amorphous layer is re-amorphized. By crystallizing again, a single crystal thin film having a large grain size can be formed. [Prior Art] Conventionally, a polycrystalline (poly) Si layer is formed on an insulating substrate such as quartz by a CVD (Chemical Vapor Deposition) method.
A method (solid phase growth method) has been proposed in which a single crystal Si thin film is obtained by performing solid phase epitaxial growth by annealing after performing + ion implantation to make it amorphous.
上述した従来の固相成長法によれば、アニール後Si薄
膜の一部分に結晶化が生じても、その周囲においても結
晶核が不規則に多数発生するため、粒径の大きな単結晶
Si薄膜が得られないという問題点があった。According to the conventional solid phase growth method described above, even if crystallization occurs in a part of the Si thin film after annealing, a large number of crystal nuclei are irregularly generated in the periphery of the Si thin film.
There is a problem that a Si thin film cannot be obtained.
本発明は、上述の点に鑑みて粒径の大きな単結晶半導
体薄膜が得られる結晶化方法を提供するものである。In view of the above points, the present invention provides a crystallization method capable of obtaining a single crystal semiconductor thin film having a large grain size.
本発明に係る半導体薄膜の結晶化方法においては、絶
縁性基板（１）上に非晶質化した半導体薄膜（３）を形
成する工程と、この非晶質化した半導体薄膜（３）の少
なくとも一部をアニールによって結晶化する工程と、半
導体薄膜の部分的に結晶化した領域、即ち結晶核（４）
上に選択的にマスク層となるホトレジスト層（５）を形
成する工程と、このマスク層（５）で覆われていない部
分の半導体薄膜（３）を再度非晶質化する工程と、半導
体薄膜（３）を改めてアニールによって結晶化する工程
を有する。In the method of crystallizing a semiconductor thin film according to the present invention, a step of forming an amorphized semiconductor thin film (3) on an insulating substrate (1) and at least the amorphized semiconductor thin film (3). A step of crystallizing a part by annealing, and a partially crystallized region of the semiconductor thin film, that is, a crystal nucleus (4)
A step of selectively forming a photoresist layer (5) serving as a mask layer thereon, a step of re-amorphizing a part of the semiconductor thin film (3) not covered with the mask layer (5), and a semiconductor thin film There is a step of crystallizing (3) by annealing again.
非晶質化した半導体薄膜（３）は、絶縁性基板（１）
上に多結晶半導体薄膜（２）を形成した後、適当なイオ
ン注入を行って非晶質化することにより形成しても良
く、又は絶縁性基板（１）上に直接非晶質の半導体薄膜
（３）を形成しても良い。また、結晶核（４）上に選択
的に形成するマスク層は、基板として石英基板（１）を
使用し、結晶核（４）を形成した後、半導体薄膜（３）
上にネガ型ホトレジスト層（５）を形成し、そして石英
基板（１）の裏面側から露光し、現像することにより形
成することができる。The amorphized semiconductor thin film (3) is an insulating substrate (1).
The polycrystalline semiconductor thin film (2) may be formed on the insulating substrate (1) by directly forming the polycrystalline semiconductor thin film (2) on the insulating substrate (1) by performing appropriate ion implantation. (3) may be formed. The mask layer selectively formed on the crystal nuclei (4) uses the quartz substrate (1) as a substrate, and after forming the crystal nuclei (4), the semiconductor thin film (3) is formed.
It can be formed by forming a negative photoresist layer (5) on the upper surface and exposing and developing from the back surface side of the quartz substrate (1).
本発明によれば、先ず非晶質半導体薄膜（３）に部分
的に結晶核（４）が生じた時点でアニールを中断し、次
に結晶核（４）上に形成したホトレジスト層（５）をマ
スクにしてその他の領域を最初の非晶質状態に戻し、こ
の後改めてアニールを施すため、既に生じている結晶核
（４）から優先的に再結晶化が進行し、従来の方法では
得られない大きさを有する単結晶半導体薄膜（７）が得
られる。According to the present invention, the annealing is interrupted when the crystal nuclei (4) are partially generated in the amorphous semiconductor thin film (3), and then the photoresist layer (5) formed on the crystal nuclei (4). Is used as a mask to return the other regions to the initial amorphous state, and then annealing is performed again, so that recrystallization preferentially proceeds from the already existing crystal nuclei (4), which is not obtained by the conventional method. A single crystal semiconductor thin film (7) having a size that cannot be obtained is obtained.
図面を参照して本発明の実施例を説明する。 Embodiments of the present invention will be described with reference to the drawings.
先ず第１図Ａに示すように、石英基板（１）上にCVD
により厚さ約800Åの多結晶（ポリ）Si薄膜（２）を形
成した後、シリコンSi+のイオン注入（例えば２×1015/
cm2、40keV）を行って非晶質（アモルファス）化させ
る。又は、プラズマCVDにより、石英基板（１）上に直
接非晶質Si薄膜を形成しても良い。First, as shown in FIG. 1A, CVD is performed on the quartz substrate (1).
After forming the polycrystalline having a thickness of about 800 Å (poly) Si thin film (2), the silicon Si + ion implantation (e.g., 2 × 10 15 /
cm 2 at 40 keV) to make it amorphous. Alternatively, the amorphous Si thin film may be directly formed on the quartz substrate (1) by plasma CVD.
次に第１図Ｂに示すように、石英基板（１）を炉の中
に配置してアニールを施す。そして、非晶質Si薄膜
（３）に分散して一部結晶化した領域、即ち結晶核
（４）が生じる条件、例えば600℃、５時間の条件でア
ニールを中断する。Next, as shown in FIG. 1B, the quartz substrate (1) is placed in a furnace and annealed. Then, the annealing is interrupted under the condition that the region partially dispersed in the amorphous Si thin film (3) and crystallized, that is, the crystal nucleus (4) is generated, for example, 600 ° C. for 5 hours.
次に第１図Ｃに示すように、Si薄膜（３）の全面にネ
ガ型のホトレジスト層（５）を形成した後、石英基板
（１）の裏面側からｇ線（436nm）（６）を照射する。
この照射の際、第２図に示すように非晶質状態のSI薄膜
の透過率（同図の曲線Ａ参照）が極く僅かであるのに対
して、結晶核（４）が生じた部分のSi薄膜の透過率（同
図の曲線Ｂ参照）が比較的良好であるため、ｇ線（６）
は結晶核（４）を透過して結晶核（４）上のホトレジス
ト層（５）のみを露光することができる。Next, as shown in FIG. 1C, after a negative photoresist layer (5) is formed on the entire surface of the Si thin film (3), a g-line (436 nm) (6) is applied from the back surface side of the quartz substrate (1). Irradiate.
At the time of this irradiation, as shown in FIG. 2, the transmittance of the SI thin film in the amorphous state (see the curve A in the figure) is extremely small, whereas the portion where the crystal nucleus (4) is generated Since the transmittance of the Si thin film of (see curve B in the figure) is relatively good, g-line (6)
Can penetrate the crystal nuclei (4) and expose only the photoresist layer (5) on the crystal nuclei (4).
次に第１図Ｄに示すように、現像処理を施して結晶核
（４）上にホトレジスト層（５）を選択的に形成する。Next, as shown in FIG. 1D, a development process is performed to selectively form a photoresist layer (5) on the crystal nuclei (4).
次に第１図Ｅに示すように、ホトレジスト層（５）が
結晶核（４）上に形成された石英基板（１）に対して、
再びシリコンSi+をイオン注入（例えば、２×1015/c
m2、40keV）する。このイオン注入の際、結晶核（４）
上のホトレジスト層（５）がマスクとなって、ホトレジ
スト層（５）で覆われていない部分のSi薄膜を選択的に
非晶質化させることができる。即ち、この工程により、
上記第１図Ｂのアニール工程で再結晶化までには至って
いないが、完全な非晶質状態ではなくなっている部分の
Si薄膜が最初の非晶質状態に戻る。Next, as shown in FIG. 1E, with respect to the quartz substrate (1) having the photoresist layer (5) formed on the crystal nuclei (4),
Ion implantation of silicon Si + again (eg 2 × 10 15 / c
m 2 , 40keV). During this ion implantation, crystal nuclei (4)
Using the upper photoresist layer (5) as a mask, the Si thin film in the portion not covered with the photoresist layer (5) can be selectively made amorphous. That is, by this process,
In the annealing step shown in FIG. 1B above, although recrystallization has not yet been reached,
The Si thin film returns to the original amorphous state.
次に第１図Ｆに示すように、ホトレジスト層（５）を
除去した後、石英基板（１）を炉内に配置して改めて約
600℃で固相アニールを施す。この固相アニールの際、
元の非晶質状態に戻ったSi薄膜（３）に再結晶化のため
の結晶核が新たに生じる間に、最初のアニールで生じた
結晶核（４）からの再結晶化が優先的に進行するため、
粒径の大きな単結晶薄膜（７）が得られる。Next, as shown in FIG. 1F, after removing the photoresist layer (5), the quartz substrate (1) is placed in a furnace and the
Solid-state annealing is performed at 600 ° C. During this solid phase annealing,
While crystal nuclei for recrystallization are newly generated in the Si thin film (3) which has returned to the original amorphous state, recrystallization from the crystal nuclei (4) generated by the first annealing is preferentially performed. To progress,
A single crystal thin film (7) having a large grain size is obtained.
本発明により、従来法では得られない大きな粒径を有
する単結晶半導体薄膜を得ることが可能になる。The present invention makes it possible to obtain a single crystal semiconductor thin film having a large grain size that cannot be obtained by the conventional method.
第１図Ａ〜Ｆは実施例の工程図、第２図は非晶質状態及
び結晶化状態にあるSi薄膜の波長に対する透過率を測定
したグラフである。 （１）は石英基板、（２）はポリSi薄膜、（３）は非晶
質Si薄膜、（４）は結晶核、（５）はホトレジスト層、
（６）はｇ線、（７）は単結晶薄膜である。1A to 1F are process diagrams of the embodiment, and FIG. 2 is a graph showing the transmittance of Si thin films in the amorphous state and the crystallized state with respect to wavelength. (1) is a quartz substrate, (2) is a poly-Si thin film, (3) is an amorphous Si thin film, (4) is a crystal nucleus, (5) is a photoresist layer,
(6) is a g-line and (7) is a single crystal thin film.
Claims (1)
形成する工程と、 上記非晶質化した半導体薄膜の少なくとも一部を結晶化
する工程と、 上記半導体薄膜の結晶化した領域上に選択的にマスク層
を形成する工程と、 上記マスク層で覆われていない部分の上記半導体薄膜を
再度非晶質化する工程と、 上記半導体薄膜を結晶化する工程 を有する半導体薄膜の結晶化方法。1. A step of forming an amorphized semiconductor thin film on an insulating substrate, a step of crystallizing at least a part of the amorphized semiconductor thin film, and a crystallized region of the semiconductor thin film. Crystallization of a semiconductor thin film, which includes a step of selectively forming a mask layer on the semiconductor layer, a step of re-amorphizing the semiconductor thin film in a portion not covered with the mask layer, and a step of crystallizing the semiconductor thin film. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62029356A JP2550968B2 (en) | 1987-02-10 | 1987-02-10 | Crystallization method of semiconductor thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62029356A JP2550968B2 (en) | 1987-02-10 | 1987-02-10 | Crystallization method of semiconductor thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63196032A JPS63196032A (en) | 1988-08-15 |
| JP2550968B2 true JP2550968B2 (en) | 1996-11-06 |
Family
ID=12273922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62029356A Expired - Fee Related JP2550968B2 (en) | 1987-02-10 | 1987-02-10 | Crystallization method of semiconductor thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550968B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2695466B2 (en) * | 1989-04-28 | 1997-12-24 | キヤノン株式会社 | Crystal growth method |
| JP2695488B2 (en) * | 1989-10-09 | 1997-12-24 | キヤノン株式会社 | Crystal growth method |
| US8465909B2 (en) * | 2009-11-04 | 2013-06-18 | Varian Semiconductor Equipment Associates, Inc. | Self-aligned masking for solar cell manufacture |
-
1987
- 1987-02-10 JP JP62029356A patent/JP2550968B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63196032A (en) | 1988-08-15 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |