JP2540766B2 - Semiconductor container - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor container, and more particularly to a semiconductor container for high frequency hybrid integrated circuits.

[0002]

2. Description of the Related Art An example of a conventional semiconductor container requiring heat dissipation will be described with reference to the drawings. FIG. 3 shows a conventional 900
It is an example of a hybrid integrated circuit of an amplifier for transmitting a MHz band mobile phone.

A substrate 2 made of Al ₂ O ₃ having a thickness of 0.8 mm is provided on a heat sink 1 made of a CuNi alloy having a thickness of 0.5 mm and having a central portion raised from both ends by 0.5 mm.
Was soldered. The convex heat sink 1 is a structure necessary for escaping stress cracks in the substrate. The substrate 2 has a high-frequency copper film circuit on the surface and an F-hole on the substrate.
ET3 was formed, and a high frequency output of 1.6 W was obtained with a power of 5.8 V 400 mA.

Pins 4 were soldered to the substrate 2 for direct current and high frequency connection with an external circuit. The FET 3 and the film circuit on the substrate 2 were soldered by the lead 5 of the FET 3.

In the mixed integrated circuit, both ends of the convex heat sink 1 are connected to the mounting surface 6 of the printed board, for example, by solder 7 to secure electrical grounding and heat dissipation.

[0006]

In the conventional semiconductor container described above, the mounting surface 6 and the heat sink 1 are not connected directly below the FET 3 which is a heating element.
Heat of 1.7W power consumption in 3 is 5m in heat sink 1
The thermal resistance is 24 ° C./W in order to conduct to the mounting surface 6 and escapes to the mounting surface 6, resulting in a temperature increase of 41 ° C. (ΔT≈24 ° C./W×1.7 W).
The joining temperature Ti is 121 ° C. Since the rise in temperature and the life of the product are contradictory, a large FET cannot be used as the FET 3 in the conventional semiconductor container, and there is a limit to the hybrid integrated circuit for high power.

In addition, this kind of high frequency hybrid integrated circuit cannot be applied to the already known heat dissipation technology.

In FIG. 4 (a), the FET chip 8 is attached to the heat sink 1 and is connected to the external circuit board 10 by the bonding wire 9, and heat is provided through the catch 11 to have fins as shown in FIG. 4 (b). In the technique of dissipating by the second heat sink 12 (Japanese Patent Laid-Open No. 58-73141), in the case of the high frequency FET 3, the chip size is 0.8 ×, for example.
The size was as small as 1.3 mm, and the size of the second heat sink 12 was not obtained, which was not effective. Further, there is a drawback that the height of the second heat sink is, for example, 10 mm, and the height of the product as a hybrid integrated circuit is high.

FIG. 5 shows a technique in which a FET chip 8 is mounted on an AlN substrate 13 having a high thermal conductivity on a heat sink with an AuSn solder 14 (Japanese Patent Laid-Open No. 2-1773).
48). The FET chip 8 is connected to the lead 5 via the Ag-5Pd wiring conductor 16 and the Mo conductor layer 17 which are sandwiched by the crystallized glass 15. This technique is excellent in heat dissipation of the FET chip 8 alone, but has a problem that it does not reduce the thermal resistance from the FET 3 to the mounting surface 6 as the high frequency hybrid integrated circuit as described above.

[0010]

The semiconductor container of the present invention comprises:
The bottom surface of the chip mounting substrate has a convex metal plate, and the clamp metal plate is arranged at a position substantially corresponding to the chip. As one specific example, a ceramic semiconductor container in which a gallium arsenide FET chip is housed is made of a metal, and a dielectric substrate having a high-frequency film circuit on the surface thereof is used. Has a structure soldered on the surface, the nuclear metal plate has a bent convex shape, the FET is located on the convex top of the nuclear metal plate surface,
A crank-shaped pawl is provided on the back surface of the nucleus top, and the end of the convex metal flat plate and the end of the crank-shaped pawl are flush with each other, and the nuclear crank-shaped pawl forms an angle of 0 <θ ≦ 45 ° with respect to the horizontal plane. It has the structure that

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1A is a plan view of a hybrid integrated circuit according to a first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA 'in FIG. 1A.
Sectional view, FIG. 1 (c) is a side view of FIG. 1 (a), FIG. 1 (d)
FIG. 3 is a back view of FIG.

On a heat sink 1 made of a CuNi alloy having a thickness of 0.5 mm and having a convex shape, Al ₂ having a thickness of 0.8 mm is formed.
The substrate 2 made of O ₃ and the FET _{3 in} the hole of the substrate 2 are soldered. The heat sink 1 is, for example, 20 × 11
mm, 2 mm width and 0.5 mm thickness directly under the FET3
Crank-shaped heat sink claws 18 made of copper are welded to the heat sink 1. Pins 4 are mounted on the substrate 2 by biting and soldering for direct current and high frequency connection with an external circuit, forming a hybrid integrated circuit through the film circuit on the substrate 2 and the leads 5 of the FET 3. . The heat sink 1 and the heat sink claw 18 are flush with the mounting surface 6, and the heat sink claw 18 is in contact with the mounting surface 6 at an angle of, for example, 5 °. The pin 4 is located at a position higher than the mounting surface 6 by an external substrate thickness of 0.6 mm made of, for example, glass epoxy. Mounting surface 6 and heat sink claw 18
The angle θ with is 0 <θ <45 ° because the connection with the mounting surface 6 is ensured by utilizing the spring property of the heat sink claw 18.
To make. Further, the heat sink claw 18 is connected to the mounting surface 6 together with the heat sink 1 by solder reflow.

FIG. 2A is a plan view of the hybrid integrated circuit of the second embodiment of the present invention, and FIG. 2B is a sectional view taken along the line BB '.

Similar to the first embodiment, a substrate 2 made of, for example, Al ₂ O _{3 having} a thickness of 0.8 mm and a FET _{3 in} a hole of the substrate 2 are soldered on the convex heat sink 1. The heat sink 1 is, for example, 20 × 11 mm, and has a heat sink claw 18 structure in which a portion 1 mm laterally below the FET 3 has a length of 2 mm and a width of 1 mm and is bent like a crank in the mounting surface 6 direction. The heat sink claw 18 has an angle θ of, for example, 5 ° and is in contact with the mounting surface 6.

FIG. 6 is an explanatory diagram of thermal resistance using the FET 3 as the heat source 19. The heat generated in the FET 3 is transmitted to the mounting surface 6 through the heat sink. Equivalently, from FET3 to FIG.
If the distances are L ₁ and L _{2 in the} left and right directions, Rth = Rt
h ₁ // Rth ₂ , Rth ₁ = (L ₁ / L ₂ ) Rth ₂
For example, Rth ₁ = 60 ° C./W, L ₁ = 12 mm, L ₂
= 8 mm, the total thermal resistance Rth = 24 ° C./W, and the heat sink claws 18 of the present invention make Rth ₃ = 160.
The total thermal resistance Rth≈19 ° C./W is obtained by ° C / W.

[0017]

As described above, according to the present invention, since the heat sink claw 18 is provided, the heat conduction claw 18 is inserted between the FET 3 and the mounting surface 6 so that the heat conduction path is short-circuited. For example, in the heat sink claw 18 having a width of 1 mm, the effect of reducing the thermal resistance from the FET 3 to the mounting surface 6 from 20 ° C./W to 16 ° C./W,
The grounded source inductance of the FET3 is, for example, 2.0n
Since it is reduced from H to 1.6 nH, it is possible to suppress the rotation of the S parameter in the frequency band of the S band to the C band, and the effect that the stability coefficient K <1 region as the hybrid integrated circuit is wide and stable operation is possible. There is.

Since the heat sink claw 18 is thin, for example, having a width of 1 mm, it is not possible to prevent the stress on the substrate 2 from being reduced by making the heat sink 1 convex.

[Brief description of drawings]

FIG. 1A is a plan view of a first embodiment of the present invention,
1B is a cross-sectional view taken along the line AA 'in FIG. 1A, FIG. 1C is a side view of FIG. 1A, and FIG. 1D is a rear view of FIG.

FIG. 2A is a plan view of a second embodiment of the present invention,
2B is a sectional view taken along the line BB ′ of FIG.

FIG. 3A is a plan view showing an example of a conventional hybrid integrated circuit;
FIG. 1B is a side view of FIG.

FIG. 4A is a perspective view of a conventional chip heat dissipation technology example,
FIG. 4B is a perspective view in which the second heat sink is attached to FIG.

FIG. 5 is a cross-sectional view of a conventional chip heat dissipation technology example using AlN.

FIG. 6A is a side view for explaining the thermal resistance, and FIG.
Is an equivalent circuit diagram of FIG.

[Explanation of symbols]

 1 1st heat sink 2 board 3 FET 4 pin 5 lead 6 mounting surface 7 solder 8 FET chip 9 bonding wire 10 external circuit board 11 receiving 12 second heat sink 13 AlN board 14 AuSn solder 15 crystallized glass 16 Ag-5Pd wiring Conductor 17 Mo Conductor Layer 18 Heat Sink Claw 19 Heat Source

Claims (3)

(57) [Claims] In a semiconductor container, a front surface of a first metal plate bent in a convex shape is connected to a back surface of a substrate on which a semiconductor chip is mounted, and a second metal bent in a crank shape in a semiconductor container. A plate is provided on the back surface of the first metal plate, and
The end of the first metal plate and the end of the second metal plate are flush with each other.
Forming a semiconductor container. 2. A convex on the back surface of a substrate on which a semiconductor chip is mounted.
Semiconductor container having a first metal plate bent into a shape
In, the second metal plate bent in the crank shape
It is provided at a position substantially corresponding to the chip, the end of the first metal plate and the end of the second metal plate are flush with each other, and the end of the second metal plate is horizontal. Angle 0
A semiconductor container characterized by a structure having <θ ≦ 45 ° directions. 3. The semiconductor container according to claim 1, wherein the semiconductor chip is located in a through hole provided in the substrate and is in direct contact with the second metal plate.