JP2539667Y2 - デューティ可変回路 - Google Patents
デューティ可変回路Info
- Publication number
- JP2539667Y2 JP2539667Y2 JP1988079383U JP7938388U JP2539667Y2 JP 2539667 Y2 JP2539667 Y2 JP 2539667Y2 JP 1988079383 U JP1988079383 U JP 1988079383U JP 7938388 U JP7938388 U JP 7938388U JP 2539667 Y2 JP2539667 Y2 JP 2539667Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- mos transistor
- clock
- channel mos
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988079383U JP2539667Y2 (ja) | 1988-06-15 | 1988-06-15 | デューティ可変回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988079383U JP2539667Y2 (ja) | 1988-06-15 | 1988-06-15 | デューティ可変回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH021924U JPH021924U (cs) | 1990-01-09 |
| JP2539667Y2 true JP2539667Y2 (ja) | 1997-06-25 |
Family
ID=31304268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988079383U Expired - Lifetime JP2539667Y2 (ja) | 1988-06-15 | 1988-06-15 | デューティ可変回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2539667Y2 (cs) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002035740A1 (en) * | 2000-10-26 | 2002-05-02 | Fujitsu Limited | Pulse width control circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5002964B2 (ja) * | 2006-01-20 | 2012-08-15 | ソニー株式会社 | 遅延回路及びそれを備えたアナログ/デジタルコンバータ回路 |
| US9379722B2 (en) * | 2013-06-25 | 2016-06-28 | Qualcomm Incorporated | Frequency divider with duty cycle adjustment within feedback loop |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5961312A (ja) * | 1982-09-30 | 1984-04-07 | Toshiba Corp | パルス遅延回路 |
-
1988
- 1988-06-15 JP JP1988079383U patent/JP2539667Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002035740A1 (en) * | 2000-10-26 | 2002-05-02 | Fujitsu Limited | Pulse width control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH021924U (cs) | 1990-01-09 |
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