JP2526566Y2 - 半導体装置の実装基板 - Google Patents

半導体装置の実装基板

Info

Publication number
JP2526566Y2
JP2526566Y2 JP1990076378U JP7637890U JP2526566Y2 JP 2526566 Y2 JP2526566 Y2 JP 2526566Y2 JP 1990076378 U JP1990076378 U JP 1990076378U JP 7637890 U JP7637890 U JP 7637890U JP 2526566 Y2 JP2526566 Y2 JP 2526566Y2
Authority
JP
Japan
Prior art keywords
mounting
semiconductor element
bonding wire
metallized
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1990076378U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0434741U (US20030220297A1-20031127-C00074.png
Inventor
広之 中川
孝仁 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1990076378U priority Critical patent/JP2526566Y2/ja
Publication of JPH0434741U publication Critical patent/JPH0434741U/ja
Application granted granted Critical
Publication of JP2526566Y2 publication Critical patent/JP2526566Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
JP1990076378U 1990-07-18 1990-07-18 半導体装置の実装基板 Expired - Lifetime JP2526566Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990076378U JP2526566Y2 (ja) 1990-07-18 1990-07-18 半導体装置の実装基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990076378U JP2526566Y2 (ja) 1990-07-18 1990-07-18 半導体装置の実装基板

Publications (2)

Publication Number Publication Date
JPH0434741U JPH0434741U (US20030220297A1-20031127-C00074.png) 1992-03-23
JP2526566Y2 true JP2526566Y2 (ja) 1997-02-19

Family

ID=31617794

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990076378U Expired - Lifetime JP2526566Y2 (ja) 1990-07-18 1990-07-18 半導体装置の実装基板

Country Status (1)

Country Link
JP (1) JP2526566Y2 (US20030220297A1-20031127-C00074.png)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007329502A (ja) * 2007-08-16 2007-12-20 Toshiba Corp 発光装置
JP4403199B2 (ja) * 2008-11-17 2010-01-20 株式会社東芝 発光装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63198341A (ja) * 1987-02-13 1988-08-17 Nec Corp 半導体装置
JPH0648874Y2 (ja) * 1988-10-26 1994-12-12 富士電機株式会社 半導体装置

Also Published As

Publication number Publication date
JPH0434741U (US20030220297A1-20031127-C00074.png) 1992-03-23

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Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term