JP2518721Y2 - 半導体素子収納用パッケージ - Google Patents

半導体素子収納用パッケージ

Info

Publication number
JP2518721Y2
JP2518721Y2 JP7565590U JP7565590U JP2518721Y2 JP 2518721 Y2 JP2518721 Y2 JP 2518721Y2 JP 7565590 U JP7565590 U JP 7565590U JP 7565590 U JP7565590 U JP 7565590U JP 2518721 Y2 JP2518721 Y2 JP 2518721Y2
Authority
JP
Japan
Prior art keywords
semiconductor element
organic resin
resin adhesive
container
external lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7565590U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0434747U (enrdf_load_stackoverflow
Inventor
浩一郎 野元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP7565590U priority Critical patent/JP2518721Y2/ja
Publication of JPH0434747U publication Critical patent/JPH0434747U/ja
Application granted granted Critical
Publication of JP2518721Y2 publication Critical patent/JP2518721Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP7565590U 1990-07-16 1990-07-16 半導体素子収納用パッケージ Expired - Lifetime JP2518721Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7565590U JP2518721Y2 (ja) 1990-07-16 1990-07-16 半導体素子収納用パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7565590U JP2518721Y2 (ja) 1990-07-16 1990-07-16 半導体素子収納用パッケージ

Publications (2)

Publication Number Publication Date
JPH0434747U JPH0434747U (enrdf_load_stackoverflow) 1992-03-23
JP2518721Y2 true JP2518721Y2 (ja) 1996-11-27

Family

ID=31616422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7565590U Expired - Lifetime JP2518721Y2 (ja) 1990-07-16 1990-07-16 半導体素子収納用パッケージ

Country Status (1)

Country Link
JP (1) JP2518721Y2 (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0434747U (enrdf_load_stackoverflow) 1992-03-23

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term