JP2516390Y2 - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JP2516390Y2 JP2516390Y2 JP1987195253U JP19525387U JP2516390Y2 JP 2516390 Y2 JP2516390 Y2 JP 2516390Y2 JP 1987195253 U JP1987195253 U JP 1987195253U JP 19525387 U JP19525387 U JP 19525387U JP 2516390 Y2 JP2516390 Y2 JP 2516390Y2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor chip
- outer frame
- leads
- metal foil
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987195253U JP2516390Y2 (ja) | 1987-12-23 | 1987-12-23 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987195253U JP2516390Y2 (ja) | 1987-12-23 | 1987-12-23 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01100457U JPH01100457U (https=) | 1989-07-05 |
| JP2516390Y2 true JP2516390Y2 (ja) | 1996-11-06 |
Family
ID=31485939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987195253U Expired - Lifetime JP2516390Y2 (ja) | 1987-12-23 | 1987-12-23 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2516390Y2 (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010097511A (ko) * | 2000-04-24 | 2001-11-08 | 이중구 | 이층형 칩 스케일 반도체 팩키지 및, 그것의 제조 방법 |
-
1987
- 1987-12-23 JP JP1987195253U patent/JP2516390Y2/ja not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010097511A (ko) * | 2000-04-24 | 2001-11-08 | 이중구 | 이층형 칩 스케일 반도체 팩키지 및, 그것의 제조 방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01100457U (https=) | 1989-07-05 |
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