JP2510972B2 - Bidirectional thyristor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bidirectional semiconductor device, and more particularly to a semiconductor device for AC switching having a five-layer structure in which conductivity types are alternately different.

[Technical Background of the Invention] A semiconductor device for alternating current switching having a five-layer structure with alternating conductivity types is usually called a triac, and as shown in FIG. A semiconductor substrate having a five-layer structure of n has a main electrode (T ₁ ) and a gate electrode (G) on one surface and a main electrode (T ₂ ) on the other surface.

This semiconductor device has a function of shifting from an off state to an on state by a signal input to the gate electrode (G) and controlling AC power. The firing mode is the main electrode (T ₁ ),
There are the following four types depending on the combination of the bias direction between (T ₂ ) and the bias directions of the main electrode (T ₁ ) and the gate electrode (G).

I Mode: main electrodes (T ₁₎ to the main electrodes (T ₂₎ a positive voltage is applied to, I-mode add positive signal to the gate electrode (G) to simultaneously main electrodes (T _1): main electrode (T ₁₎ to a positive voltage is applied to the main electrode (T _2), III-mode add negative signal to the gate electrode (G) to the main electrodes (T ₁₎ at the same time: the main electrode (T ₁₎ In contrast, a negative voltage is applied to the main electrode (T ₂ ), and at the same time a positive signal is applied to the gate electrode (G) with respect to the main electrode (T ₁ ). III mode: Main electrode (T ₁ ) with respect to the main electrode (T ₁ ). ₂ ) Apply a negative voltage to the main electrode (T ₁ ) and apply a negative signal to the gate electrode (G) at the same time. Of these four modes, the ones that are normally used are 3 except the III mode. Two of the street modes. Due to the complexity of the ignition mechanism, the III mode has not been used in the past because the gate current required for ignition is much larger than other modes.

However, recently, there has been a demand for a semiconductor device capable of driving four modes including the III mode, and particularly, I and III.
It is desired to realize direct drive of triac by IC using mode. For that purpose, it is necessary to reduce the gate current, which used to be about 10 to 20 mA, to about 5 mA, to make the gate trigger characteristic highly sensitive.

By the way, since the triac can be considered to be composed of two thyristors that are equivalently connected in anti-parallel, half of the P-type regions (P ₁ ) and (P ₂ ) in FIG. A relatively high concentration of diffusion is required for the anode region of the thyristor, but the other half is
Since it corresponds to another thyristor P base and N emitters are diffused therein, it is desirable that the concentration is lower than that of the anode. However, in the past, there was no requirement for a trigger function in the III mode, and it was not necessary to make the sensitivity extremely high for other trigger modes as well.
The P-type regions (P ₁ ) and (P ₂ ) were formed simultaneously and at the same concentration. That is, conventionally, P-type impurities are simultaneously adhered to both surfaces of an N-type semiconductor substrate and diffused into the inside of the substrate to form P-type regions (P ₁ ) and (P ₂ ).
The P-type region (P _1), depositing the respective N-type impurity in a part of (P _2), these P-type regions (P _1), depositing the N-type impurity respectively in a portion of (P ₂₎ , N-type regions (N _E1 ), (N _E2 ), and (N _EG ) were formed by diffusing these to a predetermined depth in the P-type regions (P ₁ ) and (P ₂ ).

However, in order to make the triac with high sensitivity in the III mode and the trig with high sensitivity in all modes, various restrictions are caused in the conventional structure, and the control such as diffusion is difficult in the manufacturing process. It's extremely difficult.

[Object of the Invention] An object of the present invention is to enhance the sensitivity of the gate trigger characteristic, particularly the trigger characteristic in the III mode, without damaging the basic characteristics of the triac.

[Summary of the Invention] A semiconductor substrate having different conductivity type layers alternately stacked, and a first conductivity type first substrate formed on one surface of the semiconductor substrate.
A surface layer, a second conductive type first intermediate layer adjacent to and continuous with the surface of the semiconductor substrate, and a first PN junction formed by the first surface layer and the second conductive type first intermediate layer , A first PN junction end exposed on the second intermediate layer of the first conductivity type, a first PN junction flat portion connected to the first PN junction end and formed along the surface of the semiconductor substrate, and the first PN junction A low-concentration layer provided on the first intermediate layer portion of the second conductivity type facing a flat portion, a high-concentration layer adjacent to and continuous with the first intermediate layer portion, and forming a large depth, the first PN junction end portion and the second conductivity layer. Type 1
A first main electrode formed over the intermediate layer, a second surface layer of the first conductivity type formed in the exposed portion of the first intermediate layer of the second conductivity type separated from the first surface layer, and The gate electrode connecting the exposed portion of the second surface layer and the first intermediate layer of the second conductivity type, and the one portion of the first surface layer in the projected portion of the one surface of the semiconductor substrate obtained on the other surface of the semiconductor substrate. And a part of the second surface layer are overlapped with each other to form a third surface layer of the first conductivity type, and a second intermediate layer of the second conductivity type that is adjacent to and continuous with the third surface layer and forms the other surface of the semiconductor substrate. And this second conductivity type second
An intermediate layer of the first conductivity type adjacent to and continuous with the intermediate layer, and a second P formed between the second intermediate layer and the third surface layer of the first conductivity type
An N junction, a second PN junction end exposed at a second intermediate layer portion of the second conductivity type constituting the other surface of the semiconductor substrate, and the second PN junction end portion.
A second PN junction flat portion connected to the PN junction end portion and formed along the other surface of the semiconductor substrate; and a second main electrode connecting the second PN junction end portion and the second conductive type second intermediate layer A low concentration layer formed in a second intermediate layer portion of the second conductive type located between the third surface layer and the intermediate layer of the first conductive type and a high concentration layer of another portion, the first main electrode -First surface layer of the first conductivity type-Low concentration layer formed in the first intermediate layer of the second conductivity type-Low concentration of the intermediate layer of the first conductivity type and the second intermediate layer portion of the second conductivity type Layer-a conductive path composed of the third surface layer of the first conductivity type, the second main electrode, a high-concentration layer of the second intermediate layer portion of the second conductivity type-the intermediate layer of the first conductivity type-the above The bidirectional service according to the present invention is characterized in that the conductive paths composed of the low-concentration layer formed on the first intermediate layer of the second conductivity type and the first surface layer of the first conductivity type are alternately used. There is a feature of the lister.

Embodiments of the Invention Hereinafter, the present invention will be described based on embodiments with reference to the drawings.

FIG. 1 shows an example of a triac having a planar structure.
In this semiconductor device, the same N-type first and second surface layers (N _E1 ), (N _EG ) are provided on one surface of an N-type semiconductor substrate and are separated from each other, and these first and second surfaces are also provided. Layer (N _E1 ), (N _EG )
A P-type first intermediate layer exposed portion (P ₁ ) is provided so as to surround, and a third surface layer (N _E2 ) having the same conductivity type as the first surface layer (N _E1 ) is provided on the other surface. As indicated by the broken line (1) in the drawing, a part of it overlaps the projected portion of the first surface layer (N _E1 ), and further overlaps the projected portion of the second surface layer (N _EG ). 3 the surface layer (n _E2) as the intermediate layer exposed portion surrounding the (P ₁₎ and the second intermediate layer exposed portion of the same conductivity type (P ₂₎ is provided, as a whole n-p-n-p- n of 5
It is formed in a layered structure. Moreover, the first intermediate layer adjacent to the first surface layer (N _E1 ) on the side of the third surface layer N _E2 is
The impurity concentration is lower than the first intermediate layer exposed portion (P ₁ ) adjacent to the second surface layers (N _E1 ) and (N _EG ) and the diffusion depth is shallow. In addition, the first surface layer (N _E2 ) is formed on the third surface layer (N _E2 ).
The second intermediate layer adjacent to _E1) side, smaller than the impurity concentration and the depth of the diffusion and summer shallow the third surface layer (a second intermediate layer exposed portion adjacent to the N _E2) (P ₂₎ . In addition, the first surface layer (N _E1 ) and the first intermediate layer exposed portion (P ₁ ) and the second surface layer (N _EG ) and the first intermediate layer exposed portion (P ₁ ) are formed on one surface of the substrate. First, connecting each sky
The main electrode (T ₁ ) and the gate electrode (G) are provided, and the second main electrode (T ₂ ) that connects the third surface layer (N _E2 ) and the second intermediate layer exposed portion (P ₂ ) is provided on the other surface. ₂ ) is provided.

This semiconductor device can be manufactured as follows.

First, as shown in FIG. 2 (a), isolation diffusion is applied to an N-type semiconductor substrate to form a P-type region (2) for separating into individual elements. Next, as shown in FIG. 2B, a certain region surrounded by the P region (2) on one surface of the substrate and a boundary region with the P region (2) on the other surface are crossed,
P-type impurities are deposited at 1100 ° C. to form a shallow diffusion layer (3). After oxidizing the surface of the diffusion layer (3), a temperature lower than the impurity attachment temperature when the diffusion layer (3) is formed in the region (4) between the diffusion layers (3) on each surface,
For example, P-type impurities are deposited at 950 ° C. to form a shallow diffusion layer (5) as shown in FIG. After that, an oxide film is formed on the entire surface and processed at a high temperature of 1200 ° C or higher,
(D) As shown in the figure, diffuse deeply to a predetermined depth,
P-type diffusion layers (3a) and (5a) corresponding to the first and second intermediate layer exposed portions (P ₁ ) and (P ₂ ) and the first and second intermediate layers are formed. Diffusion layers (5a) formed on both sides of this substrate
Is formed so that one of the projected portions overlaps the other, and the impurity concentration is smaller than that of the adjacent diffusion layer (3a), and the diffusion depth is shallow due to this difference in impurity concentration. Next, diffusion layers (3a) formed on both sides of this substrate
An N-type impurity is attached to a predetermined area of (5a) and diffused to a predetermined depth as shown in (e), and N-type first and second surface layers (N _E1 ) are formed on one surface of the substrate. , (N _EG ) and a third surface layer (N _E2 ) is formed on the other surface of the substrate so that a part thereof overlaps the projected portion of the first surface layer (N _E1 ). After that, an oxide film formed on one surface of the substrate is opened so as to extend over the first surface layer (N _E1 ) and the diffusion layer (3a) respectively, and the oxide film on the other surface is removed to form these holes. Then, a metal film is deposited on the other surface to form the first and second main electrodes (T ₁ ) and (T ₂ ) and the gate electrode (G) as shown in FIG.

When the triac is configured as described above, the gate trigger characteristic in each firing mode including the III mode can be made highly sensitive. That is, the triac ignition mechanism in the III mode is such that a gate current flows laterally in the first intermediate layer from the gate electrode (G) to the first main electrode (T ₁ ) to generate N _E1 −P ₁ Injection of electrons starts from a portion of the junction near the gate electrode (G). Then, the electrons reach the n ⁻ region, reduce the potential of this portion, forward bias the junction composed of P ₁ —N, and holes are injected from the first intermediate layer to the n ⁻ region. The holes diffuse in the n ⁻ region, reach the second intermediate layer, and finally flow into the second main electrode (T ₂ ). In this case, if the second surface layer (N _EG ) of the first surface layer (N _E1 ) where injection of electrons is started is formed so as to overlap a part of the third surface layer (N _E2 ), the n ⁻ region The holes that have diffused into the second intermediate layer and reach the second intermediate layer laterally flow in this overlapping portion in the second intermediate layer so as to avoid the third surface layer (N _E2 ). At this time, due to the lateral resistance of this overlapping part,
In the second intermediate layer, a lateral voltage drop occurs, which is partially P ₂
The junction made of -N _E2 is forward biased and electrons are injected from the third surface layer (N _E2 ) to the second intermediate layer. The electrons diffuse the second intermediate layer n ^- enter the region, n ^- lowering the potential of the region with respect to the first intermediate layer. Through this series of operations, each junction is strongly forward-biased, the thyristor composed of P ₁ -N ^-- P ₂ -N _E2 is turned on, and ignition by the III mode is started.

In contrast to this ignition mode, in the triac of this embodiment, the concentration of the diffusion layer (5a) formed by diffusing P-type impurities is lower than that of the other P-type diffusion layer (3a). A P-N junction between the first and third surface layers (N _E1 ), (N _E2 ) formed by diffusing N-type impurities can be performed with high injection efficiency, and gate trigger characteristics in the III mode Could be made highly sensitive.

Further, since the diffusion layer (5a) has a low concentration, there is also a manufacturing advantage that the gate sensitivity is not easily affected by the dispersion of diffusion of the first and third surface layers (N _E1 ) and (N _E2 ).

Further, by forming the diffusion layer (3a) at a higher concentration than that of the diffusion layer (3a), there is an advantage that deep diffusion can be performed in a short time.

Further, since the deep diffusion layer (3a) is formed so as to surround the diffusion layer (5a) and has a large curvature required at the end of the planar structure, its breakdown voltage can be increased, and the reliability of the equipment used can be improved. Can be increased.

EFFECTS OF THE INVENTION A third surface layer is formed on the other surface of the semiconductor substrate so as to partially overlap the projected portion of the first surface layer formed on the one surface, and the third surface layer is formed on the first surface layer side. Since the concentration of the second intermediate layer adjacent to the third surface layer is set to be smaller than the concentration of the exposed portion of the second intermediate layer adjacent to the third surface layer, the gate trigger characteristic in the III mode can be made highly sensitive.

[Brief description of drawings]

FIG. 1 is a diagram of a triac having a planar structure according to an embodiment of the present invention, FIGS. 2 (a) to 2 (e) are diagrams for explaining a manufacturing method of the triac shown in FIG. 1, and FIG. 3 is a diagram of a conventional triac. Is. (G) …… Gate electrode, (N _E1 ) …… First surface layer (N _E2 ) …… Third surface layer, (N _EG ) …… Second surface layer (P ₁ ) …… First intermediate layer exposed Part (P ₂ ) ... 2nd intermediate layer exposed part (T ₁ ) ... 1st main electrode, (T ₂ ) ... 2nd main electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shinichi Matsumoto 70 Minowa, Kimitsu city Kimitsu factory Toshiba Components Co., Ltd. (56) Reference JP 57-196569 (JP, A) JP 55- 124262 (JP, A) JP 56-150862 (JP, A) JP 58-188161 (JP, A)

Claims (1)

(57) [Claims] 1. A semiconductor substrate having layers of different conductivity type alternately stacked, a first surface layer of a first conductivity type formed on one surface of the semiconductor substrate, and a surface of the semiconductor substrate adjacent to and continuous with the first surface layer. A first intermediate layer of the second conductivity type, a first PN junction formed by the first surface layer and the first intermediate layer of the second conductivity type, and a first intermediate layer of the second conductivity type exposed. A 1PN junction end portion, a first PN junction flat portion connected to the first PN junction end portion and formed along the surface of the semiconductor substrate, and the second intermediate layer of the second conductivity type facing the first PN junction flat portion A low-concentration layer provided in a portion, a high-concentration layer adjacent to and continuous with the high-concentration layer and forming a large depth, and a first concentration layer formed across the first PN junction end and the first intermediate layer of the second conductivity type. A second table of the first conductivity type formed on the exposed portion of the first intermediate layer of the second conductivity type separated from the main electrode and the first surface layer. A layer, a gate electrode connecting the second surface layer and an exposed portion of the first intermediate layer of the second conductivity type, and the first electrode in a projected portion of the one surface of the semiconductor substrate obtained on the other surface of the semiconductor substrate. A third surface layer of the first conductivity type formed by overlapping a part of the surface layer and a part of the second surface layer, and a second surface layer of the second conductivity type which is adjacent to and continuous with the third surface layer and constitutes the other surface of the semiconductor substrate. A second intermediate layer and a first conductive type intermediate layer adjacent to and continuous with the second conductive type second intermediate layer;
A second PN junction formed between the second intermediate layer and the third surface layer of the first conductivity type, and a second PN junction forming the other surface of the semiconductor substrate.
A second PN junction end exposed at the conductive second intermediate layer portion;
A second PN junction flat portion connected to the second PN junction end portion and formed along the other surface of the semiconductor substrate, and a second main portion connecting the second PN junction end portion and the second conductivity type second intermediate layer. An electrode, a low-concentration layer formed in a second conductive-type second intermediate layer portion located between the third surface layer and the first conductive-type intermediate layer, and a high-concentration layer in another portion, Main electrode-first surface layer of first conductivity type-low concentration layer formed on first intermediate layer of second conductivity type-intermediate layer of first conductivity type and second intermediate layer portion of second conductivity type Low-concentration layer-conducting path composed of the third surface layer of the first conductivity type, the second main electrode-high concentration layer of the second intermediate layer portion of the second conductivity type-intermediate layer of the first conductivity type −
A bidirectional thyristor characterized by alternately using a conductive path composed of a low-concentration layer formed in the first intermediate layer of the second conductivity type and the first surface layer of the first conductivity type.