JP2505184B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having an MIS or MOS structure such as MOSFET formed on a semiconductor substrate, and more particularly to a highly reliable semiconductor device of this type.

[Conventional technology]

In recent years, with the progress of fine processing technology in semiconductor devices such as MPSFET, the gate length has been remarkably miniaturized, and thereby the integration degree and performance of integrated circuits composed of MOSFET have been dramatically improved. However, as the miniaturization of gates progresses, many problems have arisen. For example, there are a decrease in reliability such as characteristic deterioration due to the photocarrier effect, a decrease in withstand voltage between source and sorain, a shot channel effect, and the like, which are serious problems in a MOSFET having a gate length of 2 μm or less to submicron. Among these, the characteristic deterioration due to the photocarrier effect is remarkable in the n-channel MOSFET.
ET will be described as an example.

As the most well-known conventional technique as a solution to the characteristic deterioration of MOSFET due to the hot carrier effect, for example, the Institute of Electronics and Communication Engineers, April 1978 (Proceedings p220).
LDD (Lightly Doped Drain) structure MOSFET proposed by
It has been known.

FIG. 7 is a diagram showing the structure of a MOSFET according to this conventional technique. In FIG. 7, 1 is a p-type substrate, 2 is a gate oxide film, 3 is a gate, 4 is an n-type low concentration layer, and 5 is a sidewall. , 6 are source and drain diffusion layers, 7 is a protective insulating layer, and 8 is source and drain electrodes.

The LDD structure MOSFET (hereinafter referred to as LDDMOSFET) shown in FIG. 7 is characterized in that an offset region formed by the n-type low concentration layer 4 is provided between the source and drain diffusion layers 6 and the channel region formed below the gate 3. It is provided. In this LDD MOSFET, ion implantation for forming the n-type low-concentration layer 4 is performed by using the gate 3 provided on the p-type substrate 1 with the gate oxide film 2 interposed as a mask, and then the sidewall made of a silicon oxide film is used. 5 is formed, and then ion implantation is performed for the source and drain diffusion layers 6 to form an n-type high-concentration layer. Regarding the manufacturing method, for example, IEEE JOURNAL OF SOLID-STATE C
IRUITS, VOL.SC-17, No2, APRIL 1982 P220 to P226.

In this LDDMOSFET, the introduction of the n-type low-concentration layer relaxes the electric field near the drain and reduces the width of the sky layer that extends from the drain in the channel direction. Effective against That is, the LD according to the related art
Compared with a single-drain structure MOSFET, the DMOSFET has less characteristic deterioration due to photocarriers, and high reliability can be secured even in a MOSFET with a shorter gate length. This is, for example, Spring 1985, 32nd Japan Society of Applied Physics, Proceedings (page 555, article number 1p-E-11).
Has been reported in. According to this paper, the critical gate length that ensures sufficient reliability is
2.3μm for SFET, 1.0μ for LDDMOSFET
m.

[Problems to be solved by the invention]

However, the LDDMOSFET according to the above-mentioned conventional technique has a problem in that, when the gate length is further shortened, the characteristics due to photocarriers are significantly deteriorated, and it is difficult to maintain reliability. Several models have been proposed for the degradation mechanism of the MOSFET due to the hot carrier when the gate length is shortened. The degradation mechanism peculiar to the LDD MOSFET in the models will be described with reference to the drawings.

FIGS. 8A and 8B are views for explaining the deterioration mechanism of the LDD MOSFET. In this figure, 9, 10 and 12 are electrons and 11 is a hole, and other symbols are the same as in the case of FIG.

In the MOSFET, a strong electric field exists at the drain end,
As shown in FIG. (A), the electrons 9 accelerated here generate electron-hole pairs of electrons 10 and holes 11,
The electrons pass through the potential barrier of the gate oxide film 2 and enter the side wall 5 to be captured as shown in FIG. 8 (B). Because of this captured electron 12,
The side wall 5 is negatively charged, the electrons in the n-type example concentration layer 4 decrease near the gate oxide film 2, that is, near the surface, and the resistance of this portion increases. This allows the MOSFET
The gm will be effectively reduced. As described above, the LDD MOSFET according to the related art has a limit in securing reliability when the gate length is shortened, and there is a problem that the reliability cannot be secured when the gate length is a certain length or less.

An object of the present invention is to provide a MOSFET semiconductor device having a higher photocarrier withstand capability than the LDDMOSFET according to the prior art.

[Means for solving problems]

According to the present invention, the above-mentioned object is to make the sidewall provided on the side surface of the gate conductive so that the electrical resistivity thereof is 1 Ω.
It is achieved by setting the value between cm and 1 × 10 ⁶ Ω · cm and connecting this sidewall to a specific potential.

[Action]

By making the sidewall conductive and connecting it to a specific potential, for example, a gate electrode, the electrons taken into the sidewall can be discharged through the gate electrode. In this case, the resistivity of the sidewall is 1Ω · cm
By appropriately setting it to about 1 × 10 ⁶ Ω · cm, it is possible to make it almost unaffected by the parasitic capacitance existing between the sidewall and the offset region forming a part of the drain diffusion layer. That is, the resistance in the side wall along the electron discharge path is set to a certain level or more by selecting the resistivity of the side wall,
If the time constant due to this resistance and the parasitic capacitance is set longer than the cycle in which the MOSFET element actually operates, the delay in circuit operation due to the parasitic capacitance can be ignored. On the other hand, electrons that are hot carriers are injected only when the gate is at a high level, and if this period is long, more electrons are taken into the side wall, but because the side wall is conductive, The taken-in electrons are gradually absorbed by the gate and are not excessively accumulated in the side wall, so that performance deterioration such as gm reduction of the LDD MOSFET does not occur.

〔Example〕

Hereinafter, an embodiment of a semiconductor device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an MO which is an embodiment of a semiconductor device according to the present invention.
FIG. 2 is a diagram showing the structure of the SFET, and FIG. 2 is a diagram illustrating a mechanism capable of reducing characteristic deterioration according to the present invention. In FIGS. 1 and 2, 51 is a side wall, and other reference numerals are the same as those in the prior art shown in FIG.

As in the case of the prior art, the MOSFET according to the present invention has an offset region formed by the n-type low concentration layer 4 formed between the source and drain diffusion layers 6 and the channel region formed under the gate 3. The side wall 51 formed in contact with the gate 3 constitutes the structure shown in FIG. The difference between this MOSFET and the prior art is that the side wall 51 has conductivity and is connected to a specific potential V. The resistivity of the side wall 51 is 1Ω
· Cm to 1 Set × 10 ⁶ Ω · cm, as the material, doped with suppressing original containing polysilicon intrinsic Shitsuku or low impurity concentration, or oxygen, nitrogen, the diffusion of other impurities such as carbon Polysilicon or the like can be used.

In the MOSFET according to the present invention, the side wall 51 has conductivity and is connected to a specific potential V as described above. Therefore, the electrons taken in the side wall 51 are connected by the mechanism described with reference to FIG. Can be discharged to this particular potential. Further, the material having the resistivity of the above-mentioned magnitude is used for the side wall 51 so that the side wall 51 does not act as a gate when the side wall 51 is connected to a specific potential connection point, for example, the gate 3. To do so. By using such a material for the side wall 51, a certain amount of resistance is generated along the electron discharge path. This resistance can eliminate the influence on the element operation due to the parasitic capacitance existing between the sidewall 51 and the n-type low concentration layer 4. That is, as shown in FIG.
51 is connected to gate 3, and a resistor R ₁ is placed in the side wall 51.
And the parasitic capacitance C ₁ exists, the gate 3 becomes
N type low concentration layer 4 via a series circuit of resistor R ₁ and parasitic capacitance C ₁
Will be connected to. The resistivity of the sidewall 51 is selected, and the time constant of this resistance R ₁ and parasitic capacitance C ₁ is
If the element is selected longer than the actual operation cycle, the delay in circuit operation can be ignored. Further, the electrons taken into the side wall 51 are discharged through the resistor R ₁ without being stored in the side wall 51.

Next, a manufacturing process of the semiconductor device having such a structure will be described with reference to the drawings.

3 (1) to 3 (7) are views for explaining this manufacturing process, in which 13 is a LOCOS oxide film, 14 is a p-type well portion, and 15 is a passivation film. Is the same as described in FIG.

(1) A p-type semiconductor substrate 1 having a resistivity of 10 Ω · cm is prepared [(1) in FIG. 3].

(2) A LOCOS (selective oxide) film 13 is formed to a thickness of 6000 Å and a gate oxide film 2 is formed to a thickness of 300 Å in the active region [Fig. 3 (2)].

(3) The p-type well portion 14 is formed by ion-implanting boron with an acceleration voltage of 75 KV and an implantation amount of 3 × 10 ¹² pieces / cm ² .
Figure (3)].

(4) Polycrystalline silicon is deposited to a thickness of 5000Å, and phosphorus is doped into this to reduce the resistance, and then a gate 3 having a desired shape is formed by photolithography technology [Fig. 3 (4)]. ].

(5) By the self-alignment method using the gate 3,
Phosphorus is ion-implanted at an accelerating voltage of 50 KV and an implantation amount of 1 × 10 ³ / cm ² to form an offset region by the n-type low-concentration layer 4 which becomes a part of the source and the drain [FIG. .

(6) Oxygen-doped polycrystalline silicon is deposited to a thickness of 5000Å by chemical vapor reaction, and isotropic etching is performed to form sidewalls 51 on the side wall of the gate 3. Next, an acceleration voltage of 80 is applied by the self-alignment method using the gate 3 and the side wall 51.
Arsenic is ion-implanted at a KV of 5 × 10 ¹⁵ ions / cm ² to form the source and drain diffusion layers 6 (FIG. 3 (6)).

(7) After depositing the interlayer insulating film 7, a contact hole is formed by photolithography technique to deposit aluminum to a thickness of 8000Å, and a wiring shape is processed by the photolithography technique to form an electrode 8.
Finally, the passivation film 15 is deposited [3rd
Figure (7)].

As described above, it is possible to obtain a MOSFET having a large photocarrier resistance, in which a conductive sidewall is provided on the side wall of the gate.

FIG. 4, FIG. 5 and FIG. 6 show the structure of one embodiment of the present invention and the structures of the second and third embodiments only around the side walls.

In the previously described embodiment shown in FIG. 4, the electrically conductive sidewall 51 is electrically connected to the gate 3 so that the electrons trapped in the sidewall 51 are discharged through the gate 3 at the high level. It is something to try. In this case, since the gate 3 is not always at the high level, it cannot be said to be a desirable shape in terms of efficiency of discharging electrons.

In the CMOS inverter, the drain of the n-channel MOSFET is always connected to the power supply potential and is at the high level. Therefore, if the side wall 51 is connected to the drain, the electrons in the side wall 51 can be efficiently released. The second and third embodiments shown in FIGS. 5 and 6 show specific examples thereof.

In the second embodiment of the present invention, as shown in FIG. 5, a contact hole for the drain diffusion layer 6 is formed as a sidewall.
51 on the side, aluminum electrode 8 side wall
It is also connected to 51 so that the side wall 51 has the same potential as the drain.

In the third embodiment of the present invention, as shown in FIG. 6, the sidewall 51 is removed by removing the silicon oxide film connected to the gate oxide film 2 on the drain before depositing the sidewall 51. And the drain diffusion layer 6 are directly connected.

In the second and third embodiments of the present invention shown in FIGS. 5 and 6 described above, an example in which the sidewall is connected to the drain has been described. In this embodiment, the sidewall connected to the drain is described. Is a side wall on the drain side, and the side wall on the source side is connected to the source. Further, in the present invention, the side wall may be provided so as to be insulated from the gate, the source and the drain, and the power source potential or the ground potential may be connected to the side wall.

Although the present invention has been described with reference to the embodiments of the n-channel MOSFET, the present invention can be applied to the p-channel MOSFET by changing the conductivity type of impurities.

〔The invention's effect〕

As described above, according to the present invention, the sidewall of the LDD MOSFET is made conductive, and the sidewall is connected to a specific potential, so that the hot carrier taken in the sidewall is discharged. The resistance of the low-concentration impurity layer located between the drain diffusion layer and the channel region can be suppressed by the influence of the carrier trapped in the sidewall. Therefore, even if it is used for a long time, characteristic deterioration does not occur.
It is possible to obtain a highly reliable short channel MOSFET.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a MOSFET according to an embodiment of the present invention, FIG. 2 is a diagram for explaining a mechanism capable of reducing characteristic deterioration according to the present invention, and FIGS. 3 (1), (2) and (3). , (4),
(5), (6), (7) are views for explaining the manufacturing process,
FIG. 4, FIG. 5 and FIG. 6 show the structure of one embodiment of the present invention,
FIGS. 7A and 7B are diagrams showing the structures of the second and third embodiments, respectively, only around the sidewalls thereof, FIG. 7 is a diagram showing the structure of a MOSFET according to the prior art, and FIGS. 8A and 8B are deteriorations of LDD MOSFETs. It is a figure explaining a mechanism. 1 ... p-type substrate, 2 ... gate oxide film, 3 ... gate,
4 …… n-type low concentration layer, 5,51 …… side wall, 6 ……
Source and drain diffusion layers, 7 ... Protective insulating layer, 8 ...
… Electrodes, 9,10,12 …… electrons, 11 …… holes, 13 …… LOCOS oxide film, 14 …… p-type well part, 15 …… passivation film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masataka Minami, 4026 Kujimachi, Hitachi, Ltd. 4026 Hitachi, Ltd. Hitachi Research Laboratory (72) Takahiro Nagano 4026, Kuji, Hitachi Hitachi, Ltd. Hitachi Research In-house (56) Reference JP 61-36973 (JP, A) JP 61-292374 (JP, A) JP 60-43863 (JP, A)

Claims (3)

(57) [Claims] 1. A semiconductor device having a metal-insulating film-semiconductor MIS or MOS structure formed on a semiconductor substrate, having sidewalls on a side surface of a gate, between a high-concentration source / drain layer and a channel region. In a semiconductor device having a low-concentration offset region provided by a self-alignment method using a gate, the sidewall is made conductive, and its electrical resistivity is from 1 Ω · cm to 1 × 10 ⁶
A semiconductor device characterized by setting the value between Ω · cm and connecting this sidewall to a specific potential. 2. The semiconductor device according to claim 1, wherein the sidewall is electrically connected to a gate electrode. 3. As the material for forming the sidewall, polycrystalline silicon with an intrinsic or low impurity concentration, or polycrystalline silicon doped with an element that suppresses diffusion of other impurities such as oxygen, nitrogen and carbon is used. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.