JP2504030B2 - Buffer memory monitoring circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission communication system, and more particularly to a buffer memory monitoring circuit thereof.

(Prior Art) Conventionally, in this kind of buffer memory monitoring circuit, the operations of the write counter and the read counter inside the buffer memory are individually monitored.

FIG. 2 is a block diagram showing an example of a buffer memory monitoring circuit according to the prior art. In FIG. 2, 21 is a write clock signal source, 22 is a read clock signal source,
23 is a write counter, 24 is a read counter, 25 is a buffer request circuit, 26 and 27 are buffer memory monitoring circuits, 28 is a buffer memory alarm signal terminal, and 29 is a buffer request signal terminal.

In FIG. 2, the buffer memory monitoring circuits 26 and 27 operate in parallel with the buffer request circuit 25.

(Problems to be Solved by the Invention) The conventional buffer memory monitoring circuit described above individually monitors both the write counter and the read counter inside the buffer memory, and requires two monitoring circuits. There are drawbacks.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a buffer memory monitoring circuit configured to eliminate the above-mentioned drawbacks by monitoring a buffer request signal shared by a write counter and a read counter inside a buffer memory so that one circuit is sufficient. It is in.

(Means for Solving Problems) A buffer memory monitoring circuit according to the present invention comprises a write counter, a read counter, a stuff request circuit,
A buffer memory monitoring circuit is provided.

The writing counter executes the counting operation by the writing clock signal, and the reading counter executes the counting operation by the reading clock signal.

The stuff request circuit uses the output of the write counter as data and the output of the read counter as the clock to form a D-type flip-flop.

The buffer memory monitoring circuit is for monitoring the buffer memory by the output of the buffer request circuit.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is a block diagram showing an embodiment of a buffer memory monitoring circuit according to the present invention. In FIG. 1, 11 is a write-side clock signal source, a read-side clock signal source, and 13
Is a writing counter, 14 is a reading counter, 15 is a buffer request circuit, 16 is a buffer memory monitoring circuit, 17 is a buffer memory alarm signal terminal, and a buffer request signal terminal.

The output of the write counter 13 and the output of the read counter 14 are input to the stuff request circuit 15, and a stuff request signal is sent out.

FIG. 2 shows the output signal (W COUN
FIG. 3 is a waveform timing chart showing T), the output signal (R COUNT) of the read counter 14, and the output signal (SD) of the stuff request circuit 15. In FIG. 2, 1RCLK represents one clock time of the clock signal output from the read-side clock signal source 12, and SD represents the pulse signal output from the stuff request circuit 15. In FIG. 2, the output signal of the write counter 13 is data and the output signal of the read counter 14 is a clock, and the output signal of the D-type flip-flop forming the stuff request circuit 15 is the stuff request signal.

By the above operation, when the time interval between the output of the write counter 13 and the output of the read counter 14 becomes a certain value or less, the clock signal of the read side signal source 12 is extracted for one clock period.

Therefore, the output signal of the clock signal source 11 on the writing side and the output signal of the clock signal source 12 on the reading side can be simultaneously monitored by monitoring the stack request signal for a certain period of time.

(Effect of the Invention) As described above, according to the present invention, the circuit configuration is simplified by monitoring the stuff request signal shared by the write counter and the read counter in the buffer memory, and the reliability and cost efficiency are improved. There is an effect that and can be improved at the same time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a buffer memory monitoring circuit according to the present invention. FIG. 2 is a waveform timing chart showing operation waveforms of the buffer memory monitoring circuit shown in FIG. FIG. 3 is a block diagram showing an example of a buffer memory monitoring circuit according to the prior art. 11,12,21,22 …… Clock signal source 13,14,23,24 …… Counter 15,25 …… Staff request circuit 16,26,27 …… Buffer memory monitoring circuit 17,18,28,29 …… Signal Terminal

Claims (1)

(57) [Claims] 1. A write counter that performs a count operation by a write clock signal, a read counter that performs a count operation by a read clock signal, and the output of the write counter as data, and the output of the read counter as a clock. A buffer memory monitoring circuit comprising: a buffer request circuit for forming a D-type flip-flop; and a buffer memory monitoring circuit for monitoring the buffer memory by the output of the buffer request circuit.