JP2025514693A5 - - Google Patents

Info

Publication number
JP2025514693A5
JP2025514693A5 JP2024560668A JP2024560668A JP2025514693A5 JP 2025514693 A5 JP2025514693 A5 JP 2025514693A5 JP 2024560668 A JP2024560668 A JP 2024560668A JP 2024560668 A JP2024560668 A JP 2024560668A JP 2025514693 A5 JP2025514693 A5 JP 2025514693A5
Authority
JP
Japan
Prior art keywords
block
filling process
metal filling
opening
contact plug
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024560668A
Other languages
English (en)
Japanese (ja)
Other versions
JP2025514693A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/US2023/015640 external-priority patent/WO2023204918A1/en
Publication of JP2025514693A publication Critical patent/JP2025514693A/ja
Publication of JP2025514693A5 publication Critical patent/JP2025514693A5/ja
Pending legal-status Critical Current

Links

JP2024560668A 2022-04-19 2023-03-20 Cmosデバイス用のコンタクト形成プロセス Pending JP2025514693A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202263332622P 2022-04-19 2022-04-19
US63/332,622 2022-04-19
PCT/US2023/015640 WO2023204918A1 (en) 2022-04-19 2023-03-20 Contact formation process for cmos devices

Publications (2)

Publication Number Publication Date
JP2025514693A JP2025514693A (ja) 2025-05-09
JP2025514693A5 true JP2025514693A5 (https=) 2026-03-27

Family

ID=88420383

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024560668A Pending JP2025514693A (ja) 2022-04-19 2023-03-20 Cmosデバイス用のコンタクト形成プロセス

Country Status (7)

Country Link
US (1) US20230377997A1 (https=)
EP (1) EP4511874A4 (https=)
JP (1) JP2025514693A (https=)
KR (1) KR20230149249A (https=)
CN (1) CN118891712A (https=)
TW (1) TW202343548A (https=)
WO (1) WO2023204918A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12431360B2 (en) * 2023-07-18 2025-09-30 Applied Materials, Inc. Selective etching between silicon-and-germanium-containing materials with varying germanium concentrations
US12394631B2 (en) * 2023-09-29 2025-08-19 Applied Materials, Inc. Selective etching of silicon-and-germanium-containing materials with increased surface purities

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6596577B2 (en) * 1998-08-25 2003-07-22 Micron Technology, Inc. Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US6703279B2 (en) * 2002-01-04 2004-03-09 Promos Technologies, Inc. Semiconductor device having contact of Si-Ge combined with cobalt silicide
US7863201B2 (en) * 2008-03-24 2011-01-04 Samsung Electronics Co., Ltd. Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance
US9576809B2 (en) * 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US10297586B2 (en) * 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US10685870B2 (en) * 2017-08-30 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN111902912A (zh) * 2018-03-26 2020-11-06 朗姆研究公司 用于金属互连层的中间层
US11232947B1 (en) * 2020-09-01 2022-01-25 Taiwan Semiconductor Manufacturing Company Limited Ammonium fluoride pre-clean protection

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