KR20230149249A - Cmos 디바이스들을 위한 콘택 형성 프로세스 - Google Patents

Cmos 디바이스들을 위한 콘택 형성 프로세스 Download PDF

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Publication number
KR20230149249A
KR20230149249A KR1020230049966A KR20230049966A KR20230149249A KR 20230149249 A KR20230149249 A KR 20230149249A KR 1020230049966 A KR1020230049966 A KR 1020230049966A KR 20230049966 A KR20230049966 A KR 20230049966A KR 20230149249 A KR20230149249 A KR 20230149249A
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South Korea
Prior art keywords
semiconductor regions
contact layer
sccm
processing chamber
substrate
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Korean (ko)
Inventor
니콜라스 루이스 브레일
바라수브라마니안 프라나타르티하란
벤자민 콜롬보
안추안 왕
Original Assignee
어플라이드 머티어리얼스, 인코포레이티드
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Publication of KR20230149249A publication Critical patent/KR20230149249A/ko
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • HELECTRICITY
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
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    • H10P72/0431Apparatus for thermal treatment
    • H10P72/0434Apparatus for thermal treatment mainly by convection
    • H01L21/8238
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D64/01Manufacture or treatment
    • H10D64/011Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
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    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326Deposition processes
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    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
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    • H10P72/0452Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers
    • H10P72/0454Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers surrounding a central transfer chamber
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    • H10P72/0451Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H10P72/0471Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber
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    • H10P72/0451Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H10P72/0474Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one lithography chamber
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    • H10W20/033Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
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    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
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    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2902Materials being Group IVA materials
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    • H10P14/34Deposited materials, e.g. layers
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    • H10P14/3404Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411Silicon, silicon germanium or germanium
KR1020230049966A 2022-04-19 2023-04-17 Cmos 디바이스들을 위한 콘택 형성 프로세스 Pending KR20230149249A (ko)

Applications Claiming Priority (2)

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US202263332622P 2022-04-19 2022-04-19
US63/332,622 2022-04-19

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KR20230149249A true KR20230149249A (ko) 2023-10-26

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KR1020230049966A Pending KR20230149249A (ko) 2022-04-19 2023-04-17 Cmos 디바이스들을 위한 콘택 형성 프로세스

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US (1) US20230377997A1 (https=)
EP (1) EP4511874A4 (https=)
JP (1) JP2025514693A (https=)
KR (1) KR20230149249A (https=)
CN (1) CN118891712A (https=)
TW (1) TW202343548A (https=)
WO (1) WO2023204918A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12431360B2 (en) * 2023-07-18 2025-09-30 Applied Materials, Inc. Selective etching between silicon-and-germanium-containing materials with varying germanium concentrations
US12394631B2 (en) * 2023-09-29 2025-08-19 Applied Materials, Inc. Selective etching of silicon-and-germanium-containing materials with increased surface purities

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6596577B2 (en) * 1998-08-25 2003-07-22 Micron Technology, Inc. Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US6703279B2 (en) * 2002-01-04 2004-03-09 Promos Technologies, Inc. Semiconductor device having contact of Si-Ge combined with cobalt silicide
US7863201B2 (en) * 2008-03-24 2011-01-04 Samsung Electronics Co., Ltd. Methods of forming field effect transistors having silicided source/drain contacts with low contact resistance
US9576809B2 (en) * 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US10297586B2 (en) * 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US10685870B2 (en) * 2017-08-30 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
CN111902912A (zh) * 2018-03-26 2020-11-06 朗姆研究公司 用于金属互连层的中间层
US11232947B1 (en) * 2020-09-01 2022-01-25 Taiwan Semiconductor Manufacturing Company Limited Ammonium fluoride pre-clean protection

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Publication number Publication date
TW202343548A (zh) 2023-11-01
EP4511874A4 (en) 2026-04-01
WO2023204918A9 (en) 2024-10-10
EP4511874A1 (en) 2025-02-26
WO2023204918A1 (en) 2023-10-26
JP2025514693A (ja) 2025-05-09
US20230377997A1 (en) 2023-11-23
CN118891712A (zh) 2024-11-01

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