WO2023204918A1 - Contact formation process for cmos devices - Google Patents

Contact formation process for cmos devices Download PDF

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Publication number
WO2023204918A1
WO2023204918A1 PCT/US2023/015640 US2023015640W WO2023204918A1 WO 2023204918 A1 WO2023204918 A1 WO 2023204918A1 US 2023015640 W US2023015640 W US 2023015640W WO 2023204918 A1 WO2023204918 A1 WO 2023204918A1
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Prior art keywords
semiconductor regions
contact layer
seem
substrate
processing chamber
Prior art date
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Ceased
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PCT/US2023/015640
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English (en)
French (fr)
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WO2023204918A9 (en
Inventor
Nicolas Louis Breil
Balasubramanian Pranatharthiharan
Benjamin Colombeau
Anchuan Wang
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Applied Materials Inc
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Applied Materials Inc
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Priority to CN202380028968.2A priority Critical patent/CN118891712A/zh
Priority to JP2024560668A priority patent/JP2025514693A/ja
Priority to EP23792310.7A priority patent/EP4511874A4/en
Publication of WO2023204918A1 publication Critical patent/WO2023204918A1/en
Publication of WO2023204918A9 publication Critical patent/WO2023204918A9/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
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    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
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    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
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    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
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    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
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    • H10P72/0454—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers surrounding a central transfer chamber
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    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H10P72/0471—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one ion or electron beam chamber
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    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0468—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process
    • H10P72/0474—Apparatus for manufacturing or treating in a plurality of work-stations comprising a chamber adapted to a particular process comprising at least one lithography chamber
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    • H10P72/06—Apparatus for monitoring, sorting, marking, testing or measuring
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    • H10W20/00—Interconnections in chips, wafers or substrates
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    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
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    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
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    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
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    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium

Definitions

  • Embodiments described herein generally relate to semiconductor device fabrication, and more particularly, to systems and methods of forming a contact within a semiconductor structure.
  • Multi-gate metal-oxide-sem iconductor field-effect transistors such as complementary metal-oxide semiconductor (CMOS) devices
  • CMOS complementary metal-oxide semiconductor
  • 3D three-dimensional
  • an epitaxial layer of silicon-containing material e.g., boron- doped p-type silicon germanium or phosphorus-doped n-type silicon
  • silicon-containing material e.g., boron- doped p-type silicon germanium or phosphorus-doped n-type silicon
  • the formation and patterning of such epitaxial layer may damage various portions of the CMOS device, such as spacers, gate cap layers, or epitaxially grown layers.
  • Embodiments of the present disclosure provide a method of forming a contact layer in a semiconductor structure.
  • the method includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions, performing a patterning process to form a patterned stack, wherein the patterned stack comprises a patterned layer that comprises openings formed over the first contact layer disposed within each opening in the dielectric layer and a portion of the patterned layer that is disposed over each second contact layer disposed within each opening in the dielectric layer, and performing a selective removal process to remove the first contact layer selectively to the plurality of first semiconductor regions, the dielectric layer, and the patterned layer.
  • Embodiments of the present disclosure provide a method of forming a contact layer in a semiconductor structure.
  • the method includes performing a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, wherein the exposed surfaces of the plurality of first and second semiconductor regions are each disposed within openings formed in a dielectric layer disposed over the substrate, performing a first selective epitaxial deposition process to simultaneously form a first contact layer having a first thickness on the exposed surface of the first semiconductor regions and a second contact layer having a second thickness on the exposed surface of the second semiconductor regions, wherein the second thickness is larger than the first thickness, and performing a selective removal process to remove the first contact layer and the second contact layer selectively to the plurality of first semiconductor regions, and the dielectric layer until the first contact layer is substantially removed from the first semiconductor regions and a portion of the second contact layer remains on the second semiconductor regions.
  • Embodiments of the present disclosure provide a processing system, including a first processing chamber, a second processing chamber, a third processing chamber, and a system controller configured to perform, in the first processing chamber, a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, perform, in the second processing chamber, a first selective deposition process to epitaxially form a first contact layer on the exposed surfaces of the first semiconductor regions and a second contact layer on the exposed surface of the second semiconductor regions of the substrate, and perform, in the third processing chamber, a selective removal process to remove the first contact layer selectively to the first semiconductor regions.
  • a processing system including a first processing chamber, a second processing chamber, a third processing chamber, and a system controller configured to perform, in the first processing chamber, a pre-clean process on exposed surfaces of a plurality of first semiconductor regions and a plurality of second semiconductor regions formed on a substrate, perform, in the second processing chamber, a first selective deposition process to epit
  • Figure 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.
  • Figure 2A is a cross sectional view of a processing chamber, according to one or more embodiments.
  • Figure 2B is an enlarged view of a portion of the processing chamber of Figure 2A.
  • Figure 3 is a cross sectional view of a processing chamber, according to one or more embodiments.
  • Figure 4 is a cross sectional view of a processing chamber, according to one or more embodiments.
  • Figure 5 depicts a process flow diagram of a method of forming a contact layer in a semiconductor structure according to a first embodiment of the present disclosure.
  • Figures 6A, 6B, 6C, 6D, 6E, 6F, and 6G are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of Figure 5.
  • Figure 7 depicts a process flow diagram of a method of forming a contact layer in a semiconductor structure according to a second embodiment of the present disclosure.
  • Figures 8A, 8B, 8C, 8D, and 8E are cross-sectional views of a portion of the semiconductor structure corresponding to various states of the method of Figure 7.
  • identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
  • the embodiments described herein provide methods and systems for forming a contact that includes an epitaxial layer of silicon-containing material (e.g., boron- doped p-type silicon germanium or phosphorus-doped n-type silicon) at a selected portion (e.g., on an exposed surface of a layer of silicon or silicon germanium) of a structure that is used to form a CMOS device.
  • silicon-containing material e.g., boron- doped p-type silicon germanium or phosphorus-doped n-type silicon
  • the methods and systems may be particularly useful for forming, in a semiconductor structure having a region that includes silicon, a region that includes silicon germanium, and a dielectric layer formed thereover, an epitaxial layer that includes silicon germanium selectively on an exposed surface of the silicon germanium material within an opening or feature (e.g., contact trench) formed in the dielectric layer.
  • an opening or feature e.g., contact trench
  • the processes described herein are configured to form a contact without damaging these previously formed semiconductor structures.
  • FIG. 1 is a schematic top view of a multi-chamber processing system 100, according to one or more embodiments of the present disclosure.
  • the processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130.
  • substrates in the processing system 100 can be processed in and transferred between the various chambers without exposing the substrates to an ambient environment exterior to the processing system 100 (e.g., an atmospheric ambient environment such as may be present in a fab).
  • the substrates can be processed in and transferred between the various chambers maintained at a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment among various processes performed on the substrates in the processing system 100.
  • a low pressure e.g., less than or equal to about 300 Torr
  • the processing system 100 may provide for an integrated solution for some processing of substrates.
  • Examples of a processing system that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer® or Centura® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from aspects described herein.
  • the factory interface 102 includes a docking station 132 and factory interface robots 134 to facilitate transfer of substrates.
  • the docking station 132 is adapted to accept one or more front opening unified pods (FOUPs) 136.
  • each factory interface robot 134 generally includes a blade 138 disposed on one end of the respective factory interface robot 134 adapted to transfer the substrates from the factory interface 102 to the load lock chambers 104, 106.
  • the load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108.
  • the transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to processing chambers 120, 122.
  • the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to processing chambers 124, 126, 128, 130.
  • the ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, slit valve openings with slit valves for passing substrates therethrough by the transfer robots 112, 114 and for providing a seal between respective chambers to prevent a gas from passing between the respective chambers.
  • any port is open for transferring a substrate therethrough. Otherwise, the port is closed.
  • the load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically illustrated).
  • the gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo-pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers.
  • a factory interface robot 134 transfers a substrate from a FOIIP 136 through a port 140 or 142 to a load lock chamber 104 or 106.
  • the gas and pressure control system then pumps down the load lock chamber 104 or 106.
  • the gas and pressure control system further maintains the transfer chambers 108, 110 and holding chambers 116, 118 with an interior low pressure or vacuum environment (which may include an inert gas).
  • an interior low pressure or vacuum environment which may include an inert gas.
  • the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 into the transfer chamber 108 through the port 144 or 146.
  • the transfer robot 112 is then capable of transferring the substrate to and/or between any of the processing chambers 120, 122 through the respective ports 152, 154 for processing and the holding chambers 116, 118 through the respective ports 148, 150 for holding to await further transfer.
  • the transfer robot 114 is capable of accessing the substrate in the holding chamber 116 or 118 through the port 156 or 158 and is capable of transferring the substrate to and/or between any of the processing chambers 124, 126, 128, 130 through the respective ports 160, 162, 164, 166 for processing and the holding chambers 116, 118 through the respective ports 156, 158 for holding to await further transfer.
  • the transfer and holding of the substrate within and among the various chambers can be in the low pressure or vacuum environment provided by the gas and pressure control system.
  • the processing chambers 120, 122, 124, 126, 128, 130 can be any appropriate chamber for processing a substrate.
  • the processing chamber 120 can be capable of performing an etch process
  • the processing chamber 122 can be capable of performing a cleaning process
  • the processing chamber 124 can be capable of performing a selective removal process
  • the processing chambers 126, 128, 130 can be capable of performing respective epitaxial growth processes.
  • the processing chamber 120 may be a SelectraTM Etch chamber available from Applied Materials of Santa Clara, Calif.
  • the processing chamber 122 may be a SiCoNiTM Preclean chamber available from Applied Materials of Santa Clara, Calif.
  • the processing chamber 126, 128, or 130 may be a CenturaTM Epi chamber available from Applied Materials of Santa Clara, Calif.
  • a system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof.
  • the system controller 168 may control the operation of the processing system 100 using a direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130.
  • the system controller 168 enables data collection and feedback from the respective chambers to coordinate performance of the processing system 100.
  • the system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174.
  • the CPU 170 may be one of any form of a general purpose processor that can be used in an industrial setting.
  • the memory 172, or non-transitory computer-readable medium, is accessible by the CPU 170 and may be one or more of memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote.
  • the support circuits 174 are coupled to the CPU 170 and may comprise cache, clock circuits, input/output subsystems, power supplies, and the like.
  • the various methods disclosed herein may generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction code stored in the memory 172 (or in memory of a particular processing chamber) as, for example, a software routine.
  • the CPU 170 controls the chambers to perform processes in accordance with the various methods.
  • FIG. 1 is a cross sectional view of a processing chamber 200, according to one or more embodiments, that is adapted to perform a pre-clean process as detailed below.
  • the processing chamber 200 may be the processing chamber 122 shown in Figure 1 .
  • Figure 2B is an enlarged view of a portion of the processing chamber 200 of Figure 2A.
  • the processing chamber 200 may be particularly useful for performing a thermal or plasma-based cleaning process and/or a plasma assisted dry etch process.
  • the processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206.
  • the lid assembly 204 is disposed at an upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202.
  • a vacuum system can be used to remove gases from processing chamber 200.
  • the vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed in the chamber body 202.
  • the processing chamber 200 also includes a controller 212 for controlling processes within the processing chamber 200.
  • the lid assembly 204 includes stacked components adapted to provide precursor gases and/or a plasma to a processing region 214 within the processing chamber 200.
  • a first plate 216 is coupled to a second plate 218.
  • a third plate 220 is coupled to the second plate 218.
  • the lid assembly 204 may be connected to a power source (not shown) for supplying a plasma to a cone-shaped chamber 222 formed in the lid assembly 204.
  • the lid assembly 204 can also be connected to a remote plasma source 224 that creates the plasma upstream of the lid stack.
  • the remote plasma cavity (e.g., the processing region 214, the first plate 216, and the second plate 218 in Figures 2A-2B) is coupled to a gas source 226 (or the gas source 226 is coupled directly to the lid assembly 204 in the absence of the remote plasma source 224).
  • the gas source 226 may include a gas source that is adapted to provide helium, argon, or other inert gas. In some configurations, the gas provided by the gas source 226 can be energized into a plasma that is provided to the lid assembly 204 by use of the remote plasma source 224.
  • the gas source 226 may provide process gases that can be activated by the remote plasma source 224 prior to being introduced to a surface of the substrate that is disposed within the processing chamber 200.
  • the cone-shaped chamber 222 has an opening 228 that allows a formed plasma to flow from the remote plasma source 224 to a volume 230 formed in a fourth plate 232 of the lid assembly 204.
  • a plasma is generated within the cone-shaped chamber 222 by the application of energy delivered from a plasma source.
  • the energy can be provided by biasing the lid assembly 204 to capacitively couple RF, VHF and/or UHF energy to the gases positioned in the cone- shaped chamber 222.
  • the remote plasma source 224 may not be used, or not be installed within the lid assembly 204.
  • the central conduit 234 communicates with the mixing chamber 238 through an opening 242 in the fifth plate 236.
  • the opening 242 may have a diameter less than, greater than or the same as a diameter of the central conduit 234. In the embodiment of Figure 2B, the opening 242 has diameter the same as the central conduit 234.
  • the fourth plate 232 also includes inlets 244 and 246 that are adapted to provide gases to the mixing chamber 238.
  • the inlet 244 is coupled to a first gas source 248 and the inlet 246 is coupled to a second gas source 250.
  • the first gas source 248 and the second gas source 250 may include processing gases as well as inert gases, for example inert gases such as argon and/or helium, utilized as a carrier gas.
  • the first gas source 248 may include ammonia (NH3) as well as argon (Ar).
  • the second gas source 250 may contain fluorine containing gases, hydrogen containing gases, or a combination thereof. In one example, the second gas source 250 may contain hydrogen fluoride (HF) as well as argon (Ar).
  • the inlet 244 is coupled to the mixing chamber 238 through a cylindrical channel 252 (shown in phantom) and holes 254 formed in the fifth plate 236.
  • the inlet 246 is coupled to the mixing chamber 238 through a cylindrical channel 256 (shown in phantom) and holes 258 formed in the fifth plate 236.
  • the holes 254, 258 formed in the fifth plate 236 are generally sized so that they enable a uniform flow of gases, which are provided from their respective gas source 248, 250, into the mixing chamber 238.
  • the holes 258 have a diameter that is less than a width of the opening defined by the opposing sidewalls of the cylindrical channel 256 formed in the fourth plate 232.
  • the holes 258 are typically distributed around the circumference of the center-line of the cylindrical channel 256 to provide uniform fluid flow into the mixing chamber 238.
  • the holes 254 have a diameter that is less than a width of the opening defined by the opposing sidewalls of the cylindrical channel 252 formed the fourth plate 232.
  • the holes 254 are typically distributed around the circumference of the center-line of the cylindrical channel 252 to provide uniform fluid flow into the mixing chamber 238.
  • the inlets 244 and 246 provide respective fluid flow paths laterally through the fourth plate 232, turning toward and penetrating through the fifth plate 236 to the mixing chamber 238.
  • the lid assembly 204 also includes a seventh plate or first gas distributor 260, which may be a gas distribution plate, such as a showerhead, where the various gases mixed in the lid assembly 204 are flowed through perforations 262 formed therein.
  • the perforations 262 are in fluid communication with the mixing chamber 238 to provide flow pathways from the mixing chamber 238 through the first gas distributor 260.
  • a blocker plate 264 and a gas distribution plate, such as a second gas distributor 266, which may be a gas distribution plate, such as a showerhead, is disposed below the lid assembly 204.
  • a different cleaning process may be utilized to clean the substrate surface.
  • a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 through the lid assembly 204, while ammonia (NH3) may be directly injected into the processing chamber 200 via a separate gas inlet 268 that is disposed at a side of the chamber body 202 and coupled to a gas source (not shown).
  • the support assembly 206 may include a substrate support 270 to support a substrate 272 thereon during processing.
  • the substrate support 270 may be coupled to an actuator 274 by a shaft 276 which extends through a centrally-located opening formed in a bottom of the chamber body 202.
  • the actuator 274 may be flexibly sealed to the chamber body 202 by bellows (not shown) that prevent vacuum leakage around the shaft 276.
  • the actuator 274 allows the substrate support 270 to be moved vertically within the chamber body 202 between a processing position and a loading position.
  • the loading position is slightly below the opening of a tunnel (not shown) formed in a sidewall of the chamber body 202.
  • the substrate support 270 has a flat, or a substantially flat, substrate supporting surface for supporting a substrate 272 to be processed thereon.
  • the substrate support 270 may be moved vertically within the chamber body 202 by the actuator 274, which is coupled to the substrate support 270 by the shaft 276.
  • the substrate support 270 may be elevated to a position in close proximity to the lid assembly 204 to control the temperature of the substrate 272 being processed.
  • the substrate 272 may be heated via radiation emitted from the second gas distributor 266, or another radiant source, or by convection or conduction from the second gas distributor 266 through an intervening gas.
  • the substrate may be disposed on lift pins 278 to perform additional thermal processing steps, such as performing an annealing step.
  • Figure 3 is a cross sectional view of a processing chamber 300, according to one or more embodiments, that is adapted to perform an epitaxial (Epi) deposition process as detailed below.
  • the processing chamber 300 may be the processing chamber 126, 128, or 130 shown in Figure 1.
  • the processing chamber 300 includes a housing structure 302 made of a process resistant material, such as aluminum or stainless steel, for example 316L stainless steel.
  • the housing structure 302 encloses various functioning elements of the processing chamber 300, such as a quartz chamber 304, which includes an upper quartz chamber 306, and a lower quartz chamber 308, in which a processing volume 310 is contained.
  • Reactive species are provided to the quartz chamber 304 by a gas distribution assembly 312, and processing byproducts are removed from the processing volume 310 by an outlet port 314, which is typically in communication with a vacuum source (not shown).
  • a substrate support 316 is adapted to receive a substrate 318 that is transferred to the processing volume 310.
  • the substrate support 316 is disposed along a longitudinal axis 320 of the processing chamber 300.
  • the substrate support 316 may be made of a ceramic material or a graphite material coated with a silicon material, such as silicon carbide, or other process resistant material. Reactive species from precursor reactant materials are applied to a surface 322 of the substrate 318, and byproducts may be subsequently removed from the surface 322 of the substrate 318.
  • Heating of the substrate 318 and/or the processing volume 310 may be provided by radiation sources, such as upper lamp modules 324A and lower lamp modules 324B.
  • the upper lamp modules 324A and the lower lamp modules 324B are infrared (IR) lamps.
  • Non-thermal energy or radiation from the lamp modules 324A and 324B travels through an upper quartz window 326 of the upper quartz chamber 306, and through a lower quartz window 328 of the lower quartz chamber 308.
  • Precursor reactant materials, as well as diluent, purge and vent gases for the processing chamber 300 enter through the gas distribution assembly 312 and exit through the outlet port 314.
  • the upper quartz window 326 is shown as being curved or convex, the upper quartz window 326 may be planar or concave as the pressure on both sides of the upper quartz window 326 is substantially the same (7.e. , atmospheric pressure).
  • the low wavelength radiation in the processing volume 310 which is used to energize reactive species and assist in adsorption of reactants and desorption of process byproducts from the surface 322 of the substrate 318, typically ranges from about 0.8 pm to about 1 .2 pm, for example, between about 0.95 pm to about 1 .05 pm, with combinations of various wavelengths being provided, depending, for example, on the composition of the film which is being epitaxially grown.
  • the component gases enter the processing volume 310 via the gas distribution assembly 312. Gas flows from the gas distribution assembly 312 and exits through the outlet port 314 as shown generally by a flow path 334. Combinations of component gases, which are used to clean/passivate a substrate surface, or to form the silicon and/or germanium-containing film that is being epitaxially grown, are typically mixed prior to entry into the processing volume 310.
  • the overall pressure in the processing volume 310 may be adjusted by a valve (not shown) on the outlet port 314. At least a portion of the interior surface of the processing volume 310 is covered by a liner 336.
  • the liner 336 comprises a quartz material that is opaque. In this manner, the chamber wall is insulated from the heat in the processing volume 310.
  • the temperature of surfaces in the processing volume 310 may be controlled within a temperature range of about 200°C to about 600°C, or greater, by the flow of a cooling gas, which enters through the inlet 330 and exits through the outlet 332, in combination with radiation from the upper lamp modules 324A positioned above the upper quartz window 326.
  • the temperature in the lower quartz chamber 308 may be controlled within a temperature range of about 200°C to about 600°C or greater, by adjusting the speed of a blower unit which is not shown, and by radiation from the lower lamp modules 324B disposed below the lower quartz chamber 308.
  • the pressure in the processing volume 310 may be between about 0.1 Torr to about 600 Torr, such as between about 5 Torr to about 30 Torr.
  • the temperature on the surface 322 of the substrate 318 may be controlled by power adjustment to the lower lamp modules 324B in the lower quartz chamber 308, or by power adjustment to both the upper lamp modules 324A overlying the upper quartz window 326, and the lower lamp modules 324B in the lower quartz chamber 308.
  • the power density in the processing volume 310 may be between about 40 W/cm 2 to about 400 W/cm 2 , such as about 80 W/cm 2 to about 120 W/cm 2
  • the gas distribution assembly 312 is disposed normal to, or in a radial direction 338 relative to, the longitudinal axis 320 of the processing chamber 300 or the substrate 318. In this orientation, the gas distribution assembly 312 is adapted to flow process gases in the radial direction 338 across, or parallel to, the surface 322 of the substrate 318.
  • the process gases are preheated at the point of introduction to the processing chamber 300 to initiate preheating of the gases prior to introduction to the processing volume 310, and/or to break specific bonds in the gases. In this manner, surface reaction kinetics may be modified independently from the thermal temperature of the substrate 318.
  • precursors used to form silicon (Si) and silicon germanium (SiGe) blanket or selective epitaxial films are provided to the gas distribution assembly 312 from the one or more gas sources 340A and 340B.
  • IR lamps 342 (only one is shown in Figure 3) may be utilized to heat the precursors within the gas distribution assembly 312 as well as along the flow path 334.
  • the gas sources 340A, 340B may be coupled the gas distribution assembly 312 in a manner adapted to facilitate introduction zones within the gas distribution assembly 312, such as a radial outer zone and a radial inner zone between the outer zones when viewed in from a top plan view.
  • the gas sources 340A, 340B may include valves (not shown) to control the rate of introduction into the zones.
  • the gas sources 340A, 340B may include silicon precursors such as silanes, including silane (SiF ), disilane (Si2He,), dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cle), dibromosilane (SiH2Br2), higher order silanes, derivatives thereof, and combinations thereof.
  • the gas sources 340A, 340B may also include germanium containing precursors, such as germane (GeH4), digermane (Ge2He), germanium tetrachloride (GeCk), dichlorogermane (GeH2Cl2), derivatives thereof, and combinations thereof.
  • the silicon and/or germanium containing precursors may be used in combination with hydrogen chloride (HCI), chlorine gas (CI2), hydrogen bromide (HBr), and combinations thereof.
  • the gas sources 340A, 340B may include one or more of the silicon and germanium containing precursors in one or both of the gas sources 340A, 340B.
  • the precursor materials enter the processing volume 310 through openings or holes 344 (only one is shown in Figure 3) in the perforated plate 346 in this excited state, which in one embodiment is a quartz material, having the holes 344 formed therethrough.
  • the perforated plate 346 is transparent to IR energy, and may be made of a clear quartz material. In other embodiments, the perforated plate 346 may be any material that is transparent to IR energy and is resistant to process chemistry and other processing chemistries.
  • the energized precursor materials flow toward the processing volume 310 through the holes 344 in the perforated plate 346, and through channels 348 (only one is shown in Figure 3).
  • a portion of the photons and nonthermal energy from the IR lamps 342 also passes through the holes 344, the perforated plate 346, and channels 348 facilitated by a reflective material and/or surface disposed on the interior surfaces of the gas distribution assembly 312, thereby illuminating the flow path 334 of the precursor materials. In this manner, the vibrational energy of the precursor materials may be maintained from the point of introduction to the processing volume 310 along the flow path.
  • FIG 4 is a cross sectional view of a processing chamber 400, according to one or more embodiments, that is adapted to perform a selective removal process (SRP) as detailed below.
  • the processing chamber 400 may be the processing chamber 124 shown in Figure 1.
  • the processing chamber 400 includes a chamber body 402, a lid assembly 404, and a support assembly 406.
  • the lid assembly 404 is disposed at an upper end of the chamber body 402, and the support assembly 406 is at least partially disposed within the chamber body 402.
  • a vacuum system can be used to remove gases from processing chamber 400.
  • the vacuum system includes a vacuum pump 408 coupled to a vacuum port 410 disposed in the chamber body 402.
  • the lid assembly 404 includes a remote plasma system (RPS) 412 that may process a fluorine-containing precursor which then travels through a gas inlet assembly 414. Two distinct gas supply channels are visible within the gas inlet assembly 414.
  • RPS remote plasma system
  • a first channel 416 carries a gas that passes through the RPS 412, while a second channel 418 bypasses the RPS 412. Either channel may be used for the fluorine-containing precursor. In some implementations, the first channel 416 may be used for a process gas and the second channel 418 may be used for a treatment gas.
  • a lid (also referred to as a “conductive top portion”) 420 and a perforated partition (also referred to as a “showerhead”) 422 are shown with an insulating ring 424 in between, which allows an AC potential to be applied to the lid 420 relative to the perforated partition 422. The AC potential strikes a plasma in a chamber plasma region 426.
  • the process gas may travel through the first channel 416 into the chamber plasma region 426 and may be excited by a plasma in the chamber plasma region 426 alone or in combination with the RPS 412. If the process gas (e.g., the fluorine- containing precursor) flows through the second channel 418, then only the chamber plasma region 426 is used for excitation.
  • the perforated partition 422 separates the chamber plasma region 426 from a substrate processing region 428 beneath the perforated partition 422. The perforated partition 422 allows a plasma present in the chamber plasma region 426 to avoid directly exciting gases in the substrate processing region 428, while still allowing excited species to travel from the chamber plasma region 426 into the substrate processing region 428.
  • the perforated partition 422 is positioned between the chamber plasma region 426 and the substrate processing region 428 and allows plasma effluents (excited derivatives of precursors or other gases) created within the RPS 412 and/or the chamber plasma region 426 to pass through through-holes 430 that traverse the thickness of the plate.
  • the perforated partition 422 also has one or more hollow volumes 432 which can be filled with a precursor in the form of a vapor or gas (such as a fluorine-containing precursor) and pass through small holes 434 into the substrate processing region 428 but not directly into the chamber plasma region 426.
  • the perforated partition 422 is thicker than the length of the smallest diameter 436 of the through-holes 430 in this embodiment.
  • the length 438 of the smallest diameter 436 of the through-holes 430 may be restricted by forming larger diameter portions of the through-holes 430 part way through the perforated partition 422 to maintain a significant concentration of excited species penetrating from the chamber plasma region 426 to the substrate processing region 428.
  • the length of the smallest diameter 436 of the through-holes 430 may be the same order of magnitude as the smallest diameter 436 of the through-holes 430 or less in some embodiments.
  • the perforated partition 422 may be adapted to serve the purpose of an ion suppressor. Alternatively, a separate processing chamber element may be included (not shown) which suppresses the ion concentration traveling into the substrate processing region 428.
  • the lid 420 and the perforated partition 422 may function as a first electrode and a second electrode, respectively, so that the lid 420 and the perforated partition 422 may receive different electric voltages.
  • electrical power e.g., RF power
  • electrical power may be applied to the lid 420 while the perforated partition 422 (serving as ion suppressor) is grounded.
  • An RF generator may provide electrical power to the lid 420 and/or the perforated partition 422.
  • the voltage applied to the lid 420 may facilitate a uniform distribution of plasma (/.e., reduce localized plasma) within the chamber plasma region 426.
  • the insulating ring 424 may electrically insulate the lid 420 from the perforated partition 422.
  • the insulating ring 424 may be made from a ceramic and may have a high breakdown voltage to avoid sparking.
  • Portions of the processing chamber 400 near the capacitively-coupled plasma components that are described above may further include a cooling unit (not shown) that includes one or more cooling fluid channels to cool surfaces exposed to the plasma with a circulating coolant (e.g., water).
  • the perforated partition 422 may distribute (via the through-holes 430) process gases which contain fluorine, hydrogen and/or plasma effluents of such process gases upon excitation by a plasma in the chamber plasma region 426.
  • the process gas introduced into the RPS 412 and/or the chamber plasma region 426 may contain fluorine (e.g., F2, NFs or XeF2).
  • the process gas may also include a diluent gases such as helium (He), argon (Ar), or nitrogen (N2).
  • Plasma effluents may include ionized or neutral derivatives of the process gas and may also be referred to herein as radical-fluorine and/or radicalhydrogen referring to the atomic constituent of the process gas introduced.
  • the through-holes 430 suppress the migration of ionically-charged species out of the chamber plasma region 426 while allowing uncharged neutral or radical species to pass through the perforated partition 422 into the substrate processing region 428.
  • These uncharged species may include highly reactive species that are transported with less-reactive carrier gas by the through-holes 430.
  • the migration of ionic species by the through-holes 430 may be reduced, and in some instances completely suppressed.
  • Controlling the amount of ionic species passing through the perforated partition 422 provides increased control over the gas mixture brought into contact with the underlying patterned substrate, which in turn increases control of the deposition and/or etch characteristics of the gas mixture.
  • adjustments in the ion concentration of the gas mixture can alter the etch selectivity (e.g., a ratio of the etch rate of silicon germanium to the etch rate of silicon).
  • the number of the through-holes 430 may be between about 60 and about 2000.
  • the through-holes 430 may have a variety of shapes but are most easily made round.
  • the smallest diameter 436 of the through-holes 430 may be between about 0.5 mm and about 20 mm or between about 1 mm and about 6 mm in some embodiments.
  • the number of the small holes 434 used to introduce unexcited precursors into the substrate processing region 428 may be between about 100 and about 5000 or between about 500 and about 2000 in different embodiments.
  • the diameter of the small holes 434 may be between about 0.1 mm and about 2 mm.
  • the through-holes 430 may control the passage of the plasma-activated gas (/.e., the ionic, radical, and/or neutral species) through the perforated partition 422.
  • the aspect ratio of the holes (/.e., the hole diameter to length) and/or the geometry of the holes may be controlled so that the flow of ionically-charged species in the activated gas passing through the perforated partition 422 is reduced.
  • the through-holes 430 in the perforated partition 422 may include a tapered portion that faces the chamber plasma region 426, and a cylindrical portion that faces the substrate processing region 428. The cylindrical portion may be proportioned and dimensioned to control the flow of ionic species passing into the substrate processing region 428.
  • An adjustable electrical bias may also be applied to the perforated partition 422 as an additional means to control the flow of ionic species through the perforated partition 422.
  • through-holes 430 may have a smaller inner diameter (ID) toward the top surface of the perforated partition 422 and a larger ID toward the bottom surface.
  • ID inner diameter
  • the bottom edge of the through-holes 430 may be chamfered to help evenly distribute the plasma effluents in the substrate processing region 428 as the plasma effluents exit the perforated partition 422 and promote even distribution of the plasma effluents and precursor gases.
  • the smaller ID may be placed at a variety of locations along the through-holes 430 and still allow the perforated partition 422 to reduce the ion density within substrate processing region 428. The reduction in ion density results from an increase in the number of collisions with walls prior to entry into the substrate processing region 428.
  • the smaller ID of the through-holes 430 may be between about 0.2 mm and about 20 mm. In other embodiments, the smaller ID may be between about 1 mm and 6 mm or between about 0.2 mm and about 5 mm. Further, aspect ratios of the through- holes 430 (/.e., the smaller ID to hole length) may be approximately 1 to 20. The smaller ID of the through-holes 430 may be the minimum ID found along the length of the through-holes 430.
  • the cross sectional shape of through-holes 430 may be generally cylindrical, conical, or any combination thereof.
  • the support assembly 406 may include a substrate support 440 to support a substrate 442 thereon during processing.
  • the substrate support 440 may be coupled to an actuator 444 by a shaft 446 which extends through a centrally-located opening formed in a bottom of the chamber body 402.
  • the actuator 444 may be flexibly sealed to the chamber body 402 by bellows (not shown) that prevent vacuum leakage around the shaft 446.
  • the actuator 444 allows the substrate support 440 to be moved vertically within the chamber body 402 between a processing position and a loading position.
  • the loading position is slightly below the opening of a tunnel (not shown) formed in a sidewall of the chamber body 402.
  • the substrate support 440 has a flat, or a substantially flat, substrate supporting surface for supporting a substrate 442 to be processed thereon.
  • the substrate support 440 may be moved vertically within the chamber body 402 by the actuator 444, which is coupled to the substrate support 440 by the shaft 446.
  • the substrate may be disposed on lift pins 488 to perform additional thermal processing steps, such as performing an annealing step.
  • Figure 5 depicts a process flow diagram of a method 500 of forming a contact layer in a semiconductor structure 600 according to a first embodiment of the present disclosure.
  • Figures 6A, 6B, 6C, 6D, 6E, 6F, and 6G are cross-sectional views of a portion of the semiconductor structure 600 corresponding to various states of the method 500. It should be understood that Figures 6A, 6B, 6C, 6D, 6E, 6F, and 6G illustrate only partial schematic views of the semiconductor structure 600, and the semiconductor structure 600 may contain any number of transistor sections and additional materials having aspects as illustrated in the figures.
  • the semiconductor structure 600 may include a first transistor device 602 and a second transistor device 604 formed on a substrate.
  • the term “substrate” as used herein refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned.
  • the substrate may be a silicon based material or any suitable insulating materials or conductive materials as needed.
  • the substrate may include a material such as crystalline silicon (e.g., Si ⁇ 100> or Si ⁇ 111 >), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.
  • SOI silicon on insulator
  • a portion of a first transistor device 602 of a plurality of first transistor devices formed on the substrate includes a first semiconductor region 606 formed of a first material.
  • a portion of a second transistor device 604 of a plurality of second transistor devices formed on the substrate includes a second semiconductor region 608 formed of a second material.
  • the first and second materials include materials having differing compositions, such that the second material can be selectively etched relative to the first material (7.e. , an etch rate of the second material is higher than an etch rate of the first material).
  • the etch selectivity of the second material i.e., a ratio of the etch rate of the second material to the etch rate of the first material is between about 10:1 to 500:1.
  • Example combinations of the first material and the second material include silicon (Si)Zsilicon germanium (SiGe), germanium (Ge)Zsilicon germanium (SiGe), or silicon (Si)Zgermanium tin (GeSn), respectively.
  • the first semiconductor regions 606 may be doped with n-type dopants such as phosphorus (P), antimony (Sb), with the concentration between about 1 O 20 cm -3 and 5 x 10 21 cm -3 , depending upon the desired conductive characteristic of the first transistor device 602.
  • the second semiconductor regions 608 may be doped with p- type dopants such as boron (B) or gallium (Ga), with the concentration of between about 10 2 ° cm -3 and 5 x 10 21 cm -3 , depending upon the desired conductive characteristic of the second transistor device 604.
  • the semiconductor structure 600 further includes a dielectric layer 610 having a first opening 612 formed over each of the first semiconductor regions 606 and a second opening 614 formed over each of the second semiconductor regions 608.
  • the dielectric layer 610 may be formed of a dielectric material, such as silicon dioxide (SiO2) or silicon nitride (SisN4).
  • the first semiconductor regions 606 and the second semiconductor regions 608 may be formed using any suitable deposition technique, such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the openings 612 and 614 are formed by a patterning technique, such as a lithography and etch process.
  • a deposition technique such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD)
  • a patterning technique such as a lithography and etch process.
  • the method 500 begins with a pre-clean process in block 510.
  • the pre-clean process may be performed in a processing chamber, such as the processing chamber 122 shown in Figure 1 , or the processing chamber 200 shown in Figure 2.
  • the pre-clean process is configured to remove contaminants, such as native oxide layers, or patterning residues (e.g., fluorocarbons) formed on the exposed surfaces of the first semiconductor regions 606 within the first openings 612 and the second semiconductor regions 608 within the second openings 614.
  • the pre-clean process is used to prepare the exposed surfaces of the first semiconductor regions 606 within the first openings 612 and the second semiconductor regions 608 within the second openings 614 on which an epitaxial layer can be formed in a subsequent epitaxial deposition process.
  • the pre-clean process can be used to further modulate a growth rate of a subsequently deposited epitaxial layer on surfaces of the first semiconductor regions 606 (e.g.
  • the modulation of the growth rate of a subsequently deposited epitaxial layer can be performed by controlling amount of residual materials disposed at the surfaces of the first semiconductor regions 606 and the second semiconductor regions 608, such as the amount of remaining oxide material, surface activation process, and/or altering the crystal structure (e.g., promoting an amorphous or crystalline structure) of the material at the surfaces of the first semiconductor regions 606 and the second semiconductor regions 608 after performing the pre-clean process.
  • the pre-clean process can have some etch rate selectivity between a surface of a SiGe:B containing region that is oxidized and a surface of a Si: P containing region that is oxidized, such that the pre-clean process will “clean” SiGe:B surface (e.g., remove the oxides formed thereon) and leave the Si: P surface with at least a portion of an oxide layer formed thereon, for example.
  • the pre-clean process may include an anisotropic remote plasma assisted dry etch process, such as a reactive ion etching (RIE) process, using a plasma formed from a gas including argon (Ar), helium (He), or a combination thereof.
  • RIE reactive ion etching
  • the plasma effluents directionally bombard and remove a remaining dielectric layer within the first opening 612 and the second opening 614.
  • the pre-clean process may include an isotropic plasma etching process, such as a SiCoNiTM dry chemical etching process, using a plasma formed from a gas including ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas, such as nitrogen (N2), hydrogen (H2), or a combination thereof.
  • the dry chemical etching process is selective for oxide layers, and thus does not readily etch silicon, germanium, or nitride layers regardless of whether the layers are amorphous, crystalline or polycrystalline. Selectivity of the dry chemical etching process for oxide versus silicon or germanium is at least about 3:1 , and usually 5:1 or better, sometimes 10:1.
  • the dry chemical etching process is also highly selective of oxide versus nitride.
  • the selectivity of the dry chemical etching process versus nitride is at least about 3:1 , usually 5:1 or better, sometimes 10:1.
  • the pre-clean process may include an inductively coupled plasma (ICP) etching process, using a plasma formed from a gas including chlorine (CI2) and hydrogen (H2), and a carrier gas including argon (Ar) and helium (He).
  • ICP inductively coupled plasma
  • the ICP etching process is used to form deep ridges with smooth sidewalls in silicon.
  • the pre-clean process may include a surface activation process based on the isotropic plasma etching process, such as a SiCoNiTM dry chemical etching process, using a plasma formed from a gas including ammonia (NH3), nitrogen trifluoride (NF3), hydrogen fluoride (HF), or a combination thereof, and a carrier gas, such as nitrogen (N2), hydrogen (H2), or a combination thereof.
  • the plasma cleaning process is a remote plasma assisted dry cleaning process which involves the concurrent exposure of a substrate to HF and NH3, and optionally including plasma by-products of one or more of the gases. Inert gases such as argon and helium may also be used.
  • Any one, or combination of the three gases, inert/HF/NHs may be exposed to energy, as described above, to form a plasma thereof that is used to remove the desired contaminants and passivate at least portions of the surface of the substrate. Any residual compounds remaining on the surface of the substrate after exposing the substrate to the plasma can then be removed by subsequently heating the substrate to a desired temperature.
  • a first selective deposition process is performed to epitaxially form a first contact layer 616 on an exposed surface of the first semiconductor region 606 within the first opening 612, and a second contact layer 618 on an exposed surface of the second semiconductor region 608 within the second opening 614, as shown in Figure 6B.
  • the first selective deposition process may be performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1 , or the processing chamber 300 shown in Figure 3.
  • the first contact layer 616 is subsequently removed, as discussed below.
  • the second contact layer 618 is formed as interfaces between the second semiconductor regions 608 and a metal contact plug to be formed within the second opening 614, to minimize parasitic resistance.
  • the first contact layer 616 and the second contact layer 618 are formed of a third material. Examples of the third material includes silicon germanium (SiGe) with a ratio of germanium (Ge) ranging between 20% and 100%.
  • the first contact layer 616 and the second contact layer 618 may be doped with p- type dopants such as boron (B) or gallium (Ga), with the concentration of between about 1 O 20 cm 3 and 5 x 10 21 cm 3 , depending upon the desired conductive characteristic of the second contact layer 618.
  • the first selective deposition process includes a first deposition process and a first etch process.
  • the first deposition process is an epitaxial deposition process.
  • the selectivity in the first selective deposition process may arise from differences in nucleation of the third material on the exposed surfaces of the first semiconductor regions 606 and the second semiconductor regions 608 (e.g., silicon (Si) or silicon germanium (SiGe)) from that on exposed surfaces of the dielectric layer 610 (e.g., silicon dioxide (SiC ) or silicon nitride (SisN4)).
  • the nucleation may occur at a faster rate on the exposed surfaces of the first semiconductor regions 606 and the second semiconductor regions 608 (e.g., silicon (Si) or silicon germanium (SiGe)) than on the exposed surfaces of the dielectric layer 610 (e.g.
  • silicon dioxide (S i O2) or silicon nitride (SisN4) silicon dioxide (S i O2) or silicon nitride (SisN4)
  • an epitaxial layer of the third material may be formed on the exposed surfaces of the first semiconductor regions 606 and the second semiconductor regions 608 (e.g., silicon (Si) or silicon germanium (SiGe)), while an amorphous layer of the third material may be formed on the exposed surfaces of the dielectric layer 610 (e.g., silicon dioxide (SiCh) or silicon nitride (SisN4)), when the semiconductor structure 600 is exposed to a deposition gas in the first deposition process.
  • the dielectric layer 610 e.g., silicon dioxide (SiCh) or silicon nitride (SisN4)
  • the amorphous layers of the third material formed on the exposed surfaces of the dielectric layer 610 can be etched at a faster rate than the epitaxial layers of the third material formed on the exposed surfaces of the first semiconductor regions 606 and the second semiconductor regions 608, by an appropriate etching gas.
  • an overall result of the first deposition process and the first etch process combined can be epitaxial growth of the third material on the exposed surfaces of the first semiconductor regions 606 and the second semiconductor regions 608, while minimizing growth, if any, of the third material on the exposed surfaces of the dielectric layer 610.
  • the deposition gas includes a silicon-containing precursor, a germanium containing precursor, and a dopant source.
  • the silicon- containing precursor may include silane (SiH4), disilane (Si2He), tetrasilane (Si4Hi 0), or a combination thereof.
  • the germanium-containing precursor may include germane (GeH4), germanium tetrachloride (GeCk), and digermane (Ge2He).
  • the dopant source may include, for example, boron, or gallium, depending upon the desired conductive characteristic of the second contact layer 618.
  • the dopant source may include a precursor diborane (B2H6).
  • the etching gas includes an etchant gas and a carrier gas.
  • the etchant gas may include halogen-containing gas, such as hydrogen chloride (HCI), chlorine (CI2), or hydrogen fluoride (HF).
  • the carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).
  • the first deposition process and the first etch process may be performed at a low temperature less than about 450°C and at a pressure of between 5 Torr and 600 Torr.
  • a cycle of the first deposition and first etch processes may be repeated as needed to obtain a desired thickness of the first contact layer 616 and the second contact layer 618.
  • a thickness of the first contact layer 616 and the second contact layer 618 may be between about 30 A and about 100 A.
  • a patterning process is performed to form a patterning stack 620 over the second semiconductor regions 608 so as to cover the second contact layer 618, as shown in Figure 6C.
  • the patterning process may be performed using a conventional photolithography patterning process.
  • the patterning stack 620 may be deposited onto exposed surfaces of the semiconductor structure 600 using a planarizing fill process (e.g., spin-coating) and subsequently patterned by a suitable lithography and etch process.
  • the patterning stack 620 may be formed of organic dielectric layer (ODL), silicon anti-reflective coating (SiARC), or photoresist.
  • a selective removal process is performed to remove the first contact layer 616 (e.g., silicon germanium (SiGe)) selectively to the first semiconductor regions 606 (e.g., silicon (Si)) and the dielectric layer 610 (e.g., silicon dioxide (SiC ) or silicon nitride (SisN4)), as shown in Figure 6D.
  • the SRP may be performed in a processing chamber, such as the processing chamber 124 shown in Figure 1 , or the processing chamber 400 shown in Figure 4.
  • the SRP includes a plasma etch using plasma effluents formed from a fluorine- containing precursor (e.g. nitrogen trifluoride (NF3)).
  • Plasma effluents from a remote plasma source e.g., the remote plasma source 224 shown in Figure 4
  • a substrate processing region e.g., the substrate processing region 428 shown in Figure 4
  • the plasmas effluents react with exposed surfaces of the semiconductor structure 600 and selectively remove the first contact layer 616 (e.g., silicon germanium (SiGe)) while very slowly removing the first semiconductor regions 606 (e.g., silicon (Si)).
  • the etch selectivity of silicon germanium results partly from the presence of an ion suppressor (e.g., the perforated partition 422 shown in Figure 4) positioned between a chamber plasma region (e.g., the chamber plasma region 426 shown in Figure 4) and the substrate processing region (e.g., the substrate processing region 428 shown in Figure 4).
  • the fluorine-containing precursor includes nitrogen trifluoride, fluorocarbon, atomic fluorine, diatomic fluorine, interhalogen fluoride (e.g. bromine trifluoride, chlorine trifluoride), sulfur hexafluoride, xenon difluoride, or a combination thereof.
  • a diluent gas e.g., argon (Ar), helium (He), nitrogen (N2), or a combination thereof
  • the diluent gas reduces diffusivity of plasma effluents and thus increases the etch selectivity of silicon germanium.
  • the fluorine-containing precursor e.g. nitrogen trifluoride (NF3)
  • NF3 nitrogen trifluoride
  • the fluorine-containing precursor is supplied at a flow rate of between about 5 seem (standard cubic centimeters per minute) and about 40 seem, argon (Ar) at a flow rate of between about 4 seem and about 1500 seem, helium (He) at a flow rate of between about 100 seem and about 5000 seem, and nitrogen (N2) at a flow rate of between about 100 seem and about 5000 seem.
  • the SRP may be performed at a temperature of between about - 20°C and about 60°C and at a pressure of between 1 °Torr and 50°Torr.
  • the etch selectivity of silicon germanium (SiGe) with a ratio of germanium (Ge) of 30% may be higher than 200:1 to phosphorus-doped silicon (Si:P), higher than 500:1 to thermal oxide (SiOx), and higher than 500:1 to silicon nitride (SisN4).
  • a conventional plasma ashing process is performed to remove the patterning stack 620, as shown in Figure 6E.
  • the plasma ashing process may be performed in a processing chamber, such as the processing chamber 122 shown in Figure 1 , or the processing chamber 200 shown in Figure 2.
  • the plasma ashing process can use a plasma formed from a gas including oxygen (O2).
  • the ashing process can use a wet clean process using a solution, such as a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2), to remove residue of the patterning stack 620 on the semiconductor structure 600.
  • a solution such as a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2)
  • a second deposition process is performed, as shown in Figure 6F.
  • the second deposition process may be each performed in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1 , or the processing chamber 300 shown in Figure 3.
  • a metal layer 622 is formed on the exposed surfaces of the first semiconductor regions 606 and the second contact layer 618.
  • the metal layer 622 contacts the second contact layer 618 and provides an electrical connection between a contact plug to be formed within the second openings 614 and the second semiconductor regions 608, while maintaining an electrical connection therethrough.
  • the metal layer 622 may be formed of a metal material, such as titanium (Ti), cobalt (Co), nickel (Ni), molybdenum (Mo), or tantalum (Ta), or silicide thereof.
  • the metal source may include a precursor that includes titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), or molybdenum (Mo) or combination thereof.
  • the second deposition process may be each performed at a temperature of between about 300°C and about 800°C and at a pressure of between 1 °Torr and 50°Torr.
  • a barrier metal layer 624 can also be formed on the exposed inner surfaces of the first opening 612 and the second opening 614, and the exposed surfaces of the dielectric layer 610.
  • the barrier metal layer 624 protects the metal layer 622 and allow nucleation and growth of contact plugs in the first opening 612 and the second opening 614, as discussed below.
  • the barrier metal layer 624 may be formed of a barrier metal material that is titanium nitride (TiN), or tantalum nitride (TaN).
  • the metal layer 622 is a silicide layer that is formed from a portion of the barrier metal layer 624 by use of a spike-anneal process.
  • the metal layer 622 is a silicide layer that is formed by a separate selective deposition process that is performed before forming the barrier metal layer 624.
  • the second deposition process performed in block 560 may include any appropriate deposition process, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like, in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1 , at a temperature of between about 100°C and about 300°C.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • a metal fill process is performed to form a first contact plug 626 in the first opening 612 and a second contact plug 628 in the second opening 614, as shown in Figure 6G.
  • the first contact plug 626 and the second contact plug 628 may be formed of contact plug metal material, such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo).
  • the first contact plug 626 and the second contact plug 628 may include a metal that has a desirable work function.
  • the metal fill process in block 570 may include a chemical vapor deposition (CVD) process using a tungsten- containing precursor, such as WFe, or a cobalt-containing precursor, in a processing chamber, such as the processing chamber 126, 128, or 130 shown in Figure 1.
  • CVD chemical vapor deposition
  • the semiconductor structure 600 may planarized, such as by use of a chemical mechanical planarization (CMP) process.
  • CMP chemical mechanical planarization
  • Figure 7 depicts a process flow diagram of a method 700 of forming a contact layer in a semiconductor structure 800 according to a second embodiment of the present disclosure.
  • Figures 8A, 8B, 8C, 8D, and 8E are cross-sectional views of a portion of the semiconductor structure 800 corresponding to various states of the method 700. It should be understood that Figures 8A, 8B, 8C, 8D, and 8E illustrate only partial schematic views of the semiconductor structure 800, and the semiconductor structure 800 may contain any number of transistor sections and additional materials having aspects as illustrated in the figures.
  • the method 700 begins with a pre-clean process in block 710.
  • the pre-clean process in block 710 is generally the same as the pre-clean process in block 510.
  • the pre-clean process in block 710 may be tailored such that a growth rate of an epitaxial layer of the third material (e.g., silicon germanium (SiGe)) on exposed surfaces of the second semiconductor regions 608 (e.g., silicon germanium (SiGe)) is higher than a growth rate of an epitaxial layer of the third material (e.g., silicon germanium (SiGe)) on exposed surfaces of the first semiconductor regions 606 (e.g., silicon (Si)).
  • a growth rate of an epitaxial layer of the third material e.g., silicon germanium (SiGe)
  • SiGe silicon germanium
  • Knobs for controlling the pre-clean process may include a gas chemistry, a gas ratio, a gas flow rate, a substrate temperature, temperature gradients, a chamber pressure, power and/or frequency of the power source, RF excitation frequencies, duty cycle and/frequency of RF powers, etch time, or a combination thereof.
  • the modulation of the growth rate of a subsequently deposited epitaxial layer can be adjusted by controlling or adjusting the composition of the materials disposed at the surfaces of the first semiconductor regions 606 and the second semiconductor regions 608 and/or altering the crystal structure of the material at the surfaces of the first semiconductor regions 606 and the second semiconductor regions 608 after performing the pre-clean process.
  • a first selective deposition process is performed to epitaxially form a first contact layer 816 on exposed surfaces of the first semiconductor regions 606 within the first opening 612, and a second contact layer 818 on exposed surfaces of the second semiconductor regions 608 within the second opening 614, as shown in Figure 8B.
  • the first selective deposition process in block 720 can in general be the same as the first selective deposition process in block 520.
  • the second contact layer 818 will grow to a greater thickness than the thickness of the first contact layer 816 during the same processing time period.
  • the process parameters used to simultaneously form the second contact layer 818 and the first contact layer 816 are adjusted and/or controlled such that the thickness of the second contact layer 818 formed on the second semiconductor regions 608 is greater than the thickness of the first contact layer 816 formed on the first semiconductor regions 606 during the same processing time period.
  • the growth rate of a silicon germanium (SiGe) containing second contact layer 818 on the silicon germanium (SiGe) containing second semiconductor regions 608 can be made significantly larger than the growth rate of the silicon germanium (SiGe) containing first contact layer 816 on the silicon containing first semiconductor regions 606.
  • the deposition process parameters e.g., temperature, process pressure, precursor gas composition, etc.
  • the first contact layer 816 can be formed to a thickness of between about 5 A and about 100 A and the second contact layer 818 can be formed to a thickness of between about 30A and about 100 A, wherein the thickness of the first contact layer 816 is less than the thickness of the second contact layer 818.
  • a selective removal process is performed to remove the first contact layer 816 (e.g., silicon germanium (SiGe)) selectively to the first semiconductor regions 606 (e.g., silicon (Si)) and the dielectric layer 610 (e.g., silicon dioxide (SiC ) or silicon nitride (S isN4)), as shown in Figure 8C.
  • the SRP in block 730 is the same as the SRP in block 540.
  • the second contact layer 818 is exposed (unlike the second contact layer 618 covered by the patterning stack 620 as shown in Figures 6C and 6D), and thus the second contact layer 818 is also selectively removed.
  • an amount of the first contact layer 816 and the second contact layer 818 is removed, such as all of the first contact layer 816, and thus leaving an amount of the second contact layer 818 remaining over the second semiconductor regions 608 due to the increased thickness of the second contact layer 818 versus the thickness of the first contact layer 816 formed during block 720.
  • a cycle of the first selective deposition process in block 720 and the SRP in block 730 may be repeated as need to obtain a desired thickness of the second contact layer 818.
  • a thickness of the second contact layer 618 may be between about 30 A and about 100 A.
  • a second deposition process is performed to form the metal layer 622 and the barrier metal layer 624, as shown in Figure 8D.
  • the second deposition process provided in block 740 can be the same as the second deposition process in block 560.
  • a metal fill process is performed to form the first contact plug 626 in the first opening 612 and the second contact plug 628 in the second opening 614, as shown in Figure 6E.
  • the metal fill process provided in block 750 can be the same as the metal fill process in block 670.
  • the embodiments described herein provide methods and system for forming a contact epitaxial layer within a trench on a selected portion of a transistor structure.
  • the contact trench structure includes a metal contact plug formed within a trench between adjacent device modules, and contacts that interface between the contact plug and silicon-based channels in the device modules.
  • the contacts are formed by a selective deposition process, reducing parasitic resistance.
  • the metal contact plug is formed void-free by a deposition-each-deposition process, reducing contact resistance.
  • the contact epitaxial layer may be p-type silicon germanium formed on an exposed surface of a p-type MOS device (e.g., silicon germanium) while no epitaxial layer may be formed on an n-type MOS (e.g., silicon) or a dielectric layer formed over the p-type MOS device and the n-type MOS device.
  • a p-type MOS device e.g., silicon germanium
  • n-type MOS e.g., silicon
  • the methods and systems do not require a patterning of an epitaxial layer using a photomask, and thus damages on a fabricated semiconductor structures are reduced.
PCT/US2023/015640 2022-04-19 2023-03-20 Contact formation process for cmos devices Ceased WO2023204918A1 (en)

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US12431360B2 (en) * 2023-07-18 2025-09-30 Applied Materials, Inc. Selective etching between silicon-and-germanium-containing materials with varying germanium concentrations
US12394631B2 (en) * 2023-09-29 2025-08-19 Applied Materials, Inc. Selective etching of silicon-and-germanium-containing materials with increased surface purities

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090239344A1 (en) * 2008-03-24 2009-09-24 Samsung Electronics Co., Ltd. Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance
US20120214303A1 (en) * 2001-07-25 2012-08-23 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US20180277530A1 (en) * 2015-03-09 2018-09-27 Monolithic 3D Inc. Methods for processing a 3d semiconductor device
WO2019190795A1 (en) * 2018-03-26 2019-10-03 Lam Research Corporation Intermediate layer for metal interconnect layer
US11232947B1 (en) * 2020-09-01 2022-01-25 Taiwan Semiconductor Manufacturing Company Limited Ammonium fluoride pre-clean protection

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6596577B2 (en) * 1998-08-25 2003-07-22 Micron Technology, Inc. Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry
US6703279B2 (en) * 2002-01-04 2004-03-09 Promos Technologies, Inc. Semiconductor device having contact of Si-Ge combined with cobalt silicide
US9576809B2 (en) * 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US10685870B2 (en) * 2017-08-30 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120214303A1 (en) * 2001-07-25 2012-08-23 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US20090239344A1 (en) * 2008-03-24 2009-09-24 Samsung Electronics Co., Ltd. Methods of Forming Field Effect Transistors Having Silicided Source/Drain Contacts with Low Contact Resistance
US20180277530A1 (en) * 2015-03-09 2018-09-27 Monolithic 3D Inc. Methods for processing a 3d semiconductor device
WO2019190795A1 (en) * 2018-03-26 2019-10-03 Lam Research Corporation Intermediate layer for metal interconnect layer
US11232947B1 (en) * 2020-09-01 2022-01-25 Taiwan Semiconductor Manufacturing Company Limited Ammonium fluoride pre-clean protection

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4511874A4 *

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