JP2024540486A - 積層ダイのサーマルバイパス - Google Patents

積層ダイのサーマルバイパス Download PDF

Info

Publication number
JP2024540486A
JP2024540486A JP2024529347A JP2024529347A JP2024540486A JP 2024540486 A JP2024540486 A JP 2024540486A JP 2024529347 A JP2024529347 A JP 2024529347A JP 2024529347 A JP2024529347 A JP 2024529347A JP 2024540486 A JP2024540486 A JP 2024540486A
Authority
JP
Japan
Prior art keywords
thermal
block
heat
microelectronic device
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024529347A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024540486A5 (cg-RX-API-DMAC10.html
Inventor
ベルガセム ハーバ
クリストファー オーブション
Original Assignee
アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド filed Critical アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド
Publication of JP2024540486A publication Critical patent/JP2024540486A/ja
Publication of JP2024540486A5 publication Critical patent/JP2024540486A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/10—Arrangements for heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/254—Diamond
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/258—Metallic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Materials Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
JP2024529347A 2021-11-17 2022-11-15 積層ダイのサーマルバイパス Pending JP2024540486A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US202163264214P 2021-11-17 2021-11-17
US63/264,214 2021-11-17
PCT/US2022/049992 WO2023091430A1 (en) 2021-11-17 2022-11-15 Thermal bypass for stacked dies

Publications (2)

Publication Number Publication Date
JP2024540486A true JP2024540486A (ja) 2024-10-31
JP2024540486A5 JP2024540486A5 (cg-RX-API-DMAC10.html) 2025-10-16

Family

ID=86324028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024529347A Pending JP2024540486A (ja) 2021-11-17 2022-11-15 積層ダイのサーマルバイパス

Country Status (7)

Country Link
US (1) US20230154816A1 (cg-RX-API-DMAC10.html)
EP (1) EP4434089A4 (cg-RX-API-DMAC10.html)
JP (1) JP2024540486A (cg-RX-API-DMAC10.html)
KR (1) KR20240103015A (cg-RX-API-DMAC10.html)
CN (1) CN118476024A (cg-RX-API-DMAC10.html)
TW (2) TWI899518B (cg-RX-API-DMAC10.html)
WO (1) WO2023091430A1 (cg-RX-API-DMAC10.html)

Families Citing this family (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US10607136B2 (en) 2017-08-03 2020-03-31 Xcelsis Corporation Time borrowing between layers of a three dimensional chip stack
US10672663B2 (en) 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
TWI910033B (zh) 2016-10-27 2025-12-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
WO2018125673A2 (en) 2016-12-28 2018-07-05 Invensas Bonding Technologies, Inc Processing stacked substrates
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
TWI782939B (zh) 2016-12-29 2022-11-11 美商英帆薩斯邦德科技有限公司 具有整合式被動構件的接合結構
WO2018169968A1 (en) 2017-03-16 2018-09-20 Invensas Corporation Direct-bonded led arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US10991804B2 (en) 2018-03-29 2021-04-27 Xcelsis Corporation Transistor level interconnection methodologies utilizing 3D interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US10923413B2 (en) 2018-05-30 2021-02-16 Xcelsis Corporation Hard IP blocks with physically bidirectional passageways
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
KR102878117B1 (ko) 2018-06-13 2025-10-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 패드로서의 ｔｓｖ
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
US11664357B2 (en) 2018-07-03 2023-05-30 Adeia Semiconductor Bonding Technologies Inc. Techniques for joining dissimilar materials in microelectronics
WO2020010136A1 (en) 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US12406959B2 (en) 2018-07-26 2025-09-02 Adeia Semiconductor Bonding Technologies Inc. Post CMP processing for hybrid bonding
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US11296044B2 (en) 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
US11387202B2 (en) 2019-03-01 2022-07-12 Invensas Llc Nanowire bonding interconnect for fine-pitch microelectronics
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US12374641B2 (en) 2019-06-12 2025-07-29 Adeia Semiconductor Bonding Technologies Inc. Sealed bonded structures and methods for forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US12080672B2 (en) 2019-09-26 2024-09-03 Adeia Semiconductor Bonding Technologies Inc. Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive
US12113054B2 (en) 2019-10-21 2024-10-08 Adeia Semiconductor Technologies Llc Non-volatile dynamic random access memory
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
KR20260009391A (ko) 2019-12-23 2026-01-19 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 결합형 구조체를 위한 전기적 리던던시
KR20260077969A (ko) 2020-03-19 2026-05-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
WO2021236361A1 (en) 2020-05-19 2021-11-25 Invensas Bonding Technologies, Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
WO2022094587A1 (en) 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
KR20230125309A (ko) 2020-12-28 2023-08-29 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 기판-관통 비아를 가지는 구조체 및 이를 형성하기위한 방법
TW202243181A (zh) 2020-12-28 2022-11-01 美商英帆薩斯邦德科技有限公司 具有直通基板穿孔的結構以及形成此結構的方法
TW202618935A (zh) 2020-12-30 2026-05-01 美商艾德亞半導體接合科技有限公司 具有導電特徵的結構以及形成此結構的方法
US12550799B2 (en) 2021-03-31 2026-02-10 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures
JP2024515033A (ja) 2021-03-31 2024-04-04 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 担体の直接ボンディング及び剥離
US12300634B2 (en) 2021-08-02 2025-05-13 Adeia Semiconductor Bonding Technologies Inc. Protective semiconductor elements for bonded structures
KR102849299B1 (ko) * 2021-09-17 2025-08-25 삼성전자주식회사 반도체 패키지 및 그 제조방법
JP2024535904A (ja) 2021-09-24 2024-10-02 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 能動インターポーザ付きのボンデッド構造体
KR20240090512A (ko) 2021-10-19 2024-06-21 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 멀티-다이 스태킹에서의 적층된 인덕터
US12640483B2 (en) 2021-10-22 2026-05-26 Adeia Semiconductor Technologies Llc Radio frequency device packages
JP2024541923A (ja) 2021-10-25 2024-11-13 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 積層化電子デバイス用の電力分配
US12563749B2 (en) 2021-10-28 2026-02-24 Adeia Semiconductor Bonding Technologies Inc Stacked electronic devices
US12604771B2 (en) 2021-10-28 2026-04-14 Adeia Semiconductor Bonding Technologies Inc. Direct bonding methods and structures
JP2024537478A (ja) 2021-11-05 2024-10-10 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド マルチチャンネル型デバイス積層化
US12557615B2 (en) 2021-12-13 2026-02-17 Adeia Semiconductor Technologies Llc Methods for bonding semiconductor elements
JP2025500315A (ja) 2021-12-20 2025-01-09 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド ダイパッケージの熱電冷却
US12622307B2 (en) 2021-12-23 2026-05-05 Adeia Semiconductor Bonding Technologies Inc. Controlled grain growth for bonding and bonded structure with controlled grain growth
US12667031B2 (en) 2021-12-23 2026-06-23 Adeia Semiconductor Bonding Technologies Inc. Direct bonding on package substrates
JP2025514099A (ja) 2022-04-25 2025-05-02 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド ダイレクトボンディング用膨張制御型構造体及びその形成方法
US12707941B2 (en) 2022-05-13 2026-08-11 Adeia Semiconductor Bonding Technologies Inc. Bonding surface validation on dicing tape
JP2025517291A (ja) 2022-05-23 2025-06-05 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド ボンデッド構造体のための試験用素子
US12545010B2 (en) 2022-12-29 2026-02-10 Adeia Semiconductor Bonding Technologies Inc. Directly bonded metal structures having oxide layers therein
US12506114B2 (en) 2022-12-29 2025-12-23 Adeia Semiconductor Bonding Technologies Inc. Directly bonded metal structures having aluminum features and methods of preparing same
US12341083B2 (en) 2023-02-08 2025-06-24 Adeia Semiconductor Bonding Technologies Inc. Electronic device cooling structures bonded to semiconductor elements
US12598962B2 (en) 2023-03-14 2026-04-07 Adeia Semiconductor Bonding Technologies Inc. System and method for bonding transparent conductor substrates

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6822326B2 (en) 2002-09-25 2004-11-23 Ziptronix Wafer bonding hermetic encapsulation
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US8379917B2 (en) 2009-10-02 2013-02-19 DigitalOptics Corporation Europe Limited Face recognition performance using additional image features
KR101715761B1 (ko) * 2010-12-31 2017-03-14 삼성전자주식회사 반도체 패키지 및 그 제조방법
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US11276687B2 (en) * 2013-03-12 2022-03-15 Monolithic 3D Inc. 3D semiconductor device and structure
US8802538B1 (en) * 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
KR102184989B1 (ko) * 2013-09-11 2020-12-01 삼성전자주식회사 반도체 패키지 및 그 제조방법
US12094829B2 (en) * 2014-01-28 2024-09-17 Monolithic 3D Inc. 3D semiconductor device and structure
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
KR101973426B1 (ko) * 2015-11-03 2019-04-29 삼성전기주식회사 전자부품 패키지 및 그 제조방법
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10672663B2 (en) * 2016-10-07 2020-06-02 Xcelsis Corporation 3D chip sharing power circuit
KR102527409B1 (ko) * 2016-12-19 2023-05-02 에스케이하이닉스 주식회사 칩들 사이에 열 전달 블록을 배치한 반도체 패키지 및 제조 방법
US10727151B2 (en) * 2017-05-25 2020-07-28 Infineon Technologies Ag Semiconductor chip package having a cooling surface and method of manufacturing a semiconductor package
US10483187B2 (en) * 2017-06-30 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Heat spreading device and method
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US20190103290A1 (en) * 2017-10-03 2019-04-04 Hewlett Packard Enterprise Development Lp Thermal vapor chamber arrangement
KR20190056190A (ko) * 2017-11-16 2019-05-24 에스케이하이닉스 주식회사 열전달 플레이트를 포함하는 반도체 패키지 및 제조 방법
US10319700B1 (en) * 2017-12-30 2019-06-11 Intel Corporation Stacked semiconductor architecture including semiconductor dies and thermal spreaders on a base die
US10573630B2 (en) * 2018-04-20 2020-02-25 Advanced Micro Devices, Inc. Offset-aligned three-dimensional integrated circuit
US11276676B2 (en) * 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11664357B2 (en) * 2018-07-03 2023-05-30 Adeia Semiconductor Bonding Technologies Inc. Techniques for joining dissimilar materials in microelectronics
US12406959B2 (en) * 2018-07-26 2025-09-02 Adeia Semiconductor Bonding Technologies Inc. Post CMP processing for hybrid bonding
US11011447B2 (en) * 2018-08-14 2021-05-18 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method for forming the same
US11011494B2 (en) * 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11373963B2 (en) * 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11385278B2 (en) * 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
KR102695151B1 (ko) * 2019-08-28 2024-08-16 삼성전자주식회사 반도체 패키지
KR20260077969A (ko) * 2020-03-19 2026-05-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
JPWO2021234849A1 (cg-RX-API-DMAC10.html) * 2020-05-20 2021-11-25
US11721605B2 (en) * 2020-09-24 2023-08-08 Hrl Laboratories, Llc Wafer-level integrated micro-structured heat spreaders
KR20230128062A (ko) * 2020-12-30 2023-09-01 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합 구조
CN113208486B (zh) * 2021-04-07 2026-06-05 厦门倍杰特科技有限公司 一种弹跳芯及马桶盖板连接机构
CN113594154B (zh) * 2021-06-16 2023-08-08 北京无线电测量研究所 一种射频收发前端封装结构及系统
JP2024524391A (ja) * 2021-06-30 2024-07-05 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド 接合層内にルーティング構造体を有する素子

Also Published As

Publication number Publication date
EP4434089A1 (en) 2024-09-25
TWI923378B (zh) 2026-04-21
EP4434089A4 (en) 2025-11-19
TWI899518B (zh) 2025-10-01
KR20240103015A (ko) 2024-07-03
CN118476024A (zh) 2024-08-09
WO2023091430A1 (en) 2023-05-25
TW202545012A (zh) 2025-11-16
US20230154816A1 (en) 2023-05-18
TW202329351A (zh) 2023-07-16

Similar Documents

Publication Publication Date Title
TWI899518B (zh) 用於堆疊晶粒的熱旁路
TWI861605B (zh) 用於晶粒堆疊的流體冷卻
US20230197559A1 (en) Thermoelectric cooling for die packages
US20230197560A1 (en) Thermoelectric cooling in microelectronics
TWI890624B (zh) 用於增強冷卻的半導體封裝結構
US20230245950A1 (en) Heat dissipating system for electronic devices
JP2025500427A (ja) パッケージ基板上の直接接合法
JP2025525650A (ja) 高性能ハイブリッドボンデッド型インターコネクトシステム
CN121772759A (zh) 具有互连结构的键合结构
TWI920751B (zh) 半導體裝置及其製造方法
TW202520909A (zh) 積體電路（ｉｃ）結構及其形成方法
US20250336764A1 (en) Passive thermal control layer for integrated device
TWI220305B (en) 3-dimensional chip stacking packaging structure with heat conduction gain
WO2026030123A1 (en) Structures and methods for thermal dissipation in dies

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20251007

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20251007