JP2024501878A - フィードバック分周器のない低電力フラクショナルアナログpll - Google Patents
フィードバック分周器のない低電力フラクショナルアナログpll Download PDFInfo
- Publication number
- JP2024501878A JP2024501878A JP2023540531A JP2023540531A JP2024501878A JP 2024501878 A JP2024501878 A JP 2024501878A JP 2023540531 A JP2023540531 A JP 2023540531A JP 2023540531 A JP2023540531 A JP 2023540531A JP 2024501878 A JP2024501878 A JP 2024501878A
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- JP
- Japan
- Prior art keywords
- signal
- clock signal
- output
- retimer
- reference clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/139,584 | 2020-12-31 | ||
| US17/139,584 US11095293B1 (en) | 2020-12-31 | 2020-12-31 | Low-power fractional analog PLL without feedback divider |
| PCT/US2021/065528 WO2022147137A1 (en) | 2020-12-31 | 2021-12-29 | Low-power fractional analog pll without feedback divider |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2024501878A true JP2024501878A (ja) | 2024-01-16 |
| JPWO2022147137A5 JPWO2022147137A5 (https=) | 2024-12-19 |
| JP2024501878A5 JP2024501878A5 (https=) | 2024-12-19 |
Family
ID=77274227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023540531A Pending JP2024501878A (ja) | 2020-12-31 | 2021-12-29 | フィードバック分周器のない低電力フラクショナルアナログpll |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US11095293B1 (https=) |
| EP (1) | EP4272315B1 (https=) |
| JP (1) | JP2024501878A (https=) |
| CN (1) | CN116671019A (https=) |
| WO (1) | WO2022147137A1 (https=) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4429116A4 (en) * | 2021-11-30 | 2025-01-15 | Huawei Technologies Co., Ltd. | PHASE CONTROL LOOP, HIGH FREQUENCY TRANSMITTER-RECEIVER AND COMMUNICATION DEVICE |
| US11909409B1 (en) * | 2022-08-23 | 2024-02-20 | Faraday Technology Corp. | Low jitter PLL |
| US11870451B1 (en) * | 2022-12-20 | 2024-01-09 | Viavi Solutions Inc. | Frequency synthesizer using voltage-controlled oscillator (VCO) core of wideband synthesizer with integrated VCO |
| US12525986B2 (en) * | 2023-04-25 | 2026-01-13 | Texas Instruments Incorporated | Digital to analog conversion |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011077480A1 (ja) * | 2009-12-22 | 2011-06-30 | 株式会社 東芝 | 無線装置 |
| JP2012195824A (ja) * | 2011-03-17 | 2012-10-11 | Ricoh Co Ltd | フラクショナルpll回路 |
| WO2020123587A1 (en) * | 2018-12-13 | 2020-06-18 | Texas Instruments Incorporated | Phase-locked loop (pll) with direct feedforward circuit |
| WO2020166645A1 (ja) * | 2019-02-15 | 2020-08-20 | 株式会社ソシオネクスト | デジタル位相同期回路、デジタル制御発振器、デジタル-時間変換器 |
Family Cites Families (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6307906B1 (en) * | 1997-10-07 | 2001-10-23 | Applied Micro Circuits Corporation | Clock and data recovery scheme for multi-channel data communications receivers |
| US6310521B1 (en) * | 1999-12-23 | 2001-10-30 | Cypress Semiconductor Corp. | Reference-free clock generation and data recovery PLL |
| US6907374B1 (en) * | 2003-03-19 | 2005-06-14 | Zilog, Inc. | Self-calibrating sigma-delta analog-to-digital converter |
| JP4373267B2 (ja) * | 2003-07-09 | 2009-11-25 | 株式会社ルネサステクノロジ | スプレッドスペクトラムクロック発生器及びそれを用いた集積回路装置 |
| US7064591B1 (en) * | 2004-05-11 | 2006-06-20 | Rf Micro Devices, Inc. | Coarse tuning for fractional-N synthesizers |
| KR100630343B1 (ko) * | 2004-07-14 | 2006-09-29 | 삼성전자주식회사 | 아날로그 위상 보간 기술을 이용한 클록 데이터 복원 회로및 그 동작 방법 |
| DE102004046404B4 (de) * | 2004-09-24 | 2006-07-20 | Infineon Technologies Ag | Schaltungsanordnung und Verfahren zum Bestimmen einer Frequenzdrift in einem Phasenregelkreis |
| US7486145B2 (en) * | 2007-01-10 | 2009-02-03 | International Business Machines Corporation | Circuits and methods for implementing sub-integer-N frequency dividers using phase rotators |
| GB0805812D0 (en) * | 2008-03-31 | 2008-04-30 | Cambridge Silicon Radio Ltd | Phase locked loop modulation |
| US8289086B2 (en) * | 2008-04-02 | 2012-10-16 | Qualcomm Atheros, Inc. | Fractional and integer PLL architectures |
| DE602008004158D1 (de) * | 2008-10-03 | 2011-02-03 | Swatch Group Res & Dev Ltd | Selbstkalibrierverfahren eines Frequenzgenerators mit Zweipunkt-FSK-Modulation |
| US20180254882A1 (en) * | 2009-01-10 | 2018-09-06 | John W. Bogdan | Synthesizing Clock of OFDM Receiver |
| TWI502308B (zh) * | 2009-07-09 | 2015-10-01 | Univ Nat Taiwan | 全數位展頻時脈產生器 |
| JP2012205046A (ja) * | 2011-03-25 | 2012-10-22 | Renesas Electronics Corp | 半導体集積回路およびその動作方法 |
| US8855215B2 (en) * | 2011-05-09 | 2014-10-07 | The Royal Institution For The Advancement Of Learning/Mcgill University | Phase/frequency synthesis using periodic sigma-delta modulated bit-stream techniques |
| US10205459B2 (en) * | 2012-09-11 | 2019-02-12 | Intel Corporation | Multi-phase fractional divider |
| US9035682B2 (en) * | 2012-12-29 | 2015-05-19 | Motorola Solutions, Inc. | Method and apparatus for single port modulation using a fractional-N modulator |
| US8933733B2 (en) * | 2013-01-07 | 2015-01-13 | Mediatek Singapore Pte. Ltd. | Method and system for fast synchronized dynamic switching of a reconfigurable phase locked loop (PLL) for near field communications (NFC) peer to peer (P2P) active communications |
| US9048847B2 (en) * | 2013-09-24 | 2015-06-02 | Analog Devices Global | Apparatus and methods for synchronizing phase-locked loops |
| TWI533614B (zh) * | 2013-12-04 | 2016-05-11 | 瑞昱半導體股份有限公司 | 具有迴路頻寬校正功能的鎖相迴路裝置及其方法 |
| US9692428B2 (en) * | 2013-12-20 | 2017-06-27 | Texas Instruments Incorporated | Self-calibrating shared-component dual synthesizer |
| US9225348B2 (en) * | 2014-01-10 | 2015-12-29 | International Business Machines Corporation | Prediction based digital control for fractional-N PLLs |
| JP6360386B2 (ja) * | 2014-08-12 | 2018-07-18 | ルネサスエレクトロニクス株式会社 | スペクトラム拡散クロック生成回路 |
| US10175130B2 (en) * | 2015-04-20 | 2019-01-08 | Infineon Technologies Ag | System and method for a MEMS sensor |
| US9553714B2 (en) * | 2015-06-26 | 2017-01-24 | Broadcom Corporation | Frequency multiplier for a phase-locked loop |
| EP3168983B1 (fr) * | 2015-11-13 | 2018-10-17 | The Swatch Group Research and Development Ltd. | Procédé de calibration d'un synthétiseur de fréquence à modulation fsk à deux points |
| US10097190B2 (en) * | 2016-12-19 | 2018-10-09 | Futurewei Technologies, Inc. | Wide capture range reference-less frequency detector |
| US10063365B1 (en) * | 2017-03-10 | 2018-08-28 | Keyssa Systems, Inc. | Re-timer network insertion |
| US10128858B2 (en) * | 2017-04-04 | 2018-11-13 | Intel Corporation | Phase-locked loop circuitry including improved phase alignment mechanism |
| US10236895B1 (en) * | 2017-12-19 | 2019-03-19 | Analog Bits Inc. | Method and circuits for fine-controlled phase/frequency offsets in phase-locked loops |
| KR102474578B1 (ko) * | 2018-01-08 | 2022-12-05 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 동작 방법 |
| EP3573242B1 (en) * | 2018-03-29 | 2025-04-30 | Shenzhen Goodix Technology Co., Ltd. | Frequency generator and frequency generation method |
| US10824764B2 (en) * | 2018-06-27 | 2020-11-03 | Intel Corporation | Apparatus for autonomous security and functional safety of clock and voltages |
| US11545985B2 (en) * | 2018-12-14 | 2023-01-03 | Silicon Laboratories Inc. | Apparatus for digitally controlled oscillators and associated methods |
| JP2020098988A (ja) * | 2018-12-18 | 2020-06-25 | セイコーエプソン株式会社 | 回路装置、発振器、電子機器及び移動体 |
| JP7324013B2 (ja) * | 2019-02-15 | 2023-08-09 | キヤノン株式会社 | 分数分周器および周波数シンセサイザ |
| US10873335B2 (en) * | 2019-05-02 | 2020-12-22 | Apple Inc. | Divider control and reset for phase-locked loops |
| US20200373927A1 (en) * | 2019-05-26 | 2020-11-26 | Jinghang Liang | Differential Alias-Locked Loop |
-
2020
- 2020-12-31 US US17/139,584 patent/US11095293B1/en active Active
-
2021
- 2021-07-14 US US17/375,997 patent/US11303284B1/en active Active
- 2021-12-29 EP EP21916424.1A patent/EP4272315B1/en active Active
- 2021-12-29 CN CN202180088014.1A patent/CN116671019A/zh active Pending
- 2021-12-29 WO PCT/US2021/065528 patent/WO2022147137A1/en not_active Ceased
- 2021-12-29 JP JP2023540531A patent/JP2024501878A/ja active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011077480A1 (ja) * | 2009-12-22 | 2011-06-30 | 株式会社 東芝 | 無線装置 |
| JP2012195824A (ja) * | 2011-03-17 | 2012-10-11 | Ricoh Co Ltd | フラクショナルpll回路 |
| WO2020123587A1 (en) * | 2018-12-13 | 2020-06-18 | Texas Instruments Incorporated | Phase-locked loop (pll) with direct feedforward circuit |
| WO2020166645A1 (ja) * | 2019-02-15 | 2020-08-20 | 株式会社ソシオネクスト | デジタル位相同期回路、デジタル制御発振器、デジタル-時間変換器 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP4272315A1 (en) | 2023-11-08 |
| WO2022147137A1 (en) | 2022-07-07 |
| US11095293B1 (en) | 2021-08-17 |
| US11303284B1 (en) | 2022-04-12 |
| EP4272315A4 (en) | 2024-03-20 |
| EP4272315B1 (en) | 2025-12-17 |
| CN116671019A (zh) | 2023-08-29 |
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