JP2024049705A - Method for manufacturing array substrate, array substrate, and display device - Google Patents

Abstract

[Problem] To improve the alignment accuracy between electrodes and light-shielding portions that overlap in a plan view. [Solution] A method for manufacturing an array substrate 21 includes forming a light-shielding film 42 on the upper layer side of a plurality of switching elements 23, forming a first resist pattern 60 on the light-shielding film 42 corresponding to a layout pattern of a plurality of light-shielding portions 32 for blocking light passing between pixels PX, etching and patterning the light-shielding film 42 using the first resist pattern 60 as a mask, forming a transparent electrode film 44 on the upper layer side of the plurality of light-shielding portions 32, forming a second resist pattern 61 on the transparent electrode film 44 corresponding to a layout pattern of a common electrode 25 having an opening 25S and to which a predetermined reference potential is applied, etching the transparent electrode film 44 with a first corrosive agent using the second resist pattern 61 as a mask to form a common electrode 25, and etching the patterned light-shielding film 42 with a second corrosive agent using the common electrode 25 as a mask to remove an overlapping portion 42A of the light-shielding film 42 with the opening 25S. [Selected Figure] FIG.

Description

The technology described in this specification relates to a method for manufacturing an array substrate, an array substrate, and a display device.

Conventionally, liquid crystal panels, which are a main component of liquid crystal display devices, are configured by sealing a liquid crystal layer between a pair of substrates, with pixel electrodes and switching elements arranged in a matrix on one substrate (array substrate, active matrix substrate). The other substrate (CF substrate, opposing substrate) is formed with color filters and a light-shielding section (black matrix) to prevent color mixing.

The difficulty of aligning the pixel electrodes of the array substrate with the black matrix of the CF substrate increases as the resolution of the liquid crystal panel increases and the pixel pitch becomes smaller. As a solution to this problem, Patent Document 1 discloses a method of forming a black mask (light-shielding portion) on the drive substrate (array substrate) in a self-aligned relationship with the pixel electrodes.

The method of forming the light-shielding portion described in Patent Document 1 forms pixel electrodes by etching a transparent conductive film through a resist. Next, a light-shielding film is formed on top of it, embedding the light-shielding film in the part where the transparent conductive film has been removed. The resist is then removed, and the unnecessary part of the light-shielding film on top of it is removed together with the resist, forming the light-shielding portion. In this way, alignment between a photomask for the light-shielding portion, and in turn, the photomask for the pixel electrode and the photomask for the light-shielding portion is not required. In addition, since the light-shielding portion is etched using the pixel electrode, which is the object of alignment, as a mask, it is in a self-aligned relationship, which is said to improve alignment accuracy.

Japanese Patent Application Laid-Open No. 7-128688

However, the method for forming the light-shielding portion described in Patent Document 1 forms a light-shielding film on a resist, so it is difficult to use a sputtering method or a CVD (chemical vapor deposition) method, which require vacuuming, when forming the light-shielding film. In addition, this method is applicable when the light-shielding portion is formed in a position that does not overlap with the electrode in a planar view, but is not applicable when the two are in an overlapping positional relationship. For example, in the case of FFS (Fringe Field Switching) mode and IPS (In Plane Switching) mode, which switch liquid crystal molecules in a direction including the main surface direction (horizontal direction) of the substrate, the array substrate generally has not only pixel electrodes but also a common electrode to which a reference potential is applied. In reality, it is difficult to improve the alignment accuracy between the common electrode and the light-shielding portion while forming the light-shielding portion in a position that overlaps with the common electrode in a planar view. For example, in ultra-high definition models (e.g., liquid crystal panels for head-mounted displays with over 1000 ppi) that operate in FFS mode, even a misalignment of 1 μm in the light-shielding part relative to the common electrode can disrupt the electric field direction and reduce the light-shielding efficiency, causing color mixing and ultimately degrading display quality.

The technology described in this specification was developed based on the above-mentioned circumstances, and aims to improve the alignment accuracy between the electrodes and the light-shielding portion that overlap in a planar view.

(1) The method for manufacturing an array substrate related to the technology described in the present specification is a method for manufacturing an array substrate in which a plurality of pixels are arranged in a matrix, in which a plurality of switching elements constituting the plurality of pixels are formed on the upper layer side of an insulating substrate, a light-shielding film is formed on the upper layer side of the plurality of switching elements, a first resist pattern corresponding to a layout pattern of a plurality of light-shielding sections for blocking light passing between adjacent pixels is formed on the light-shielding film, the light-shielding film is patterned by etching using the first resist pattern as a mask, a transparent electrode film is formed on the upper layer side of the plurality of light-shielding sections, a second resist pattern corresponding to a layout pattern of a common electrode having a plurality of openings and to which a predetermined reference potential is applied is formed on the transparent electrode film, the transparent electrode film is etched with a first corrosive agent using the second resist pattern as a mask to form the common electrode, and the patterned light-shielding film is etched with a second corrosive agent using the common electrode as a mask to remove the overlapping portions of the patterned light-shielding film with the plurality of openings.

(2) In addition to the above (1), the method for manufacturing the array substrate may further include a configuration in which the first resist pattern has an extension portion that overlaps with the multiple openings of the common electrode.

(3) In addition to the above (1) or (2), the method for manufacturing the array substrate may also be such that the overlapping portion is a protrusion that faces toward the opening when viewed in a plan view.

(4) In addition to any one of (1) to (3) above, the method for manufacturing the array substrate may also include removing the second resist pattern after removing the overlapping portion.

(5) In addition to the above (4), the manufacturing method of the array substrate may further include the following: the first corrosive agent is a chemical solution containing oxalic acid as a main component, and the second corrosive agent is a chemical solution containing a mixture of phosphoric acid, nitric acid, and acetic acid.

(6) In addition to any one of (1) to (3) above, the method for manufacturing the array substrate may also include removing the second resist pattern after etching the transparent electrode film to form the common electrode and before removing the overlapping portion.

(7) In addition to the above (6), the manufacturing method of the array substrate may further include the following: the first corrosive agent is a chemical solution containing oxalic acid as a main component, and the second corrosive agent is ozone water.

(8) In addition to the above (7), the method for manufacturing the array substrate may also include forming an insulating film on the common electrode after removing the overlapping portion.

(9) In addition to any one of (1) to (8) above, the method for manufacturing the array substrate may further include forming a matrix of pixel electrodes connected to the switching elements on the upper layer side of the switching elements, and depositing the light-shielding film on the upper layer side of the pixel electrodes.

(10) In addition to any one of (1) to (9) above, the method for manufacturing the array substrate may also be an array substrate for a display panel used in a head-mounted display.

(11) In addition to the above-mentioned (10), the manufacturing method of the array substrate may also be such that the display panel is a liquid crystal panel.

(12) The array substrate related to the technology described in the present specification is provided on the upper layer side of an insulating substrate, and includes a plurality of switching elements constituting a plurality of pixels, a plurality of pixel electrodes arranged in a matrix on the upper layer side of the plurality of switching elements and connected to the plurality of switching elements, a plurality of light-shielding portions provided on the upper layer side of the plurality of pixel electrodes for blocking light passing between adjacent pixels, and a common electrode provided on the plurality of light-shielding portions, having a plurality of openings, and to which a predetermined reference potential is applied, the plurality of light-shielding portions overlap the common electrode, and the shortest distance between the outer periphery of the plurality of light-shielding portions and the opening edges of the plurality of openings in the main surface direction of the insulating substrate is 0.001 μm or more and less than 1 μm.

(13) The display device related to the technology described in this specification is a display device for a head-mounted display, which includes a display panel having the array substrate described in (12) above.

(14) In addition to the above (13), the display panel of the display device may be a liquid crystal panel.

The technology described in this specification can improve the alignment accuracy between the electrodes and the light-shielding portion that overlap in a plan view.

FIG. 1 is a schematic perspective view showing a state in which a head mounted display according to a first embodiment is used; FIG. 2 is a schematic side view showing the optical relationship between the liquid crystal display device, the lens unit, and the user's eyeball of the head mounted display; Schematic plan view of a liquid crystal display device Equivalent circuit diagram of the display area of the array substrate FIG. 2 is a plan view showing a layout pattern of gate wiring, source wiring, TFTs, and pixel electrodes (shaded). FIG. 6 is a plan view showing the layout pattern of the common electrode in FIG. 5 with the common electrode being shaded. FIG. 6 is a plan view showing a layout pattern of a first light-shielding portion in addition to that of FIG. 5, in which the first light-shielding portion is shown in a shaded pattern. FIG. 6 is a plan view showing the layout patterns of the common electrode, the first light-shielding portion, and the second light-shielding portion in addition to those in FIG. 5, with the second light-shielding portion being shaded. FIG. 9 is an enlarged plan view of the common electrode and the periphery of the second light-shielding portion adjacent to the common electrode; A cross-sectional view of the liquid crystal panel taken along line II in FIG. A cross-sectional view of the liquid crystal panel taken along line II-II in FIG. A cross-sectional view of the liquid crystal panel taken along line III-III in FIG. 17A and 17B are cross-sectional views showing a state in which a second light-shielding film is formed (the manufacturing process of the array substrate cut along line IV-IV in FIGS. 9 and 17A and 17B). 17A and 17B are cross-sectional views showing a state in which a first resist pattern is formed (the manufacturing process of the array substrate cut along line IV-IV in FIGS. 9 and 17). FIG. 2 is a plan view showing an extended portion of the first resist pattern; 17A and 17B are cross-sectional views showing a state in which the second light-shielding film is patterned (the manufacturing process of the array substrate cut along line IV-IV in FIGS. 9 and 17A and 17B). FIG. 4 is a plan view showing an overlapping portion of a patterned second light-shielding film; 17A and 17B are cross-sectional views showing a state in which a second transparent electrode film is formed (the manufacturing process of the array substrate cut along the line IV-IV in FIGS. 9 and 17A and 17B). 17A and 17B are cross-sectional views showing a state in which a second resist pattern is formed (the manufacturing process of the array substrate cut along line IV-IV in FIGS. 9 and 17). 17A and 17B are cross-sectional views showing a state in which a common electrode is formed (the manufacturing process of the array substrate cut along the line IV-IV in FIGS. 9 and 17A and 17B). 17A and 17B are cross-sectional views showing a state in which the overlapping portion of the patterned second light-shielding film is etched (the manufacturing process of the array substrate cut along the line IV-IV in FIGS. 9 and 17A and 17B). 17A and 17B are cross-sectional views showing a state in which the second resist pattern has been peeled off (the manufacturing process of the array substrate cut along line IV-IV in FIGS. 9 and 17). FIG. 1 is a cross-sectional view showing an array substrate according to a first comparative example. FIG. 11 is a cross-sectional view showing an array substrate according to a second comparative example. Electron microscope photograph taken in evaluation experiment 1 (etching time: 28 seconds) 11 is a cross-sectional view showing a state in which the second resist pattern has been peeled off in a manufacturing process of the array substrate according to the second embodiment. FIG. 11 is a cross-sectional view showing a state in which an overlapping portion of the patterned second light-shielding film is etched in a manufacturing process of the array substrate according to the second embodiment. Electron microscope photograph taken in evaluation experiment 2 (etching time: 270 seconds)

<Embodiment 1>
The configuration and manufacturing method of the array substrate 21 according to the first embodiment will be described with reference to Figs. 1 to 25. In this embodiment, a liquid crystal display device 10 for a goggle-type head-mounted display (HMD) 10HMD is illustrated as a display device including the array substrate 21. Note that some of the drawings show an X-axis, a Y-axis, and a Z-axis, and each axis direction is drawn so as to be a common direction in each drawing. Also, with respect to the Z-axis direction, the upper side of the drawing is the front side, and the lower side is the back side.

As shown in FIG. 1, the head-mounted display 10HMD includes a head-mounted device 10HMDa that is attached to the user's head 10HD. The head-mounted device 10HMDa surrounds both of the user's eyes.

As shown in FIG. 2, the head-mounted device 10HMDa includes a liquid crystal display device 10 that displays an image and a lens unit 10RE that focuses the image displayed on the liquid crystal display device 10 on the user's eyeball 10EY. The liquid crystal display device 10 includes a liquid crystal panel (display panel) 11 and a backlight device 12 that is an illumination device that irradiates the liquid crystal panel 11 with light. The main surface of the liquid crystal panel 11 that faces the lens unit 10RE is the display surface 11DS that displays the image. The lens unit 10RE is interposed between the liquid crystal display device 10 and the user's eyeball 10EY. By adjusting the focal length of the lens unit 10RE, the user can recognize that the image focused on the retina 10EYb via the crystalline lens 10EYa of the eyeball 10EY is displayed on the virtual display 10VD that appears to be located at a distance L2 from the eyeball 10EY. This distance L2 is much greater than the actual distance L1 from the eyeball 10EY to the liquid crystal display device 10. This allows the user to view an enlarged image, which is a virtual image, displayed on the virtual display 10VD, which has a screen size (e.g., several tens of inches to several hundred inches) that is much larger than the screen size of the liquid crystal display device 10 (e.g., several tenths of an inch to a few inches).

It is possible to mount one liquid crystal display device 10 on the head-mounted device 10HMDa and display an image for the right eye and an image for the left eye on that liquid crystal display device 10. Alternatively, it is possible to mount two liquid crystal display devices 10 on the head-mounted device 10HMDa and display an image for the right eye on one liquid crystal display device 10 and an image for the left eye on the other liquid crystal display device 10.

As shown in FIG. 3, the liquid crystal panel 11 is equipped with a driver 13 for driving the display and a flexible substrate 14. A control circuit substrate (signal supply source) 15 that supplies various input signals from the outside to the driver 13 is connected to the flexible substrate 14. The backlight device 12 has a known configuration, and includes, for example, a light source such as an LED and an optical member that converts the light from the light source into planar light by applying an optical effect.

As shown in FIG. 3, the central portion of the main surface of the liquid crystal panel 11 is a display area (active area) AA capable of displaying an image. The outer peripheral portion of the main surface of the liquid crystal panel 11 surrounding the display area AA is a non-display area (non-active area) NAA that is frame-shaped when viewed in a plane. In FIG. 3, the dashed line represents the outer shape of the display area AA, and the area outside the dashed line is the non-display area NAA. The liquid crystal panel 11 is formed by bonding a pair of substrates 20 and 21. Of the pair of substrates 20 and 21, the front substrate is the counter substrate (CF substrate) 20, and the back substrate is the array substrate (active matrix substrate) 21. The counter substrate 20 and the array substrate 21 each have a nearly transparent glass substrate (insulating substrate) 20GS and 21GS, and have a structure in which various films are laminated on the inner side of each glass substrate 20GS and 21GS. In addition, a polarizing plate is attached to the outer surface of each of the substrates 20 and 21.

As shown in FIG. 4, a plurality of gate wirings (scanning wirings) 26 and source wirings (image wirings) 27 are arranged in a grid pattern in the display area AA of the array substrate 21. Near the intersections of the gate wirings 26 and source wirings 27, one TFT (switching element, thin film transistor) 23 is provided. The gate wirings 26 extend along the X-axis direction across the display area AA and are connected to the gate electrodes 23G of each TFT 23. The source wirings 27 extend along the Y-axis direction across the display area AA and are connected to the source electrodes 23G of each TFT 23. The TFT 23 is connected to the source electrode 23S and drain electrode 23D and has a semiconductor portion 23C in which a channel is formed.

The pixel electrode 24 is connected to the drain electrode 23D of the TFT 23. When the TFT 23 is driven based on a scanning signal supplied to the gate line 26, the pixel electrode 24 is charged to a potential based on an image signal (data signal) supplied to the source line 27. Multiple TFTs 23 and pixel electrodes 24 are arranged in a matrix on a plane. A predetermined reference potential (common potential) is applied to the common electrode 25.

Next, the planar layout pattern of the display area AA of the array substrate 21 will be described with reference to FIG. 5 to FIG. 9. As shown in FIG. 5, the pixel electrode 24 is arranged in an area surrounded by two gate wirings 26 spaced apart in the Y-axis direction and two source wirings 27 spaced apart in the X-axis direction. The pixel electrode 24 has a vertically elongated rectangular shape in a plan view in accordance with the planar shape of this area. The source wiring 27 is partially widened, and the widened portion constitutes the source electrode 23S of the TFT 23. The central portion between the adjacent source wirings 27 of the gate wiring 26 also serves as the gate electrode 23G. The drain electrode 23D overlaps with the pixel electrode 24 and is provided in a position close to the gate electrode 23 (below the pixel electrode 24 in FIG. 5). The pixel electrode 24 and the drain electrode 23D are connected to each other through a contact hole (see FIG. 11). The semiconductor portion 23C is provided so that one end is connected to the source electrode 23S and the other end is connected to the drain electrode 23D. The semiconductor portion 23C is bent in a roughly J-shape so as to overlap the gate electrode 23G on the way from the source electrode 23S to the drain electrode 23D.

The common electrode 25 is formed at least in almost the entire display area AA. As shown in FIG. 6, the common electrode 25 overlaps all the pixel electrodes 24, and has an opening 25S at each overlapping portion with each pixel electrode 24. Each opening 25S is elongated and extends in a direction inclined with respect to the Y-axis direction. Most of the opening edge 25S1 of the opening 25S overlaps with the pixel electrode 24. When the pixel electrode 24 is charged, a fringe electric field (diagonal electric field) including a component along the main surface of the array substrate 21 and a component normal to the main surface of the array substrate 21 is generated between the pixel electrode 24 and the opening edge 25S1 of the common electrode 25. This fringe electric field controls the alignment state of the liquid crystal molecules contained in the liquid crystal layer 22. In other words, the liquid crystal panel 11 according to this embodiment operates in a type of FFS mode.

In the display area AA of the array substrate 21, a plurality of first light-shielding portions 31 and a plurality of second light-shielding portions 32 are provided. As shown in FIG. 7, the first light-shielding portion 31 extends along the X-axis direction wider than the gate wiring 26. The first light-shielding portion 31 overlaps most of the semiconductor portion 23C. As described later, the first light-shielding portion 31 is arranged on the lower layer side of the semiconductor portion 23C (FIGS. 10 to 12), and blocks light irradiated from the backlight device 12. This makes it possible to suppress fluctuations in the characteristics of the TFT 23 that may occur when light is irradiated to the semiconductor portion 23C. In addition, the first light-shielding portion 31 has a bulge portion 31A that bulges out in a circular shape according to the size of the spacer 50 in a portion overlapping with the spacer 50 of the counter substrate 20 described later. The bulge portion 31A also functions as a spacer light-shielding portion that shields the spacer 50 and its surrounding area from light and makes the spacer 50 less visible from the outside.

8, the second light shielding portion 32 is elongated along the Y-axis direction so as to straddle two first light shielding portions 31 spaced apart in the Y-axis direction. A plurality of second light shielding portions 32 are provided at intervals in the X-axis direction and the Y-axis direction. The second light shielding portion 32 overlaps the source wiring 27 and is formed wider than the source wiring 27. The second light shielding portion 32 blocks light passing between pixels PX exhibiting different colors, thereby suppressing color mixing between the pixels PX. In order to improve light shielding efficiency, the second light shielding portion 32 is preferably disposed as high up as possible (close to the opposing substrate 20) on the array substrate 21. The second light shielding portion 32 according to this embodiment is disposed directly under the common electrode 25 provided on the upper side of the TFT 23 and the pixel electrode 24 (FIG. 12).

The second light-shielding portion 32 is formed between two adjacent openings 25S of the common electrode 25 and does not overlap the openings 25S. In other words, the second light-shielding portion 32 does not overlap the openings 25S, but overlaps the portions of the common electrode 25 other than the openings 25S. The portion of the outer peripheral edge 32A of the second light-shielding portion 32 that is close to the opening edge 25S1 of the opening 25S (the portion surrounded by a dashed line in FIG. 8) is aligned with high precision by a manufacturing method described later so as not to protrude into the opening 25S. More specifically, the outer peripheral edge 32A of the second light-shielding portion 32 and the opening edge 25S1 of the common electrode 25 are aligned so as to approximately coincide with each other. Microscopically, the shortest distance L3 (see FIG. 24) between the two in the X-Y plane (the main surface direction of the glass substrate 21GS) is aligned to be at least less than 1 μm. As shown in Evaluation Experiment 1 described later, the shortest distance L3 can be made less than 0.1 μm by adjusting the materials used in the manufacturing method. In theory, the shortest distance L3 can be made 0 μm, but in practice it can be adjusted to 0.001 μm or more and less than 0.1 μm.

Next, the cross-sectional structure of the liquid crystal panel 11 will be described with reference to Figures 10 to 12. The liquid crystal panel 11 has a liquid crystal layer 22 that is disposed between a pair of substrates 20, 21 and contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. Between the substrates 20, 21, columnar spacers (photospacers) 50 are provided so as to penetrate the liquid crystal layer 22. The spacers keep the distance between the substrates 20, 21, i.e., the cell gap, constant across the surface.

As shown in Figs. 10 to 12, the display area AA of the counter substrate 20 is provided with three color filters 28, each of which has a blue (B), green (G) and red (R) color. The color filters 28 of different colors extend along the direction in which the source wiring 27 extends (Y-axis direction) and are arranged side by side in the direction in which the gate wiring 26 extends (X-axis direction). The color filters 28 overlap with each pixel electrode 24 on the array substrate 21 side in a plan view, and their boundaries (color boundaries) overlap with the source wiring 27. The R, G and B color filters 28 arranged along the X-axis direction and the three pixel electrodes 24 facing each color filter 28 constitute the three-color pixels PX of the liquid crystal panel 11. The three-color pixels PX constitute a display pixel capable of displaying a predetermined gradation of color.

The liquid crystal panel 11 according to this embodiment is used in the head mounted display 10HMD described above, and therefore has extremely high definition, with the pixel density of the liquid crystal panel 11 being, for example, about 1200 ppi. The arrangement pitch of the pixels PX in the X-axis direction is, for example, about 7 μm. The arrangement pitch of the pixels PX in the Y-axis direction is, for example, about three times the arrangement pitch in the X-axis direction.

The opposing substrate 20 is provided with a black matrix 29, which is a light-shielding portion, to block light irradiated from the backlight device 12. As shown in FIG. 10, the black matrix 29 is provided to separate a plurality of color filters 28 of different colors. The black matrix 29 is made of a light-shielding material having light-shielding properties (e.g., a material in which a photosensitive resin material such as acrylic or polyimide contains a pigment such as carbon black). The black matrix 29 extends in an approximately linear manner at least along the Y-axis direction, and a plurality of black matrices 29 are provided at intervals to sandwich the color filters 28 of different colors. The black matrix 29 is arranged to overlap with the source wiring 27 of the array substrate 21. The black matrix 29, together with the second light-shielding portion 32 and the source wiring 27 made of metal having light-shielding properties, suppresses color mixing that may occur between pixels PX of different colors. In addition, an overcoat film 30 is provided on the upper layer side (liquid crystal layer 22 side) of the color filter 28. Furthermore, an alignment film for aligning the liquid crystal molecules contained in the liquid crystal layer 22 is formed on the innermost surface (uppermost layer) of each of the substrates 20 and 21 that contacts the liquid crystal layer 22.

As shown in Figures 10 to 12, the array substrate 21 is laminated with the following layers from the lower layer side (glass substrate 21GS side): a first light-shielding portion 31 made of a first light-shielding film, a base coat film 35, a semiconductor portion 23C made of a semiconductor film, a gate insulating film 36, a gate electrode 23G made of a gate metal film, and a gate wiring 26, a first interlayer insulating film 37, a source electrode 23S made of a source metal film, a drain electrode 23D, and a source wiring 27, a second interlayer insulating film 38, a planarizing film 39, a pixel electrode 24 made of a first transparent electrode film, a bump film 40, a third interlayer insulating film 41, a second light-shielding portion 32 made of a second light-shielding film 42, a common electrode 25 made of a second transparent electrode film 44, and a protective insulating film 45.

The first light-shielding portion 31 is made of a first light-shielding film formed on the glass substrate 21GS. The semiconductor portion 23C is formed on the upper layer side of the first light-shielding portion 31 via a base coat film 35. The first light-shielding portion 31 and the semiconductor portion 23C are insulated by the base coat film 35. The semiconductor portion 23C is made of a semiconductor film. The gate electrode 23G and the gate wiring 26 are made of a gate metal film. The gate metal film is formed on the upper layer side of the semiconductor portion 23C via a gate insulating film 36. The source electrode 23S, the drain electrode 23D, and the source wiring 27 are made of a source metal film. The source metal film is formed on the upper layer side of the gate metal film via a first interlayer insulating film 37. Therefore, the TFT 23 is a top-gate type TFT.

The pixel electrode 24 is formed on the upper layer side of the source metal film via an insulating film (a second interlayer insulating film 38 and a planarizing film 39). The pixel electrode 24 is made of a first transparent electrode film. A bump film 40, which is an insulating film, is formed on the pixel electrode 24. The bump film 40 fills the contact hole and protrudes in the Z-axis direction to receive the spacer 50 formed on the opposing substrate 20. The bump film 40 extends along the X-axis direction with a width wider than the gate wiring 26, and is further widened at the overlapping position with the spacer 50 to receive the spacer 50. The planar shape of the bump film 40 roughly follows the first light shielding portion 31.

A third interlayer insulating film 41 is formed on the bump film 40. A second light-shielding portion 32 made of a second light-shielding film 42 is formed on the third interlayer insulating film 41. The third interlayer insulating film 41 insulates the pixel electrode 24 from the second light-shielding portion 32, and the pixel electrode 24 from the common electrode 25. A common electrode 25 made of a second transparent electrode film 44 is formed on the second light-shielding portion 32. A protective insulating film 45 is formed on the common electrode 25.

The first light-shielding film and the second light-shielding film 42 are made of, for example, an alloy metal material of molybdenum (Mo) and tungsten (W). The materials of the first light-shielding film and the second light-shielding film 42 may be the same or different. The base coat film 35, the gate insulating film 36, the first interlayer insulating film 37, the second interlayer insulating film 38, the third interlayer insulating film 41, and the protective insulating film 45 are made of a transparent inorganic insulating material that is a single layer or a laminate of silicon oxide (SiOx), silicon oxynitride (SiON), silicon nitride (SiNx), etc. The planarizing film 39 and the bump film 40 are made of a transparent organic insulating material such as, for example, acrylic resin (PMMA, etc.) or polyimide resin. Note that each film made of an organic insulating material usually has a larger film thickness than each film made of an inorganic insulating material. The semiconductor film is made of, for example, a polycrystalline silicon thin film in which a metal material is added to an amorphous silicon thin film. The gate metal film and the source metal film are made of a single layer film of a metal such as copper (Cu), an alloy, or a laminate film of these. The materials of the gate metal film and the source metal film may be the same or different. The first transparent electrode film and the second transparent electrode film 44 are made of transparent electrode materials such as ITO (indium tin oxide) and IZO (indium zinc oxide).

Next, a method for manufacturing the array substrate 21 will be described. The process for forming the first light-shielding portion 31 through the third interlayer insulating film 41 on the glass substrate 21GS in the above-mentioned stacking order can be appropriately performed using the same manufacturing process as the known photolithography method. Below, the manufacturing process after the formation of the third interlayer insulating film 41 will be described in detail with reference to Figures 13 to 22.

After the third interlayer insulating film 41 is formed, the second light-shielding film 42 is formed by sputtering, CVD, or the like (FIG. 13, step S1 of forming the second light-shielding film 42). A first resist film is applied on the formed second light-shielding film 42, exposed, and developed to form a first resist pattern 60 (FIG. 14, step S2 of forming the first resist pattern 60). The first resist pattern 60 corresponds to the layout pattern of the second light-shielding portion 32 and has an extension portion 60A in a part thereof. The extension portion 60A is provided in a portion adjacent to the opening edge portion 25S1 of the opening 25S as shown in FIG. 15, and is formed to be slightly larger than the layout pattern of the second light-shielding portion 32 (FIG. 8). As described above, the second light-shielding portion 32 has a planar shape that does not protrude into the opening 25S of the common electrode 25 and does not overlap with the opening 25S, but the extension portion 60A protrudes into the opening 25S formed in a later process (common electrode formation process S6) and overlaps with the opening 25S. The shape of the photomask used when exposing the first resist film is designed so that the first resist pattern 60 includes the extension portion 60A.

After the first resist pattern forming step S2, the second light-shielding film 42 is etched using the first resist pattern 60 as a mask. The second light-shielding film 42 is patterned by etching (FIG. 16, patterning step S3 of the second light-shielding film 42). The corrosive agent used for the etching is not particularly limited. The patterned light-shielding film 42 corresponds to the layout pattern of the second light-shielding portion 32, and includes a portion 42A that remains covered by the extension portion 60A of the first resist pattern 60. As shown in FIG. 17, this remaining portion 42A becomes an overlapping portion 42A that overlaps with the opening 25S of the common electrode 25 formed in a subsequent step (forming step S6 of the common electrode 25). In this embodiment, the overlapping portion 42A protrudes into the opening 25S in a planar shape, but the shape is not limited.

After the patterning step S3 of the second light-shielding film, the first resist pattern 60 is peeled off (removed). After peeling, the second transparent electrode film 44 is formed on the patterned second light-shielding film 42 (FIG. 18, forming step S4 of the second transparent electrode film). A second resist film is applied on the formed second transparent electrode film 44, exposed, and developed to form a second resist pattern 61 (FIG. 19, forming step S5 of the second resist pattern 61). The second resist pattern 61 corresponds to the layout pattern of the common electrode 25. Next, the second transparent electrode film 44 is etched with a first corrosive agent using the second resist pattern 61 as a mask to form a common electrode 25 having an opening 25S (FIG. 20, forming step S6 of the common electrode 25). For the first corrosive agent, for example, an oxalic acid-based chemical solution containing oxalic acid as a main component is used.

After the common electrode forming step S6, the patterned second light-shielding film 42 is etched with a second corrosive agent using the formed common electrode 25 as a mask. By etching, only the overlapping portion 42A of the patterned second light-shielding film 42 that overlaps with the opening 25S of the common electrode 25 is selectively removed (FIG. 21, etching step S7 of the overlapping portion 42A). As a result, the second light-shielding portion 32 has the planar shape shown in FIGS. 8 and 9, and the second light-shielding portion 32 is aligned so as not to overlap with the opening 25S. The second corrosive agent is a corrosive agent different from the first corrosive agent and capable of more selectively etching the second light-shielding film 42 than the common electrode 25 (a corrosive agent whose corrosion rate of the second light-shielding film 42 is greater than that of the second transparent electrode film 44). For example, a PAN-based chemical solution containing a mixture of phosphoric acid, nitric acid, and acetic acid is used for the second corrosive agent.

After etching step S7 of the overlapping portion 42A, the second resist pattern 61 is stripped off (FIG. 22, stripping step S8 of the second resist pattern 61). Then, a protective insulating film 45 is formed on the common electrode 25. The protective insulating film 45 can be formed by appropriately using the same manufacturing process as a known photolithography method.

Next, the effect of the above-mentioned manufacturing method of the array substrate 21 will be described. In the patterning step S3 of the second light-shielding film 42, the second light-shielding film 42 is patterned to have an overlapping portion 42A with the opening 25S of the common electrode 25 (FIG. 16). In the etching step S7 of the overlapping portion 42A, the overlapping portion 42A is removed by etching using the common electrode 25 as a mask (FIG. 21). In this way, if the overlapping portion 42A is formed in the second light-shielding film 42 in advance and the overlapping portion 42A is removed using the common electrode 25, which is the counterpart to be aligned in a later process, as a mask, the opening 25S of the common electrode 25 and the second light-shielding portion 32 are in a so-called self-aligned relationship. As a result, the portion of the outer peripheral edge portion 32A of the second light-shielding portion 32 that is close to the opening edge portion 25S1 of the opening 25S (the portion surrounded by a dashed line in FIG. 8) is aligned with high precision so as not to protrude into the opening 25S.

If the etching step S7 of the overlapping portion 42A is not performed, the outer peripheral edge portion 32A of the second light-shielding portion 32 will protrude into the opening 25S, as in the array substrate 821 according to Comparative Example 1 shown in FIG. 22. That is, the second light-shielding portion 32 will include a portion that overlaps with the opening 25S. In this case, the electric field direction generated between the opening edge portion 25S1 of the common electrode 25 and the pixel electrode 24 will be disturbed. As a result, the optical characteristics of the liquid crystal molecules contained in the liquid crystal layer 22 will no longer change as designed, leading to a deterioration in display quality.

Therefore, if the outer peripheral edge 32A of the second light-shielding portion 32 is formed so as not to protrude into the opening 25S, if the etching process S7 of the overlapping portion 42A is not performed, the shortest distance L3 between the outer peripheral edge 32A and the opening edge 25S1 may become too large, at 1 μm or more, as shown in the array substrate 921 according to Comparative Example 2 shown in FIG. 24. This is because a positional misalignment of about 0.5 μm to 1.0 μm occurs in the XY plane direction between the first resist pattern 60 and the second resist pattern 61 due to manufacturing variations. If the shortest distance L3 becomes too large, at 1 μm or more, the light-shielding efficiency of the second light-shielding portion 32 decreases, resulting in color mixing.

In this embodiment, the etching process S7 of the overlapping portion 42A can reduce the shortest distance L3 between the outer peripheral edge portion 32A and the opening edge portion 25S1 to less than 1 μm. By adjusting the materials used in the manufacturing method, the shortest distance L3 can also be reduced to less than 0.1 μm, as shown in Evaluation Experiment 1 described below.

In addition, in the above-mentioned first resist pattern 60 formation step S2, the first resist pattern 60 is formed to have an extension portion 60A that overlaps with the opening 25S of the common electrode 25. This ensures that the second light-shielding film 42 is patterned in a manner that includes the overlapping portion 42A in the second light-shielding film 42 patterning step S3.

As shown in FIG. 17, the overlapping portion 42A of the second light-shielding film 42 is a protrusion that protrudes from the opening edge portion 25S1 of the opening 25S toward the inside of the opening 25S in a plan view. In this way, the overlapping portion 42A can be removed in a short time in the etching step S7 of the overlapping portion 42A.

In addition, in the deposition process S1 of the second light-shielding film 42, the second light-shielding film 42 is not deposited with the resist film remaining thereon as in Patent Document 1. Therefore, there is no concern even if a sputtering method or a CVD method that requires vacuum drawing is used when depositing the second light-shielding film 42.

<Evaluation Experiment 1>
Evaluation experiment 1 was conducted to evaluate the alignment accuracy of the above-mentioned manufacturing method of array substrate 21. In evaluation experiment 1, after performing etching step S7 of overlapping portion 42A, an electron microscope photograph was taken and the shortest distance L3 between outer peripheral edge 32A of second light-shielding portion 32 and opening edge 25S1 of opening 25S of common electrode 25 was measured.

<Conditions>
Material and thickness of the second transparent electrode film 44 (common electrode 25): ITO, 70 nm
Material and thickness of the second light-shielding film 42 (second light-shielding portion 32): alloy metal of Mo and W, 50 nm
Material and thickness of third interlayer insulating film 41: SiNx, 80 nm
Material and thickness of the first transparent electrode film (pixel electrode 24): IZO, 75 nm
Material and film thickness of the planarization film 39: organic insulating material, 2000 nm
First etchant: oxalic acid-based chemical Second etchant: PAN-based chemical Etching equipment: single-wafer wet etching equipment Etching time in etching step S7 of overlapping portion 42A: 28 seconds, 32 seconds, or 36 seconds

The results of evaluation experiment 1 will be described. As shown in FIG. 25, it was confirmed that the overlapping portion 42A was properly removed at 28 seconds, which is the shortest time that can be set as the etching time in the etching device used. In this case, the shortest distance L3 between the outer peripheral edge 32A of the second light-shielding portion 32 and the opening edge 25S1 of the opening 25S of the common electrode 25 was measured to be very small at about 0.08 μm. It was also confirmed that when the etching time was extended to 32 seconds, the shortest distance L3 decreased to about 0.05 μm. On the other hand, it was confirmed that the shortest distance L3 remained at about 0.05 μm even when the etching time was further extended to 36 seconds. Therefore, it was confirmed that when the etching time reached a predetermined threshold value or more (for example, 32 seconds or more in evaluation experiment 1), the etching progress was saturated and the shortest distance L3 stabilized at a constant value. In the etching process S7 for the overlapping portion 42A, the etching time is set to a predetermined threshold value or more, so that the outer peripheral edge portion 32A of the second light-shielding portion 32 and the opening edge portion 25S1 of the opening 25S of the common electrode 25 can be aligned with extremely high precision.

<Embodiment 2>
A manufacturing method of the array substrate 21 according to the second embodiment will be described with reference to Fig. 26 to Fig. 28. The manufacturing process according to this embodiment differs from that of the first embodiment in the order of the etching step S7 of the overlapping portion 42A and the peeling step S8 of the second resist pattern 61, and in the type of the second corrosive agent. A duplicated description of the configuration and the effects similar to those of the first embodiment will be omitted.

In this embodiment, after the common electrode forming step S6, and before the overlapping portion 42A is etched in step S7, the second resist pattern 61 is stripped in step S8 (FIG. 26). After the second resist pattern 61 is stripped, the overlapping portion 42A is etched in step S7 (FIG. 27). In step S7, ozone water is used as the second corrosive agent. Then, a protective insulating film 45 is formed on the common electrode 25.

When ozone water is used as the second corrosive agent, the second light-shielding film 42 can be oxidatively etched if the second light-shielding film 42 is made of a Mo-based metal material. Oxidative etching makes it possible to selectively etch the overlapping portion 42A of the second light-shielding film 42 more reliably without etching the common electrode 25. Therefore, there is no problem even if the second resist pattern 61 is peeled off before performing the etching process S7 of the overlapping portion 42A.

In this way, when forming the protective insulating film 45, the etching process S7 of the overlapping portion 42A can be performed by the ozone water cleaning process that is usually performed as a pre-processing. As a result, it is possible to eliminate the additional process required to align the outer peripheral edge portion 32A of the second light-shielding portion 32 with the opening edge portion 25S1 of the opening 25S of the common electrode 25 with high precision.

<Evaluation Experiment 2>
Evaluation experiment 2 was conducted to evaluate the alignment accuracy of the above-mentioned manufacturing method of the array substrate 21. In evaluation experiment 2, after the etching process S7 of the overlapping portion 42A was performed using ozone water, pure water washing (about 20 seconds) and spin drying (about 40 seconds) were performed in this order, and an electron microscope photograph was taken. In evaluation experiment 2, explanations that overlap with evaluation experiment 1 will be omitted.

<Conditions>
- Second corrosive agent: Ozone water (ozone concentration 20 ppm)
Etching device: spin cleaning device Etching time in etching step S7 of overlapping portion 42A: 180 seconds, 270 seconds, or 360 seconds

The results of evaluation experiment 2 will be described. As shown in FIG. 28, it was confirmed that the overlapping portion 42A was properly removed at an etching time of 270 seconds. In this case, the shortest distance L3 between the outer peripheral edge 32A of the second light-shielding portion 32 and the opening edge 25S1 of the opening 25S of the common electrode 25 was measured to be small at about 0.19 μm. It was confirmed that when the etching time was extended to 360 seconds, the selective etching of the second light-shielding film 42 progressed, and the shortest distance L3 increased to about 0.31 μm. On the other hand, it was confirmed that the overlapping portion 42A was not completely removed and remained at an etching time of 180 seconds. Therefore, it was confirmed that in embodiment 2, the etching speed was slower than in embodiment 1, and it was easier to control the shortest distance L3 to a desired value. As a result, the outer peripheral edge 32A of the second light-shielding portion 32 and the opening edge 25S1 of the common electrode 25 can be aligned with very high precision.

<Other embodiments>
The technology described in this specification is not limited to the embodiments described above with reference to the drawings, and for example, the following embodiments are also included within the technical scope of the present invention.

(1) The layer structure of the array substrate 21 and the planar layout pattern of each layer are not limited to those shown in the figure. For example, the TFT 23 may be a top-gate type or a dual-gate type TFT.

(2) The technology described in this specification can be applied to display panels other than the liquid crystal panel 11. For example, it can be applied to a display panel in which functional organic molecules (medium layer) other than the liquid crystal layer 22 are sandwiched between two substrates 20 and 21.

10...Liquid crystal display device (display device), 10HMD...Head mounted display, 11...Liquid crystal panel (display panel), 21...Array substrate, 21GS...Glass substrate (insulating substrate), 23...TFT (switching element), 24...Pixel electrode, 25...Common electrode, 32...Second light shielding portion (light shielding portion), 32S...Opening, 32S1...Opening edge portion, 42...Second light shielding film (light shielding film), 42A...Overlapping portion, 44...Second transparent electrode film (transparent electrode film), 45...Protective insulating film (insulating film), 60...First resist pattern, 60A...Extension portion, 61...Second resist pattern, PX...Pixel

Claims (14)

A manufacturing method of an array substrate in which a plurality of pixels are arranged in a matrix, comprising the steps of:
A plurality of switching elements constituting the plurality of pixels are formed on an upper layer side of an insulating substrate;
forming a light-shielding film on an upper layer side of the plurality of switching elements;
forming a first resist pattern on the light-shielding film, the first resist pattern corresponding to a layout pattern of a plurality of light-shielding portions for blocking light passing between adjacent pixels;
The light-shielding film is etched and patterned using the first resist pattern as a mask;
forming a transparent electrode film on an upper layer side of the plurality of light-shielding portions;
forming a second resist pattern on the transparent electrode film, the second resist pattern corresponding to a layout pattern of a common electrode having a plurality of openings and to which a predetermined reference potential is applied;
Etching the transparent electrode film with a first etchant using the second resist pattern as a mask to form the common electrode;
The method for manufacturing an array substrate includes etching the patterned light-shielding film with a second etchant using the common electrode as a mask to remove portions of the patterned light-shielding film that overlap with the plurality of openings. The method for manufacturing an array substrate according to claim 1, wherein the first resist pattern has an extension that overlaps with the multiple openings of the common electrode. The method for manufacturing an array substrate according to claim 1 or 2, wherein the overlapping portion is a protrusion that faces toward the opening in a plan view. The method for manufacturing an array substrate according to claim 1 or 2, wherein the second resist pattern is peeled off after removing the overlapping portion. The method for manufacturing an array substrate according to claim 4, wherein the first etchant is a chemical solution containing oxalic acid as a main component, and the second etchant is a chemical solution containing a mixture of phosphoric acid, nitric acid, and acetic acid. The method for manufacturing an array substrate according to claim 1 or 2, wherein the second resist pattern is peeled off after the transparent electrode film is etched to form the common electrode and before the overlapping portion is removed. The method for manufacturing an array substrate according to claim 6, wherein the first corrosive agent is a chemical solution containing oxalic acid as a main component, and the second corrosive agent is ozone water. The method for manufacturing an array substrate according to claim 7, wherein an insulating film is formed on the common electrode after removing the overlapping portion. forming a plurality of pixel electrodes in a matrix on an upper layer side of the plurality of switching elements, the pixel electrodes being connected to the plurality of switching elements;
3. The method for manufacturing an array substrate according to claim 1, wherein the light-shielding film is formed on an upper layer side of the plurality of pixel electrodes. The method for manufacturing an array substrate according to claim 1 or 2, wherein the array substrate is an array substrate for a display panel used in a head mounted display. The method for manufacturing an array substrate according to claim 10, wherein the display panel is a liquid crystal panel. A plurality of switching elements each constituting a plurality of pixels are provided on an upper layer side of an insulating substrate;
a plurality of pixel electrodes arranged in a matrix on an upper layer side of the plurality of switching elements and connected to the plurality of switching elements;
a plurality of light shielding portions provided on upper layers of the plurality of pixel electrodes for blocking light passing between adjacent pixels;
a common electrode provided on the light-shielding portions, the common electrode having a plurality of openings, and to which a predetermined reference potential is applied;
the plurality of light-shielding portions overlap with the common electrode,
An array substrate, wherein the shortest distance between the outer peripheral edges of the plurality of light-shielding portions and the edges of the plurality of openings is 0.001 μm or more and less than 1 μm in a direction along a main surface of the insulating substrate. A display device for a head mounted display, comprising a display panel having the array substrate according to claim 12. The display device according to claim 13, wherein the display panel is a liquid crystal panel.

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