JP2024025518A - level conversion circuit - Google Patents

Abstract

To provide a level conversion circuit capable of reducing power consumption.SOLUTION: A second transistor control circuit 5 performs ON-control of a transistor MN3 during the output of a first one-shot pulse outputted in response to switching of an input voltage VIN from an L-level to an H-level and performs ON-control of a transistor MP5 while the output of the first one-shot pulse is stopped. A second transistor control circuit 6 performs ON-control of a transistor MN4 during the output of a second one-shot pulse in response to switching of the input voltage VIN from the H-level to the L-level and performs ON-control of a transistor MP6 while the output of the second one-shot pulse is stopped.SELECTED DRAWING: Figure 1

Description

The present invention relates to a level conversion circuit.

FIG. 4 shows a conventional level conversion circuit (for example, see FIG. 1 of Patent Document 1). In the conventional level conversion circuit, when an input voltage having the amplitude of H level (VDD1) and L level (GND) is input to the input terminal IN, the amplitude of H level (VDD2) and L level (VL2=VDD2-VDD3) is changed. This is a circuit that outputs an output voltage from an output terminal OUT. In FIG. 4, MP21 to MP29 are P-channel field effect transistors, MN21 to MN28 are N-channel field effect transistors, R11 to R17 are resistors, AND1 and AND2 are AND circuits, and INV1 to INV7 are inverters.

In the conventional level conversion circuit, when the input voltage and the output voltage are at L level, transistors MP24, MN21, MP29, MN27, and MN28 are turned on, and four resistors R11, R15, R16, and R17 turn on as shown by the arrows. There was a problem in that power consumption was high because the current continued to flow.

JP2020-21978A

The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a level conversion circuit that reduces power consumption.

In order to achieve the above-mentioned object, the level conversion circuit according to the present invention has the following features [1] to [4].
[1]
A level conversion circuit that converts an input voltage having an amplitude of a first high voltage and a first low voltage to an output voltage having an amplitude of a second high voltage and a second low voltage,
a first transistor having a gate or base connected to a first node and a source or emitter connected to a positive electrode of a second power supply supplying the second high voltage;
a second transistor whose gate or base is connected to a second node and whose source or emitter is connected to the positive electrode of the second power supply;
a latch circuit that latches an output depending on the on/off state of the first transistor and the second transistor and outputs a voltage having an amplitude of the second high voltage and the second low voltage;
a third transistor connected between the first node and a negative electrode of a first power source that supplies the first high voltage;
a fourth transistor connected between the second node and the negative electrode of the first power supply;
is provided between the positive electrode of the second power source, the first node, and the second node, and when the third transistor is on and the fourth transistor is off, the first transistor is turned on and the second transistor is turned on. a first transistor control circuit that turns off the first transistor and turns on the second transistor when the third transistor is off and the fourth transistor is on;
a fifth transistor connected between the positive electrode of the second power supply and the first node;
a sixth transistor connected between the positive electrode of the second power source and the second node;
a first one-shot pulse output circuit that outputs a first one-shot pulse in response to a rise of the input voltage from the first low voltage to the first high voltage;
a second one-shot pulse output circuit that outputs a second one-shot pulse in response to a fall of the input voltage from the first high voltage to the first low voltage;
The third transistor is turned on while outputting the first one-shot pulse, the fifth transistor is turned on while outputting the first one-shot pulse is stopped, and the third transistor is turned on while outputting the second one-shot pulse. The level conversion circuit includes a second transistor control circuit that turns on four transistors and turns on the sixth transistor while outputting the second one-shot pulse is stopped.
[2]
In the level conversion circuit described in [1],
The second transistor control circuit includes:
a seventh transistor connected between the positive electrode of the second power supply and the gate or base of the fifth transistor;
a first resistor connected between the seventh transistor and a negative electrode of a third power supply for supplying the second low voltage;
a second resistor connected between the positive electrode of the second power supply and the gate or base of the seventh transistor;
an eighth transistor connected between the second resistor and the negative electrode of the first power source, the gate or base of which is connected to the first one-shot pulse output circuit;
a ninth transistor connected between the positive electrode of the second power source and the gate or base of the sixth transistor;
a third resistor connected between the ninth transistor and the negative electrode of the third power supply;
a fourth resistor connected between the positive electrode of the second power supply and the gate or base of the ninth transistor;
The level conversion circuit includes a tenth transistor connected between the fourth resistor and the negative electrode of the first power source, and having a gate or base connected to the second one-shot pulse output circuit.
[3]
In the level conversion circuit described in [2],
The second transistor control circuit includes:
It has a current source that receives power supply from the first power source and supplies current, and returns the current supplied from the current source or the current according to the current supplied from the current source to the eighth transistor and The level conversion circuit has a current mirror circuit that supplies the current to the tenth transistor.
[4]
In the level conversion circuit according to any one of [1] to [3],
The first transistor control circuit includes:
an eleventh transistor whose source or emitter is connected to the positive electrode of the second power supply and whose drain or collector is connected to the first node and the gate or base;
a twelfth transistor whose source or emitter is connected to the positive electrode of the second power supply, whose gate or base is connected to the gate or base of the eleventh transistor, and whose drain or collector is connected to the second node;
a thirteenth transistor whose source or emitter is connected to the positive electrode of the second power supply and whose drain or collector is connected to the second node and the gate or base;
A level conversion circuit comprising a fourteenth transistor whose source or emitter is connected to the positive electrode of the second power supply, whose gate or base is connected to the gate or base of the thirteenth transistor, and whose drain or collector is connected to the first node. To be.

According to the present invention, it is possible to provide a level conversion circuit with reduced power consumption.

The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading the mode for carrying out the invention (hereinafter referred to as "embodiment") described below with reference to the accompanying drawings. .

FIG. 1 is a circuit diagram showing one embodiment of a level conversion circuit of the present invention. FIG. 2 is a circuit diagram showing details of the first and second one-shot pulse output circuits shown in FIG. 1. FIG. 3 is a time chart of each voltage and current of the level conversion circuit shown in FIG. FIG. 4 is a circuit diagram showing an example of a conventional level conversion circuit.

Specific embodiments of the present invention will be described below with reference to each figure.

FIG. 1 is a circuit diagram showing an embodiment of a level conversion circuit 1 of the present invention. The level conversion circuit 1 converts an input voltage VIN having an amplitude of an H level (VDD1) and an L level (GND) input to an input terminal IN, and converts the amplitude of an H level (VDD2) and an L level (VL2=VDD2-VDD3). This circuit converts the output voltage VOUT into an output voltage VOUT and outputs it from the output terminal OUT. VDD1 is a power supply voltage supplied from the first power supply 21. VDD2 is a power supply voltage supplied from the second power supply 22. VDD3 is a power supply voltage supplied from the third power supply 23, and is provided to supply VL2. For example, GND=0V, VDD1=5V, VDD2=30V, and VDD3=3V. In this embodiment, VDD1 corresponds to the first high voltage, GND corresponds to the first low voltage, VDD2 corresponds to the second high voltage, and VL2 corresponds to the second low voltage.

The level conversion circuit 1 includes transistors MP1 and MP2, a latch circuit 3, an inverter circuit 4, transistors MN3 and MN4, a first transistor control circuit 5, transistors MP5 and MP6, and first and second one-shot pulses. It includes output circuits 71 and 72 and a second transistor control circuit 8.

Transistors MP1 and MP2 as the first and second transistors are constructed from P-channel field effect transistors. The transistor MP1 has a gate connected to a node A serving as a first node, a source connected to the positive electrode of the second power supply 22, and supplied with VDD2. The transistor MP2 has a gate connected to a node B serving as a second node, a source connected to the positive electrode of the second power supply 22, and supplied with VDD2.

The latch circuit 3 is a circuit to which a voltage between VDD2 and VL2 is applied. The latch circuit 3 latches the output depending on the on/off states of the transistors MP1 and MP2, and outputs a voltage having an amplitude of an H level (VDD2) and an L level (VL2) (details will be described later). The latch circuit 3 includes transistors MP15, MP16, MN15, and MN16. Transistors MP15 and MP16 are composed of P-channel field effect transistors, and transistors MN15 and MN16 are composed of N-channel field effect transistors.

The sources of the transistors MP15 and MP16 are connected to the positive electrode of the second power supply 22, and are supplied with VDD2. The sources of the transistors MN15 and MN16 are connected to the negative electrode of the third power supply 23, and are supplied with VL2. Furthermore, the drains of the transistors MP15 and MN15 are connected to each other, and the gates of the transistors are connected to each other. The drains of the transistors MP16 and MN16 are connected to each other, and the gates of the transistors are connected to each other. Further, the drains of transistors MP15 and MN15 are connected to the gates of transistors MP16 and MN16. The drains of transistors MP16 and MN16 are connected to the gates of transistors MP15 and MN15.

The drain of transistor MP1 is connected to the gates of transistors MP15 and MN15 and the drains of transistors MP16 and MN16. The drain of transistor MP2 is connected to the drains of transistors MP15 and MN15 and the gates of transistors MP16 and MN16. The drains of the transistors MP16 and MN16 serve as the output of the latch circuit 3.

According to the above configuration, as shown in Table 1 below, in the latch circuit 3, when transistor MP1 is on and transistor MP2 is off, transistors MP15 and MN16 are turned off, transistors MN15 and MP16 are turned on, and H The level (VDD2) is output. When the transistors MP1 and MP2 are switched off from this state, the transistors MP15 and MN16 are kept off and the transistors MN15 and MP16 are kept on, and the output at H level (VDD2) is kept.

Further, in the latch circuit 3, when the transistor MP1 is off and the transistor MP2 is on, the transistors MP15 and MN16 are on and the transistors MN15 and MP16 are off, and an L level (VL2) is output. When the transistors MP1 and MP2 are switched off from this state, the transistors MP15 and MN16 are kept on and the transistors MN15 and MP16 are kept off, and the output at L level (VL2) is kept.

The inverter circuit 4 inverts the output of the latch circuit 3 twice and outputs it as an output voltage VOUT. The inverter circuit 4 has two inverters 41 and 42. The input of the inverter 41 is connected to the output of the latch circuit 3. The inverter 42 has an input connected to the output of the inverter 41, and an output connected to the output terminal OUT.

The transistors MN3 and MN4 serving as the third and fourth transistors are composed of high voltage N-channel field effect transistors. Transistor MN3 is connected between node A and the negative electrode of first power supply 21. Transistor MN4 is connected between node B and the negative electrode of first power supply 21. To explain in detail, the transistor MN3 has a source connected to the negative electrode of the first power supply 21, and a drain connected to the node A. The transistor MN4 has a source connected to the negative electrode of the first power supply 21, and a drain connected to the node B.

The first transistor control circuit 5 has transistors MP11 to MP14 as the 11th to 14th transistors, each of which is a P-channel field effect transistor. Transistors MP11 and MP12 are connected in a current mirror manner. The transistor MP11 has a source connected to the positive electrode of the second power supply 22, and a gate and a drain connected to each other. The drain of transistor MP11 is connected to node A. The transistor MP12 has a source connected to the positive electrode of the second power supply 22, and a gate connected to the gate and drain of the transistor MP11. The drain of transistor MP12 is connected to node B.

Transistors MP13 and MP14 are connected in a current mirror manner. The transistor MP13 has a source connected to the positive electrode of the second power supply 22, and a gate and a drain connected to each other. The drain of transistor MP13 is connected to node B. The transistor MP14 has a source connected to the positive electrode of the second power supply 22, and a gate connected to the gate and drain of the transistor MP13. The drain of transistor MP14 is connected to node A.

In the first transistor control circuit 5, when the transistor MN3 is on and the transistor MN4 is off, the transistors MP11 and M12 are turned on and the transistors MP13 and MP14 are turned off. As a result, the first transistor control circuit 5 outputs the L level (VDD2-VGSMP11) from the node A and the H level (VDD2) from the node B, turns on the transistor MP1, and turns off the transistor MP2. VGSMP11 is a gate-source voltage of transistor MP11, and is a voltage higher than the threshold voltage of transistor MP1.

Further, in the first transistor control circuit 5, when the transistor MN3 is off and the transistor MN4 is on, the transistors MP11 and M12 are turned off and the transistors MP13 and MP14 are turned on. As a result, the first transistor control circuit 5 outputs an H level (VDD2) from the node A and an L level (VDD2-VGSMP13) from the node B, turns off the transistor MP1, and turns on the transistor MP2. VGSMP13 is a gate-source voltage of transistor MP13, which is a voltage higher than the threshold voltage of transistor MP2.

Transistors MP5 and MP6 as the fifth and sixth transistors are constructed from P-channel field effect transistors. The transistor MP5 has a source connected to the positive electrode of the second power supply 22, and a drain connected to the node A. The transistor MP6 has a source connected to the positive electrode of the second power supply 22, and a drain connected to the node B. When transistors MP5 and MP6 are turned on while transistors MN3 and MN4 are turned off, an H level (VDD2) is forcibly output from nodes A and B.

An input terminal IN is connected to the input of the first one-shot pulse output circuit 71, and an input voltage VIN is input thereto. The first one-shot pulse output circuit 71 is a circuit that outputs a first one-shot pulse in response to the rising of the input voltage VIN from the L level to the H level. The output of the first one-shot pulse output circuit 71 is connected to the gates of a transistor MN3 and a transistor MN8, which will be described later.

The second one-shot pulse output circuit 72 has an input connected to the output of the inverter 9. An input terminal IN is connected to the input of the inverter 9, and an inverted input voltage VIN is input to the input of the second one-shot pulse output circuit 72. The second one-shot pulse output circuit 72 is a circuit that outputs a second one-shot pulse in response to the falling of the input voltage VIN from the H level to the L level. The output of the second one-shot pulse output circuit 72 is connected to the gates of a transistor MN4 and a transistor MN10, which will be described later.

Next, an example of the above-described first and second one-shot pulse output circuits 71 and 72 will be described with reference to FIG. 2. As shown in the figure, the first and second one-shot pulse output circuits 71 and 72 each include an inverter 701, a current source 702, transistors MP20 and MN20, a capacitor C, an inverter 703, and an AND circuit 704. have. The input of the inverter 701 becomes the input of the first and second one-shot pulse output circuits 71 and 72, and the input voltage VIN or the inverted input voltage VIN is supplied thereto. Current source 702 supplies current Iref2. Transistor MP20 is composed of a P-channel field effect transistor. The transistor MN20 is composed of an N-channel field effect transistor.

The gates of the transistors MP20 and MN20 are connected to each other, and the drains thereof are connected to each other. The gates of transistors MP20 and MN20 are connected to the output of inverter 701. The source of transistor MP20 is connected to current source 702, and the source of transistor MN20 is connected to GND. Capacitor C is connected between the drains of transistors MP20 and MN20 and GND. The input of the inverter 703 is connected to the capacitor C and the drains of the transistors MP20 and MN20. The AND circuit 704 has inputs connected to the inputs of the first and second one-shot pulse output circuits 71 and 72 and the output of the inverter 703. The output of the AND circuit 704 becomes the output of the first and second one-shot pulse output circuits 71 and 72.

According to the above, when the input voltage VIN or the inverted input voltage VIN switches from L level (GND) to H level (VDD1), the gates of transistors MP20 and MN20 become L level, transistor MP20 is turned on, and transistor MN20 is turned off. do. As a result, charging of the capacitor C is started by the current Iref2. While capacitor C is not charged and the voltage across it does not exceed the inverter voltage, inverter 703 outputs H level, and AND circuit 704 outputs H level first and second one-shot pulses. be done. On the other hand, when capacitor C is charged and the voltage across it exceeds the inverter voltage, the output of inverter 703 switches to L level, L level is output from AND circuit 704, and the outputs of the first and second one-shot pulses are will be stopped.

After that, when the input voltage VIN or the inverted input voltage VIN switches from the H level to the L level, the gates of the transistors MP20 and MN20 go to the H level, turning off the transistor MP20 and turning on the transistor MN20. As a result, capacitor C is discharged. According to the above configuration, the first and second one-shot pulse output circuits 71 and 72 output the first and second one-shot pulses that are at the H level for a certain period of time according to the current Iref2 and the capacitance of the capacitor C. be able to. Note that the certain time is set to be longer than the time from the timing when the input voltage VIN switches from H level to L level and from L level to H level until the output voltage VOUT switches from H level to L level and from L level to H level. ing.

Returning to FIG. 1, the second transistor control circuit 8 will be explained. The second transistor control circuit 8 turns on the transistor MN3 while outputting the first one-shot pulse, and turns on the transistor MP5 while the output of the first one-shot pulse is stopped. Further, the second transistor control circuit 8 controls the transistor MN4 to turn on while outputting the second one-shot pulse, and controls the transistor MP6 to turn on while the output of the second one-shot pulse is stopped.

The second transistor control circuit 8 includes a transistor MP7, resistors R1 and R2, a high voltage transistor MN8, a transistor MP9, resistors R3 and R4, a high voltage transistor MN10, and a current mirror circuit 81. There is. Transistors MP7 and MP9 are composed of P-channel field effect transistors. Transistors MN8 and MN10 are composed of N-channel field effect transistors.

The transistor MP7 serving as the seventh transistor has a source connected to the positive electrode of the second power supply 22, and a drain connected to the gate of the transistor MP5. A resistor R1 serving as a first resistor is connected between the drain of the transistor MP7 and the negative electrode of the third power supply 23. A resistor R2 serving as a second resistor is connected between the positive electrode of the second power supply 22 and the gate of the transistor MP7. The transistor MN8 serving as the eighth transistor is connected between the resistor R2 and the negative electrode of the first power supply 21, and has its gate connected to the output of the first one-shot pulse output circuit 71.

The transistor MP9 serving as the ninth transistor has a source connected to the positive electrode of the second power supply 22, and a drain connected to the gate of the transistor MP6. A resistor R3 serving as a third resistor is connected between the drain of the transistor MP9 and the negative electrode of the third power supply 23. A resistor R4 serving as a fourth resistor is connected between the positive electrode of the second power supply 22 and the gate of the transistor MP9. The transistor MN10 as the tenth transistor is connected between the resistor R4 and the negative electrode of the first power supply 21, and has its gate connected to the output of the second one-shot pulse output circuit 72.

The current mirror circuit 81 folds the current Iref from the current source 82 into two and supplies them to the transistors MN8 and MN10, respectively. Current mirror circuit 81 includes a current source 82 and transistors MN17 to MN19.

The current source 82 has one end connected to the positive electrode of the first power supply 21 and supplies a current Iref. Transistors MN17 to MN19 are composed of N-channel field effect transistors. The transistor MN17 has a drain connected to the current source 82, a source connected to the negative electrode of the first power supply 21, and a gate and a drain connected. The transistors MN18 and MN19 have gates connected to the gate and drain of the transistor MN17, and sources connected to the negative electrode of the first power supply 21. The drain of transistor MN18 is connected to the source of transistor MN8. The drain of transistor MN19 is connected to the source of transistor MN10.

According to the above configuration, the transistors MN3 and MN8 are turned on while the first one-shot pulse is being output. When transistor MN8 is turned on, current Iref from current mirror circuit 81 flows through resistor R2. When current Iref flows through resistor R2, transistor MP7 is turned on and transistor MP5 can be turned off. While the output of the first one-shot pulse is stopped, the transistors MN3 and MN8 are turned off. When transistor MN8 is turned off, current to resistor R2 is cut off. When the current to resistor R2 is cut off, transistor MP7 can be turned off and transistor MP5 can be turned on.

Furthermore, while the second one-shot pulse is being output, the transistors MN4 and MN10 are turned on. When the transistor MN10 is turned on, a current Iref from the current mirror circuit 81 flows through the resistor R4. When current Iref flows through resistor R4, transistor MP9 is turned on and transistor MP6 can be turned off. While the output of the second one-shot pulse is stopped, the transistors MN4 and MN10 are turned off. When transistor MN10 is turned off, current to resistor R4 is cut off. When the current to resistor R4 is cut off, transistor MP9 can be turned off and transistor MP6 can be turned on.

Next, the operation of the level conversion circuit 1 having the above-described configuration will be explained with reference to the time chart of FIG. 3. First, a case where the input voltage VIN switches from L level (GND) to H level (VDD1) will be described. When the input voltage VIN switches from the L level to the H level, the first one-shot pulse output circuit 71 outputs the first one-shot pulse to the gates of the transistors MN3 and MN8. When the first one-shot pulse is output, the transistor MN3 is turned on and the transistor MP5 is turned off. At this time, the transistor MN4 is off and the transistor MP6 is on.

As described above, when the transistor MN3 is turned on and the transistor MN4 is turned off, the transistors MP11 and MP12 are turned on and the transistors MP13 and MP14 are turned off. Therefore, (VDD2-VGSMP11) is output from node A and VDD2 is output from node B, turning on transistor MP1 and turning off transistor MP2. When transistor MP1 is turned on and transistor MP2 is turned off, as shown in Table 1, the latch circuit 3 outputs an H level (VDD2), and the output voltage VOUT becomes H level (VDD2).

Next, when a certain period of time has elapsed after the input voltage VIN switched from the L level to the H level, the output of the first one-shot pulse from the first one-shot pulse output circuit 71 to the gates of the transistors MN3 and MN8 is stopped. Ru. When the output of the first one-shot pulse is stopped, the transistor MN3 is turned off and the transistor MP5 is turned on. At this time, the transistor MN4 remains off and the transistor MP6 remains on.

As described above, when transistors MN3 and MN4 are turned off, transistors MP11 to MP14 are turned off, but since transistors MP5 and MP6 are turned on, VDD2 is output from nodes A and B. As a result, transistors MP1 and MP2 are turned off, and as shown in Table 1, the output from the latch circuit 3 is held at the H level, and the output voltage VOUT is held at the H level.

Next, a case where the input voltage VIN is switched from the H level (VDD1) to the L level (GND) will be described. When the input voltage VIN switches from the H level to the L level, a second one-shot pulse is output from the second one-shot pulse output circuit 72 to the gates of the transistors MN4 and MN10. When the second one-shot pulse is output, the transistor MN4 is turned on and the transistor MP6 is turned off. At this time, the transistor MN3 is off and the transistor MP5 is on.

As described above, when the transistor MN4 is turned on and the transistor MN3 is turned off, the transistors MP13 and MP14 are turned on and the transistors MP11 and MP12 are turned off. Therefore, VDD2 is output from node A and (VDD2-VGSMP13) is output from node B, transistor MP1 is turned off and transistor MP2 is turned on. When the transistor MP1 is turned off and the transistor MP2 is turned on, the latch circuit 3 outputs the L level (VL2) and the output voltage VOUT becomes the L level (VL2), as shown in Table 1.

Next, when a certain period of time has elapsed after the input voltage VIN switched from the H level to the L level, the output of the second one-shot pulse from the second one-shot pulse output circuit 72 to the gates of the transistors MN4 and MN10 is stopped. Ru. When the output of the second one-shot pulse is stopped, the transistor MN4 is turned off and the transistor MP6 is turned on. At this time, the transistor MN3 remains off and the transistor MP5 remains on.

As described above, when transistors MN3 and MN4 are turned off, transistors MP11 to MP14 are turned off, but since transistors MP5 and MP6 are turned on, VDD2 is output from nodes A and B. As a result, transistors MP1 and MP2 are turned off, and as shown in Table 1, the output from the latch circuit 3 is held at the L level, and the output voltage VOUT is held at the L level.

According to the embodiment described above, the nodes A and B are connected only for a certain period of time when the input voltage VIN switches from H level to L level and from L level to H level, and the first one-shot pulse and the second one-shot pulse are output. A current I1 flows through the transistors MN8 and MN10, and a current Iref flows through the transistors MN8 and MN10. When the output of the first one-shot pulse and the second one-shot pulse is stopped, the current flows through the nodes A and B and the current flows through the transistors MN8 and MN10. is blocked. This makes it possible to save power.

Further, the lowest operating voltage of VDD3 is expressed by the following formula (1), and low voltage operation is possible like the conventional level conversion circuit.
VDD3>VGSMP16+VGSMN16...(1)
VGSMP16: Gate-source voltage of transistor MP16 VGSMN16: Gate-source voltage of transistor MN16

Further, according to the embodiment described above, the second transistor control circuit 8 includes transistors MP7, MN8, MP9, MP10, and resistors R1 to R4. Thereby, it is possible to control on/off of the transistors MN3, MN4, MP5, and MP6 with a simple configuration and power saving.

According to the embodiment described above, the second transistor control circuit 8 includes the current mirror circuit 81. Thereby, the current flowing through the transistors MN8 and MN10 can be suppressed to a current Iref lower than the current I1, and power saving can be achieved.

Further, according to the embodiment described above, the first transistor control circuit 5 is composed of transistors MP11 to MP14. This makes it possible to control on/off of the transistors MP1 and MP2 with a simple configuration.

Note that the present invention is not limited to the embodiments described above, and can be modified, improved, etc. as appropriate. In addition, the material, shape, size, number, arrangement location, etc. of each component in the above-described embodiments are arbitrary as long as the present invention can be achieved, and are not limited.

According to the embodiment described above, the current Iref is folded back in the current mirror circuit 81. The current that is turned back only needs to be a current that corresponds to the current Iref, and does not need to be equal to the current Iref.

According to the embodiment described above, the first transistor control circuit 5 is composed of the transistors MP11 to MP14, but the present invention is not limited to this. For example, it may be composed of a resistor and a Zener diode provided between the positive electrode of the second power supply 22 and the nodes A and B, respectively. The resistor and Zener diode are connected in parallel. In this case, the outputs of nodes A and B are switched between VDD2 and VDD2-VDZ in response to supply and cutoff of current to nodes A and B. VDZ is the Zener voltage of the Zener diode.

According to the embodiment described above, the transistors MP1, MP2, MN3, MN4, MP5 to MP7, MN8, MP9, MN10, MP11 to MP16, MN15 to MN19, MP20, and MN20 were configured from field effect transistors. It is not limited to this. Transistors MP1, MP2, MN3, MN4, MP5 to MP7, MN8, MP9, MN10, MP11 to MP16, MN15 to MN19, MP20, and MN20 may be composed of bipolar transistors. In this case, the "gate" of the transistor can be replaced with "base," the "source" with "emitter," and the "drain" with "collector."

According to the embodiment described above, the current mirror circuit 81 is provided, but the present invention is not limited to this. The current mirror circuit 81 is not essential and may be omitted.

1 Level conversion circuit 3 Latch circuit 5 First transistor control circuit 8 Second transistor control circuit 21 First power supply 22 Second power supply 23 Third power supply 71 First one-shot pulse output circuit 72 Second one-shot pulse output circuit 81 Current mirror Circuit 82 Current source A node (first node)
B node (second node)
MP1 transistor (first transistor)
MP2 transistor (second transistor)
MN3 transistor (third transistor)
MN4 transistor (4th transistor)
MP5 transistor (fifth transistor)
MP6 transistor (6th transistor)
MP7 transistor (7th transistor)
MN8 transistor (8th transistor)
MP9 transistor (9th transistor)
MN10 transistor (10th transistor)
MP11 transistor (11th transistor)
MP12 transistor (12th transistor)
MP13 transistor (13th transistor)
MP14 transistor (14th transistor)
R1 resistance (first resistance)
R2 resistance (second resistance)
R3 resistance (third resistance)
R4 resistance (4th resistance)
VIN Input voltage VOUT Output voltage

Claims (4)

A level conversion circuit that converts an input voltage having an amplitude of a first high voltage and a first low voltage to an output voltage having an amplitude of a second high voltage and a second low voltage,
a first transistor having a gate or base connected to a first node and a source or emitter connected to a positive electrode of a second power supply supplying the second high voltage;
a second transistor whose gate or base is connected to a second node and whose source or emitter is connected to the positive electrode of the second power supply;
a latch circuit that latches an output depending on the on/off state of the first transistor and the second transistor and outputs a voltage having an amplitude of the second high voltage and the second low voltage;
a third transistor connected between the first node and a negative electrode of a first power source that supplies the first high voltage;
a fourth transistor connected between the second node and the negative electrode of the first power supply;
is provided between the positive electrode of the second power source, the first node, and the second node, and when the third transistor is on and the fourth transistor is off, the first transistor is turned on and the second transistor is turned on. a first transistor control circuit that turns off the first transistor and turns on the second transistor when the third transistor is off and the fourth transistor is on;
a fifth transistor connected between the positive electrode of the second power source and the first node;
a sixth transistor connected between the positive electrode of the second power source and the second node;
a first one-shot pulse output circuit that outputs a first one-shot pulse in response to a rise of the input voltage from the first low voltage to the first high voltage;
a second one-shot pulse output circuit that outputs a second one-shot pulse in response to a fall of the input voltage from the first high voltage to the first low voltage;
The third transistor is turned on while outputting the first one-shot pulse, the fifth transistor is turned on while outputting the first one-shot pulse is stopped, and the third transistor is turned on while outputting the second one-shot pulse. A level conversion circuit comprising: a second transistor control circuit that turns on four transistors and turns on the sixth transistor while outputting the second one-shot pulse is stopped. The level conversion circuit according to claim 1,
The second transistor control circuit includes:
a seventh transistor connected between the positive electrode of the second power supply and the gate or base of the fifth transistor;
a first resistor connected between the seventh transistor and a negative electrode of a third power supply for supplying the second low voltage;
a second resistor connected between the positive electrode of the second power supply and the gate or base of the seventh transistor;
an eighth transistor connected between the second resistor and the negative electrode of the first power source, the gate or base of which is connected to the first one-shot pulse output circuit;
a ninth transistor connected between the positive electrode of the second power source and the gate or base of the sixth transistor;
a third resistor connected between the ninth transistor and the negative electrode of the third power supply;
a fourth resistor connected between the positive electrode of the second power supply and the gate or base of the ninth transistor;
A level conversion circuit comprising: a tenth transistor connected between the fourth resistor and the negative electrode of the first power source, and having a gate or base connected to the second one-shot pulse output circuit. The level conversion circuit according to claim 2,
The second transistor control circuit includes:
It has a current source that receives power supply from the first power source and supplies current, and returns the current supplied from the current source or the current according to the current supplied from the current source to the eighth transistor and A level conversion circuit comprising a current mirror circuit that supplies the tenth transistor. The level conversion circuit according to any one of claims 1 to 3,
The first transistor control circuit includes:
an eleventh transistor whose source or emitter is connected to the positive electrode of the second power supply and whose drain or collector is connected to the first node and the gate or base;
a twelfth transistor whose source or emitter is connected to the positive electrode of the second power supply, whose gate or base is connected to the gate or base of the eleventh transistor, and whose drain or collector is connected to the second node;
a thirteenth transistor whose source or emitter is connected to the positive electrode of the second power supply and whose drain or collector is connected to the second node and the gate or base;
A level conversion circuit comprising a fourteenth transistor whose source or emitter is connected to the positive electrode of the second power supply, whose gate or base is connected to the gate or base of the thirteenth transistor, and whose drain or collector is connected to the first node. .

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