JP2023085417A - switch device - Google Patents

Abstract

To precisely detect an output current.SOLUTION: A switch device includes: a first switch connected between a first node and a second node; a second switch whose first end is connected to the first node, and turned on/off with a drive signal common to the first switch; an output current detection part for generating a sense current according to an output current flowing through the first switch by virtually shorting a second end of the second switch and the second node; a voltage across both ends limit part for limiting the voltage across both ends of the first switch at or above a predetermined lower limit value; and a driver for generating a drive signal. An output stage of the driver includes: a source current source for flowing a source current into a driving signal applying edge; and a sink current source for drawing a sink current from the driving signal applying edge. The voltage across both ends limit part controls the source current source and the sink current source according to a comparison result between the output voltage of the second node and a predetermined threshold voltage.SELECTED DRAWING: Figure 5

Description

The invention disclosed in this specification relates to a switching device.

The applicant of the present application has previously proposed many new technologies regarding switch devices such as in-vehicle IPDs (intelligent power devices) (see Patent Document 1, for example).

WO2017/187785

However, there is room for further study on the detection accuracy of the output current in the switch device.

SUMMARY OF THE INVENTION The invention disclosed in the present specification aims to provide a switch device capable of accurately detecting an output current in view of the above-described problem found by the inventors of the present application.

A switch device disclosed in this specification includes a first switch connected between a first node and a second node, and a first switch having a first end connected to the first node. A sense current corresponding to the output current flowing through the first switch is generated by imaginarily shorting a second switch that is turned on/off by a common drive signal and the second terminal of the second switch and the second node. and a voltage limiter for limiting the voltage across the first switch to a predetermined lower limit value or higher (first configuration).

The switch device having the first configuration may be configured to further include a driver for generating the drive signal (second configuration).

Further, in the switch device having the second configuration, the voltage limiter between both terminals controls the driver in accordance with a result of comparison between the output voltage of the second node and a predetermined threshold voltage (a third configuration). configuration).

In the switch device having the above third configuration, the output stage of the driver includes a source current source for supplying a source current to the application terminal of the drive signal and a sink current source for drawing a sink current from the application terminal for the drive signal. and the voltage limiter between both ends may be configured to perform on/off control and current value control of the source current and the sink current (fourth configuration).

In the switch device having the fourth configuration, the source current sources include a first source current source that generates a first source current and a second source current source that generates a second source current that is smaller than the first source current. a sourcing current source, wherein the sinking current source comprises a first sinking current source that produces a first sinking current; and a second sinking current that is smaller than the first sinking current and larger than the second sourcing current. two sink current sources, wherein during an ON period of the first switch, when the output voltage is lower than a first threshold voltage, the first source current source and the second source current source are turned on to turn on the first source current source; When the sink current source and the second sink current source are turned off, and the output voltage is higher than the first threshold voltage and lower than the second threshold voltage, the second source current source is turned on to generate the first source current. and the second sink current source and the second sink current source are turned off, and the second source current source and the second sink current source are turned on when the output voltage is higher than the second threshold voltage. While the first source current source and the first sink current source are turned off, the first sink current source is turned on to generate the first source current source and the second source current during the off period of the first switch. A configuration (fifth configuration) in which the source and the second sink current source are turned off is preferable.

In the switch device having any one of the second to fifth configurations, the voltage limiter between both terminals drives the driver according to a comparison result between the output voltage of the second node and a predetermined threshold voltage. A configuration (sixth configuration) in which the voltage is switched may be employed.

Further, in the switch device having any one of the first to sixth configurations described above, the inter-terminal voltage limiter operates the first switch according to a comparison result between the output voltage of the second node and a predetermined threshold voltage. A configuration (seventh configuration) in which a transistor used as a is selected may be employed.

Further, the electronic equipment disclosed in this specification includes a switch device having any one of the first to seventh configurations, and a load connected to the switch device (eighth configuration). It is said that

In the electronic device having the eighth configuration, the load may be a bulb lamp, a relay coil, a solenoid, a light-emitting diode, or a motor (ninth configuration).

Further, the vehicle disclosed in this specification has a configuration (tenth configuration) having the electronic device having the above eighth or ninth configuration.

According to the invention disclosed in this specification, it is possible to provide a switch device capable of detecting an output current with high accuracy.

Block diagram showing the overall configuration of a semiconductor integrated circuit device Block diagram showing one configuration example of the signal output section Block diagram showing one configuration example of the gate control section Block diagram showing a configuration example of the output current detector FIG. 4 shows a first embodiment of a Vds limiter; A diagram showing an operation example of the Vds limiter FIG. 10 is a diagram showing a second embodiment of the Vds limiter; The figure which shows 3rd Embodiment of a Vds limiting part External view showing one configuration example of a vehicle

<Semiconductor integrated circuit device (overall configuration)>
FIG. 1 is a block diagram showing the overall configuration of a semiconductor integrated circuit device. The semiconductor integrated circuit device 1 of the present embodiment is an in-vehicle high-side switch IC (=in-vehicle A type of IPD).

The semiconductor integrated circuit device 1 has external terminals T1 to T4 as means for establishing electrical connection with the outside of the device. The external terminal T1 is a power supply terminal (VBB pin) for receiving supply of a power supply voltage VBB (12 V, for example) from a battery (not shown). The external terminal T2 is a load connection terminal or an output terminal (OUT pin) for externally connecting a load 3 (bulb lamp, relay coil, solenoid, light emitting diode, motor, etc.). The external terminal T3 is a signal input terminal (IN pin) for receiving external input of the external control signal Si from the ECU 2 . The external terminal T4 is a signal output terminal (SENSE pin) for externally outputting the state notification signal So to the ECU2. An external sense resistor 4 is externally attached between the external terminal T4 and the ground terminal.

The semiconductor integrated circuit device 1 also includes an NMOSFET 10, an output current monitoring unit 20, a gate control unit 30, a control logic unit 40, a signal input unit 50, an internal power supply unit 60, an abnormality protection unit 70, and an output It is formed by integrating a current detection section 80 and a signal output section 90 .

The NMOSFET 10 is a high withstand voltage (for example, 42 V withstand voltage) power transistor having a drain connected to the external terminal T1 and a source connected to the external terminal T2. The NMOSFET 10 connected in this way functions as a switch element (high side switch) for conducting/interrupting a current path from the terminal to which the power supply voltage VBB is applied to the ground terminal via the load 3 . The NMOSFET 10 turns on when the gate drive signal G1 is at high level, and turns off when the gate drive signal G1 is at low level.

The NMOSFET 10 may be designed to have an on-resistance value of several tens of mΩ when fully on. However, the lower the on-resistance of the NMOSFET 10, the more likely overcurrent will flow when the external terminal T2 is grounded (=when the output is shorted to a grounded terminal or a similar low potential terminal), resulting in abnormal heat generation. Therefore, the lower the on-resistance of the NMOSFET 10, the more important the overcurrent protection circuit 71 and temperature protection circuit 73, which will be described later.

The output current monitoring unit 20 includes NMOSFETs 21 and 21 ′ and a sense resistor 22 and generates a sense voltage Vs (=sense signal) according to the output current Io flowing through the NMOSFET 10 .

NMOSFETs 21 and 21' are both mirror transistors connected in parallel with NMOSFET 10, and generate sense currents Is and Is' according to the output current Io. The size ratio between NMOSFET 10 and NMOSFETs 21 and 21' is m:1 (where m>1). Therefore, the sense currents Is and Is' have the magnitude of the output current Io reduced by 1/m. As with the NMOSFET 10, the NMOSFETs 21 and 21' are turned on when the gate drive signal G1 is at high level and turned off when the gate voltage G2 is at low level.

The sense resistor 22 (resistance value: Rs) is connected between the source of the NMOSFET 21 and the external terminal T2, and the sense voltage Vs (=Is×Rs+Vo) corresponding to the sense current Is, where Vo is applied to the external terminal T2. It is a current-to-voltage conversion element that produces an output voltage appearing.

The gate control unit 30 performs on/off control of the NMOSFETs 10 and 21 by generating a gate drive signal G1 obtained by increasing the current capability of the gate control signal S1 and outputting it to the gates of the NMOSFETs 10 and 21, respectively. The gate control section 30 has a function of controlling the NMOSFETs 10 and 21 so as to limit the output current Io according to the overcurrent protection signal S71.

The control logic unit 40 receives the internal power supply voltage Vreg and generates the gate control signal S1. For example, when the external control signal Si is at a high level (=the logic level for turning on the NMOSFET 10), the internal power supply voltage Vreg is supplied from the internal power supply section 60, so that the control logic section 40 is in an operating state to control the gate. The signal S1 becomes high level (=Vreg). On the other hand, when the external control signal Si is at a low level (=the logic level for turning off the NMOSFET 10), the internal power supply voltage Vreg is not supplied from the internal power supply section 60, so the control logic section 40 is in a non-operating state, and gate control is performed. The signal S1 becomes low level (=GND). In addition, the control logic unit 40 monitors various abnormal protection signals (overcurrent protection signal S71, open protection signal S72, temperature protection signal S73, and undervoltage protection signal S74). The control logic unit 40 also has a function of generating the output switching signal S2 according to the monitoring results of the overcurrent protection signal S71, the open protection signal S72, and the temperature protection signal S73 among the above-described abnormality protection signals. there is

The signal input unit 50 is a Schmitt trigger that receives the input of the external control signal Si from the external terminal T3 and transmits it to the control logic unit 40 and the internal power supply unit 60 . For example, the external control signal Si becomes high level when the NMOSFET 10 is turned on, and becomes low level when the NMOSFET 10 is turned off.

The internal power supply section 60 generates a predetermined internal power supply voltage Vreg from the power supply voltage VBB and supplies it to each section of the semiconductor integrated circuit device 1 . Whether or not the internal power supply unit 60 can operate is controlled according to the external control signal Si. More specifically, the internal power supply section 60 becomes active when the external control signal Si is at high level, and becomes non-operating when the external control signal Si is at low level.

The abnormality protection unit 70 is a circuit block for detecting various abnormalities of the semiconductor integrated circuit device 1, and includes an overcurrent protection circuit 71, an open protection circuit 72, a temperature protection circuit 73, and a low voltage protection circuit 74. .

The overcurrent protection circuit 71 generates an overcurrent protection signal S71 according to the monitoring result of the sense voltage Vs (=whether or not an overcurrent abnormality has occurred in the output current Io). For example, the overcurrent protection signal S71 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The open protection circuit 72 generates an open protection signal S72 according to the monitoring result of the output voltage Vo (=whether or not the load 3 has an open abnormality). For example, the open protection signal S72 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The temperature protection circuit 73 includes a temperature detection element (not shown) that detects abnormal heat generation in the semiconductor integrated circuit device 1 (especially around the NMOSFET 10), and detects the temperature according to the detection result (=whether abnormal heat generation occurs). Generate a protection signal S73. For example, the temperature protection signal S73 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The voltage reduction protection circuit 74 generates a voltage reduction protection signal S74 according to the monitoring result of the power supply voltage VBB or the internal power supply voltage Vreg (=whether or not a voltage reduction abnormality has occurred). For example, the low voltage protection signal S74 becomes low level when an abnormality is not detected, and becomes high level when an abnormality is detected.

The output current detection unit 80 generates a sense current Is' (=Io/m) corresponding to the output current Io by matching the source voltage of the NMOSFET 21' with the output voltage Vo using bias means (not shown). output to the signal output unit 90.

The signal output unit 90 outputs one of the sense current Is′ (=corresponding to the detection result of the output current Io) and the fixed voltage V90 (=corresponding to an abnormality flag, not explicitly shown in the figure) to an external device based on the output selection signal S2. It is selectively output to the terminal T4. When the sense current Is' is selectively output, the output detection voltage V80 (=Is' ×R4) is transmitted to the ECU 2. The output detection voltage V80 increases as the output current Io increases, and decreases as the output current Io decreases. On the other hand, when the fixed voltage V90 is selectively output, the fixed voltage V90 is transmitted to the ECU 2 as the state notification signal So.

<Signal output part>
FIG. 2 is a block diagram showing a configuration example of the signal output section 90. As shown in FIG. The signal output unit 90 of this configuration example includes a selector 91 . The selector 91 selectively outputs the sense current Is' to the external terminal T4 when the output selection signal S2 is at the logic level (for example, low level) when an abnormality is not detected, and the output selection signal S2 is at the logic level when an abnormality is detected. (for example, high level), the fixed voltage V90 is selectively output to the external terminal T4. Note that the fixed voltage V90 is set to a voltage value higher than the upper limit value of the output detection voltage V80 described above.

According to such a signal output unit 90, both the detection result of the output current Io and the abnormality flag can be transmitted to the ECU 2 using a single state notification signal So, which contributes to a reduction in the number of external terminals. becomes possible. When reading the current value of the output current Io from the state notification signal So, the state notification signal So may be A/D [analog-to-digital] converted. On the other hand, when reading the abnormality flag from the state notification signal So, the logic level of the state notification signal So may be determined using a threshold value slightly lower than the fixed voltage V90.

<Gate control part>
FIG. 3 is a block diagram showing a configuration example of the gate control unit 30. As shown in FIG. The gate control unit 30 of this configuration example includes a gate driver 31, an oscillator 32, a charge pump 33, a clamper 34, an NMOSFET 35, a resistor 36 (resistance value: R36), and a capacitor 37 (capacitance value: C37). , Zener diode 38 .

The gate driver 31 is connected between the output end of the charge pump 33 (=the end to which the boosted voltage VG is applied) and the external terminal T2 (=the end to which the output voltage Vo is applied), and controls the current capability of the gate control signal S1. A raised gate drive signal G1 is generated. The gate drive signal G1 becomes high level (=VG) when the gate control signal S1 is high level, and becomes low level (=Vo) when the gate control signal S1 is low level.

The oscillator 32 generates a clock signal CLK having a predetermined frequency and outputs it to the charge pump 33 . Whether or not the oscillator 32 can operate is controlled according to an enable signal Sa from the control logic unit 40 .

The charge pump 33 is an example of a booster that generates a boosted voltage VG higher than the power supply voltage VBB by driving a flying capacitor using the clock signal CLK and supplies the boosted voltage VG to the gate driver 31 . Whether or not the charge pump 33 operates is controlled according to the enable signal Sb from the control logic unit 40 .

The clamper 34 is connected between the external terminal T<b>1 (=application terminal of the power supply voltage VBB) and the gate of the NMOSFET 10 . In an application in which an inductive load 3 is connected to the external terminal T2, when the NMOSFET 10 is switched from on to off, the back electromotive force of the load 3 causes the output voltage Vo to become a negative voltage (<GND). Therefore, a clamper 34 (so-called active clamp circuit) is provided for energy absorption.

The drain of NMOSFET 35 is connected to the gate of NMOSFET 10 . The source of NMOSFET 35 is connected to external terminal T2. The gate of the NMOSFET 35 is connected to the application end of the overcurrent protection signal S71. A resistor 36 and a capacitor 37 are connected in series between the drain and gate of the NMOSFET 35 .

The cathode of Zener diode 38 is connected to the gate of NMOSFET 10 . The anode of Zener diode 38 is connected to the source of NMOSFET 10 . The Zener diode 38 connected in this manner functions as a clamping element that limits the gate-source voltage (=VG-Vo) of the NMOSFET 10 to a predetermined value or less.

In the gate control unit 30 of this configuration example, when the overcurrent protection signal S71 is raised to a high level, the gate drive signal G1 changes from a steady high level (=VG) to a predetermined time constant τ (=R36×C37). is lowered by As a result, the conductivity of the NMOSFET 10 gradually decreases, so that the output current Io is limited. On the other hand, when the overcurrent protection signal S71 is lowered to a low level, the gate drive signal G1 is raised with a predetermined time constant τ. As a result, the conductivity of the NMOSFET 10 gradually increases, so that the restriction on the output current Io is lifted.

Thus, the gate control section 30 of this configuration example has a function of controlling the gate drive signal G1 so as to limit the output current Io according to the overcurrent protection signal S71.

<Output current detector>
FIG. 4 is a diagram showing a configuration example of the output current detection section 80. As shown in FIG. The output current detection unit 80 of this configuration example includes an operational amplifier 81 and a PMOSFET 82 . The non-inverting input terminal (+) of the operational amplifier 81 is connected to the source of the NMOSFET 10 and the external terminal T2 (=the terminal to which the output voltage Vo is applied). The inverting input terminal (-) of the operational amplifier 81 and the source of the PMOSFET 82 are connected to the source of the NMOSFET 21'. An output terminal of the operational amplifier 81 is connected to the gate of the PMOSFET 82 . The drain of PMOSFET 82 is connected to external terminal T4. Note that the previously described signal output section 90 (FIG. 1) may be inserted between the drain of the PMOSFET 82 and the external terminal T4.

The operational amplifier 81 controls the gate of the PMOSFET 82 so as to imaginarily short the source of the NMOSFET 21' and the external terminal T2. Therefore, if the operational amplifier 81 is an ideal amplifier that does not have the offset voltage Vofs, the source voltage of the NMOSFET 21′ and the output voltage Vo will match, and the voltage between the drain and the source of the NMOSFET 21′ will become the voltage between the drain and the source of the NMOSFET 10. Vds. As a result, a sense current Is' (=Io/m) proportional to the output current Io flows through the NMOSFET 21'.

However, in reality, since the operational amplifier 81 has an offset voltage Vofs, the sense current Is' fluctuates under the influence of the offset voltage Vofs. In particular, when the output current Io is small, the drain-source voltage Vds (=Io×Ron) of the NMOSFET 10 (on-resistance value: Ron) is low. (=the generation accuracy of the sense current Is') decreases. For example, between a bulb lamp and a light emitting diode, since the output current Io flowing through the latter is smaller, the voltage Vds between the drain and the source of the NMOSFET 10 is low, and it can be said that it is easily affected by the offset voltage Vofs.

In order to solve such a problem, a Vds limiter (corresponding to a voltage limiter between both ends) is provided to limit the voltage Vds between the drain and source of the NMOSFET 10 to a predetermined lower limit value or more so that the drain-source voltage Vds does not drop too much. It is desirable to have

<Vds Limiter (First Embodiment)>
FIG. 5 is a diagram showing a first embodiment of the Vds limiter. The Vds limiter 100 of this embodiment includes comparators 101 and 102 , resistors 103 and 104 , and a current source 105 .

The comparator 101 compares the output voltage Vo input to the non-inverting input terminal (+) and the threshold voltage VBB-VdsA input to the inverting input terminal (-) to generate a comparison signal SA. The comparison signal SA becomes high level when Vo>VBB-VdsA, and becomes low level when Vo<VBB-VdsA. In other words, the comparison signal SA becomes high level when Vds<VdsA (eg, 30 mA), and becomes low level when Vds>VdsA.

The comparator 102 compares the output voltage Vo input to the non-inverting input terminal (+) and the threshold voltage VBB-VdsB input to the inverting input terminal (-) to generate a comparison signal SB. The comparison signal SB becomes high level when Vo>VBB-VdsB, and becomes low level when Vo<VBB-VdsB. In other words, the comparison signal SB becomes high level when Vds<VdsB (for example, 100 mA), and becomes low level when Vds>VdsB.

The resistors 103 and 104 and the current source 105 are connected in series between the external terminal T1 (=applying terminal of the power supply voltage VBB) and the applying terminal of the internal reference voltage VREF in the order shown. A connection node between the resistors 103 and 104 corresponds to the output end of the threshold voltage VBB-VdsA. A connection node between the resistor 104 and the current source 105 corresponds to the output end of the threshold voltage VBB-VdsB.

The Vds limiter 100 configured as described above controls the gate driver 31 using the comparison signals SA and SB. The gate driver 31 includes a source current source 311 and a sink current source 312 that form its output stage, and a controller 313 that controls them.

The source current source 311 is a circuit section for injecting a source current IH into the application terminal of the gate drive signal G1, and is connected in parallel between the application terminal of the boosted voltage VG and the application terminal of the gate drive signal G1. Includes sources 311a and 311b. The source current source 311a generates a source current IH1 (60-70 μA, for example). On the other hand, the source current source 311b generates a source current IH2 (eg, 3 μA) that is smaller than the source current IH1.

The sink current source 312 is a circuit unit for drawing the sink current IL from the application terminal of the gate drive signal G1, and is provided between the application terminal of the gate drive signal G1 and the external terminal T2 (=the application terminal of the output voltage Vo). It includes sink current sources 312a and 312b connected in parallel. The sink current source 312a generates a sink current IL1 (eg, 60-70 μA). On the other hand, the sink current source 312b generates a sink current IL2 (eg, 6 μA) that is smaller than the sink current IL1 and larger than the source current IH2.

The controller 313 controls the source current source 311 and the sink current source 312 according to the gate control signal S1 and the comparison signals SA and SB, thereby performing on/off control and current value control of the source current IH and the sink current IL, respectively. I do. Although the controller 313 is depicted as a part of the gate driver 31 in this figure, it can also be understood as a part of the Vds limiter 100 in view of its function.

FIG. 6 is a diagram showing an operation example of the Vds limiter 100 (or the controller 313). From top to bottom, the external control signal Si, the output voltage Vo, the comparison signals SA and SB, and the on/off states of the source currents IH1 and IH2. An off state and an on/off state of sink currents IL1 and IL2 are depicted. This figure shows the behavior when a load 3 (such as a light-emitting diode) that does not require a large output current Io is connected.

At time t1, the external control signal Si rises to a high level (=logic level for turning on the NMOSFET 10), and at time t2, the semiconductor integrated circuit device 1 becomes operable (=UVLO release state). At this time, the output voltage Vo has not yet risen, so Vo<VBB-VdsB (that is, Vds>VdsB). Therefore, SA=SB=L.

At this time, the controller 313 turns on the source current sources 311a and 311b and turns off the sink current sources 312a and 312b. As a result, the gate drive signal G1 rises sharply by the source current IH (=IH1+IH2) that is the sum of the source currents IH1 and IH2, so the output voltage Vo also starts to rise steeply.

When the output voltage Vo continues to rise and Vo>VBB-VdsB (that is, Vds<VdsB) at time t3, SB=H. At this time, the controller 313 turns off the source current source 311a. As a result, the source current IH for raising the gate drive signal G1 decreases (IH=IH1+IH2→IH=IH2 only), so that the rise in the output voltage Vo becomes gentle.

Further, when the output voltage Vo increases and becomes Vo>VBB-VdsA (that is, Vds<VdsA) at time t4, SA=H. At this time, the controller 313 turns on the sink current source 312b. As a result, the differential current (=IH2-IL2<0) between the source current IH2 and the sink current IL2 is pulled out from the application terminal of the gate drive signal G1. turns from an increase to a decrease.

After that, when V0<VBB-VdsA (that is, Vds>VdsA) at time t5, SA=L. At this time, the controller 313 turns off the sink current source 312b. As a result, the gate drive signal G1 begins to rise again, and the output voltage Vo begins to rise gently. At times t5 to t6, the same operation as described above is repeated, so that the output voltage Vo is maintained at the threshold voltage VBB-VdsA. Such a state corresponds to a state in which full-on of the NMOSFET 10 is prevented and the drain-source voltage Vds is limited to a predetermined lower limit (=VdsA) or higher.

At time t6, when the external control signal Si falls to a low level (=logic level for turning off the NMOSFET 10), the controller 313 turns on the sink current source 312a, and the source current sources 311a and 311b and the sink current Turn off source 312b. As a result, the gate drive signal G1 is sharply lowered by the sink current IL1, so that the output voltage Vo also starts to drop sharply.

At time t7, when the output voltage Vo drops to the zero value, the sink current source 312a should be turned off.

By introducing the Vds limiting unit 100 in this manner, the drain-source voltage Vds of the NMOSFET 10 can be limited to a predetermined lower limit (=VdsA) or higher. Therefore, even when a load 3 (such as a light-emitting diode) that does not require a large output current Io is connected, the influence of the offset voltage Vofs of the operational amplifier 81 is reduced. generation accuracy) can be improved.

In addition, since the drain-source voltage Vds limiting operation (= full-on prevention operation of the NMOSFET 10) is activated only when the output current Io is small, there is no need to worry about abnormal heat generation of the NMOSFET 10.

In addition, by using a combination of large and small source currents IH1 and IH2, the output voltage Vo can be started at high speed (time t2 to t3) and the output voltage Vo during the limiting operation of the drain-source voltage Vds (time t4 to t6). overshoot suppression can be achieved.

<Vds Limiter (Second Embodiment)>
FIG. 7 is a diagram showing a second embodiment of the Vds limiter. In the Vds limiting unit 100 of the present embodiment, the previously described comparator 102 (FIG. 5) is omitted, and according to the comparison signal SA (=comparison result between output voltage Vo and predetermined threshold voltage VBB−VdsA), The drive voltage of the gate driver 31 (and the high level voltage of the gate drive signal G1) is switched.

More specifically, the driving voltage of the gate driver 31 is switched to the boosted voltage VG when SA=L (Vds>VdsA), and is switched to the boosted voltage VG when SA=H (Vds<VdsA). It is switched to a voltage (=VG-α) lower than VG. That is, when SA=H, the NMOSFET 10 is not fully turned on and its on-resistance value Ron is raised, so that the drain-source voltage Vds increases even if the output current Io is small.

According to the present embodiment, like the first embodiment (FIG. 5), the drain-source voltage Vds of the NMOSFET 10 can be limited to a predetermined lower limit (=VdsA) or higher. Therefore, even when a load 3 (such as a light-emitting diode) that does not require a large output current Io is connected, the influence of the offset voltage Vofs of the operational amplifier 81 is reduced. generation accuracy) can be improved.

<Vds Limiter (Third Embodiment)>
FIG. 8 is a diagram showing a third embodiment of the Vds limiter. As in the second embodiment (FIG. 7), the Vds limiter 100 of the present embodiment omits the previously described comparator 102 (FIG. 5). -VdsA), transistors used as the NMOSFET 10 (NMOSFETs 10a and 10b in this figure) are selected.

The drains of the NMOSFETs 10a and 10b are both connected to the external terminal T1. The sources of the NMOSFETs 10a and 10b are both connected to the external terminal T2. Also, the gate of the NMOSFET 10a is always connected to the application terminal of the gate drive signal G1. On the other hand, the gate of the NMOSFET 10b is connected to the application terminal of the gate drive signal G1 or the source of the NMOSFET 10b according to the comparison signal SA.

More specifically, when SA=L (Vds>VdsA), the gate of NMOSFET 10b is connected to the application terminal of gate drive signal G1. As a result, both NMOSFETs 10a and 10b are used as NMOSFET 10. FIG.

On the other hand, when SA=H (Vds<VdsA), the gate of NMOSFET 10b is connected to the source of NMOSFET 10b. As a result, only the NMOSFET 10 a is used as the NMOSFET 10 . That is, when SA=H, the on-resistance value Ron of the NMOSFET 10 is raised, so that the drain-source voltage Vds increases even if the output current Io is small.

According to the present embodiment, like the first embodiment (FIG. 5) and the second embodiment (FIG. 7), the drain-source voltage Vds of the NMOSFET 10 is limited to a predetermined lower limit (=VdsA) or more. be able to. Therefore, even when a load 3 (such as a light-emitting diode) that does not require a large output current Io is connected, the influence of the offset voltage Vofs of the operational amplifier 81 is reduced. generation accuracy) can be improved.

<Application to vehicles>
FIG. 9 is an external view showing one configuration example of the vehicle. A vehicle X of this configuration example is equipped with a battery (not shown in the drawing) and various electronic devices X11 to X18 that operate with power supplied from the battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a body control unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

Electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, and other electronic devices built into vehicle X at the factory shipment stage as standard equipment or manufacturer options. is.

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

The semiconductor integrated circuit device 1, the ECU 2, and the load 3 described above can be incorporated in any of the electronic devices X11 to X18.

<Other Modifications>
Further, in the above-described embodiments, the high-side switch ICs for automobiles have been described as an example, but the application of the invention disclosed herein is not limited to this. , and other vehicle-mounted IPDs (such as vehicle-mounted low-side switch ICs and vehicle-mounted power supply ICs), as well as semiconductor integrated circuit devices other than vehicle-mounted applications.

In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is indicated by the scope of claims rather than the description of the above-described embodiments. It should be understood that all changes that fall within the meaning and range of equivalency to the claims are included.

INDUSTRIAL APPLICABILITY The invention disclosed in this specification can be used for an in-vehicle IPD and the like.

1 Semiconductor integrated circuit device (switch device)
2 ECUs
3 load 4 external sense resistor 10, 10a, 10b NMOSFET (switch element)
20 output current monitoring unit 21, 21' NMOSFET
22 sense resistor 30 gate controller 31 gate driver 311, 311a, 311b source current source 312, 312a, 312b sink current source 313 controller 32 oscillator 33 charge pump (booster)
34 clamper (active clamp circuit)
35 NMOSFETs
36 resistor 37 capacitor 38 Zener diode (clamp element)
40 control logic unit 50 signal input unit 60 internal power supply unit 70 abnormality protection unit 71 overcurrent protection circuit (overcurrent protection unit)
72 open protection circuit 73 temperature protection circuit 74 undervoltage protection circuit 80 output current detector 81 operational amplifier 82 PMOSFET
90 signal output section 91 selector 100 Vds limiting section 101, 102 comparators 103, 104 resistors 105 current sources T1 to T4 external terminals X vehicle X11 to X18 electronic equipment

Claims (7)

a first switch connected between the first node and the second node;
a second switch having a first terminal connected to the first node and turned on/off by a drive signal shared with the first switch;
an output current detection unit that imaginarily shorts the second end of the second switch and the second node to generate a sense current corresponding to the output current flowing through the first switch;
a voltage limiter for limiting the voltage across the first switch to a predetermined lower limit or higher;
a driver that generates the drive signal;
has
The output stage of the driver includes a source current source that supplies a source current to the application terminal of the drive signal and a sink current source that draws a sink current from the application terminal of the drive signal,
The switching device, wherein the voltage limiter between both ends controls the source current source and the sink current source according to a comparison result between the output voltage of the second node and a predetermined threshold voltage. The sourcing current source includes a first sourcing current source that produces a first sourcing current and a second sourcing current source that produces a second sourcing current that is less than the first sourcing current, and the sinking current source comprises a second a first sink current source that produces one sink current and a second sink current source that produces a second sink current that is less than the first sink current and greater than the second sink current;
During the ON period of the first switch, when the output voltage is lower than the first threshold voltage, the first source current source and the second source current source are turned on and the first sink current source and the second sink current source are turned on. When the sink current source is turned off and the output voltage is higher than the first threshold voltage and lower than the second threshold voltage, the second source current source is turned on to turn on the first source current source and the second sink current. source and the second sink current source are turned off, and when the output voltage is higher than the second threshold voltage, the second source current source and the second sink current source are turned on to turn on the first source current source and the second sink current source. While the first sink current source is turned off, during the off period of the first switch, the first sink current source is turned on to generate the first source current source, the second source current source and the second sink current. 2. The switching device of claim 1, wherein the source is turned off. a first switch connected between the first node and the second node;
a second switch having a first terminal connected to the first node and turned on/off by a drive signal shared with the first switch;
an output current detection unit that imaginarily shorts the second end of the second switch and the second node to generate a sense current corresponding to the output current flowing through the first switch;
a voltage limiter for limiting the voltage across the first switch to a predetermined lower limit or more;
a driver that generates the drive signal;
has
The switching device, wherein the voltage limiter between both ends switches the drive voltage of the driver according to a comparison result between the output voltage of the second node and a predetermined threshold voltage. a first switch connected between the first node and the second node;
a second switch having a first terminal connected to the first node and turned on/off by a drive signal shared with the first switch;
an output current detection unit that imaginarily shorts the second end of the second switch and the second node to generate a sense current corresponding to the output current flowing through the first switch;
a voltage limiter for limiting the voltage across the first switch to a predetermined lower limit or higher;
has
the first switch includes a first transistor and a second transistor connected in parallel between the first node and the second node;
The voltage limiter between both terminals is in a first state in which both the first transistor and the second transistor are used as the first switch according to a comparison result between the output voltage of the second node and a predetermined threshold voltage. and a second state in which only the first transistor is used as the first switch. An electronic device comprising the switch device according to any one of claims 1 to 4 and a load connected to the switch device. 6. The electronic device according to claim 5, wherein said load is a bulb lamp, a relay coil, a solenoid, a light emitting diode, or a motor. A vehicle comprising the electronic device according to claim 5 or 6.

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